CN109524453B - GaN-based high-voltage rectification resonance tunneling diode - Google Patents
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/88—Tunnel-effect diodes
- H01L29/882—Resonant tunneling diodes, i.e. RTD, RTBD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0646—PN junctions
Abstract
The invention relates to a GaN-based high-voltage rectification resonance tunneling diode. The invention comprises
Surface GaN substrate, n+‑In0.07Ga0.93N collector layer, i-In0.07Ga0.93A first N isolation layer, a first AlGaN barrier layer, and i-In0.14Ga0.86N quantum well layer, GaN second barrier layer, i-In0.21Ga0.89N second isolation layer, N+‑In0.21Ga0.89N emission region layer, passivation layer, collecting region metal electrode pin and emission region metal electrode pin. The GaN-based high-voltage resonant tunneling diode-HVRTD has forward higher blocking voltage and reverse ultralow resistivity volt-ampere characteristics, is compatible with a micro-nano integration manufacturing process of a GaN-based integrated device and a circuit (comprising a circuit, an optical circuit, a magnetic circuit, an air circuit, a mechanical circuit and a composite circuit), is very suitable for ESD protection application of the GaN-based integrated device and the circuit, and can bear +/-2000V ESD within approximately ideal 840ns time to ensure that the GaN-based integrated device and the circuit are not damaged.
Description
Technical Field
The invention relates to the technical field of compound semiconductor quantum devices, in particular to a GaN-based high-voltage rectification resonance tunneling diode (HVRRTD).
Background
For a conventional GaN/AlGaN Resonant Tunneling Diode (RTD) device, a polarization electric field is formed in the GaN/AlGaN barrier layer due to the significant spontaneous polarization effect of the GaN/AlGaN barrier layer and the significant piezoelectric polarization effect under the action of an applied voltage. Because of the restriction of factors such as the internal structure of the GaN/AlGaN material, the surface epitaxial growth dynamics and the like, for the c-plane epitaxial growth, the initial polar plane and the final polar plane of the high-quality GaN/AlGaN nano film are the same. If on a GaN substrateThe surface is a c surface, namely the polarity of the Ga surface, the direction of a polarization electric field in the AlGaN barrier layer is the same as the direction of an electric field applied to the device, the resonant tunneling effect of the RTD device can be enhanced, and the method is favorable for obtaining stronger Negative Differential Resistance (NDR) volt-ampere characteristics under lower bias voltage under the condition of the electrodeless effect than that of a barrier layer, namely higher peak/valley current density; while if the upper surface of the GaN substrate is
The plane, i.e., N surface polarity, the polarization electric field direction in the AlGaN barrier layer is opposite to the direction of the electric field applied to the device, which suppresses or destroys the resonant tunneling effect of the RTD device, and it is difficult to obtain a significant practical Negative Differential Resistance (NDR) volt-ampere characteristic below a DC bias voltage of 5V. Also, the RT characteristics of the GaN-based symmetric Multiple Quantum Well (MQW) structure RTD are asymmetric about the origin of coordinates of the I-V plane due to the influence of the polarization effect. Therefore, the conventional GaN/AlGaN Resonant Tunneling Diode (RTD) device usually adopts a GaN substrate with a c-plane upper surface, can obtain obvious resonant tunneling characteristics in a 0-3V DC bias voltage range, and can be applied to a 3V DC/pulse power supply multi-valued logic circuit or an analog circuit.
There are mainly four common schemes for on-chip ESD protection of conventional semiconductor devices or integrated circuits:
(1) reverse series (also known as stacked) silicon ordinary diode protection circuits;
the scheme mainly combines the voltage stabilization and current leakage characteristics of the reverse bias diode when the reverse bias diode is impacted by reverse high-voltage pulse with the high-resistance characteristics under reverse low voltage and the low-resistance clamping characteristics under forward low voltage to prevent the protected circuit or device from being damaged by high-voltage stress. Under the condition of no high-voltage electrostatic discharge impact excitation, when a protected circuit or device works normally, the protection diode is blocked too much at low voltage, only extremely low leakage current exists, and the influence on the normal work of the protection diode is very little. When the forward bias of the diode occurs at the moment of pin signal inversion, the forward biased diode clamps the peak potential of the corresponding pin at a level slightly higher than the power supply potential or slightly lower than the ground potential, and the normal work of a protected circuit or a protected device is not influenced. Under the condition of high-voltage electrostatic discharge impact, one diode is subjected to voltage stabilization conduction, and the peak potential of the corresponding pin is clamped at the power supply potential + stable voltage amplitude or the ground potential-stable voltage amplitude. (if the stacked common diodes at the pins and some PN junctions of other parts in the chip are prepared synchronously and have the same bias direction, the PN junctions will have similar states.) so that the main disadvantages are reflected in two aspects, on one hand, the chip is easily burnt out due to high power consumption in the discharging process and high local temperature rise caused by high stable voltage and high stable current, and the chip is not suitable for ESD protection application of devices and circuits with high blocking voltage; on the other hand, the protection circuit can only realize partial protection, and certain areas inside the protected circuit or device still can be impacted by high-voltage electrostatic discharge.
(2) A silicon controlled rectifier (SCR/also called thyristor) protection circuit;
the SCR device adopted by the scheme needs a semiconductor device structure with more than 4 layers of 3 junctions, such as PNPN/NPNP/PNPNPNPNP/NPNPN and other structures, and the SCR device is not triggered to be conducted and presents a high-resistance state when a protected circuit or the device works normally by utilizing a positive feedback interconnection structure in a parasitic double/multiple transistor in the structure and combining a necessary trigger conduction mode; when high-voltage electrostatic discharge impact occurs, the SCR is triggered and conducted rapidly, and is in a low-voltage large-current distribution mode, so that the electrostatic amplitude can be limited at a lower power consumption and a higher speed, electrostatic charges can be discharged, and the ESD protection circuit is suitable for ESD protection of devices and circuits with a wider blocking voltage range. The main disadvantage is that the size of the SCR device is large, and a proper trigger control circuit needs to be equipped to prepare a semiconductor device structure with more than 4 layers and 3 junctions, so that the preparation process has high cost.
(3) A gate-grounded N-channel metal-oxide-semiconductor field effect transistor (GGNMOSFET) protection circuit;
the characteristics of such GGNMOSFET devices are somewhat similar to those of SCRs, with the main differences being: on one hand, the device size is smaller, the blocking voltage is lower, and the voltage backspacing amplitude after triggering and conducting is smaller, so that the conducting voltage drop is higher; on the other hand, the structure and the process are completely compatible with the advanced small-size CMOS process, and the process cost is lower.
(4) A silicon-based lateral double diffused metal-oxide-semiconductor field effect transistor (LDMOS) protection circuit.
The LDMOS device has high voltage resistance and low on-state voltage drop compared with the SCR and the GGNMOSFET, belongs to a voltage driving type, needs to be provided with a necessary driving circuit, is quickly started, has low over-current density and occupies a larger chip area. Therefore, the LDMOS device is relatively suitable for low-power consumption ESD protection of a high-voltage circuit.
The core protection devices adopted by the ESD protection scheme are all silicon-based devices, and although the ESD protection scheme is widely applied to ESD protection of silicon-based integrated devices and circuits, the ESD protection scheme is difficult to be directly applied to ESD protection of GaN-based integrated devices and integrated circuits due to the problem of process compatibility.
Aiming at the defects, the invention utilizes a quantum size effect, an energy band engineering method, a heterojunction quantum well structure and a polarization field combined quantum regulation and control electron dredging method to adopt Molecular Beam Epitaxy (MBE) growth or Metal Organic Chemical Vapor Deposition (MOCVD) epitaxial growth
A high-quality wurtzite GaN material substrate on the surface; FIG. 1 shows a wurtzite four-axis coordinate system, that is, a three-dimensional space represented by a four-axis coordinate system is formed by taking a1, a2, a3 and c axes as four coordinate axes, and the obtained three-dimensional space is
Sequentially epitaxially growing n in the vertical direction of the initial crystal orientation of the surface GaN substrate through subsequent MBE or MOCVD+-In0.07Ga0.93N、i-In0.07Ga0.93N、i-AlGaN、i-In0.14Ga0.86N、i-GaN、i-In0.21Ga0.79N、n+-In0.21Ga0.79N, then etching N in sequence+-In0.21Ga0.79N、i-In0.21Ga0.79N、i-GaN、i-In0.14Ga0.86N、i-Al0.1Ga0.9N、i-In0.07Ga0.93N、n+-In0.07Ga0.93N, followed by precipitationA GaN-based High Voltage Rectification RTD (HVRRTD) device having a higher voltage blocking characteristic in one direction and a low voltage large current distribution characteristic in the other direction is prepared by depositing a metal film and etching back the metal film, and the structure of the device is shown in figure 2. The HVRRTD device is very suitable for ESD protection of GaN-based integrated devices and integrated circuits, can complete +/-2000V ESD within 0.84 mu s, and has an ESD protection circuit topology shown in figure 3, so that the integrated devices or the circuits are protected from ESD damage.
Disclosure of Invention
The invention aims to provide a GaN-based high-voltage rectification resonance tunneling diode.
The invention comprises
Surface GaN substrate 1, n+-In0.07Ga0.93 N collector layer 2, i-In0.07Ga0.93A first N isolation layer 3, a first AlGaN barrier layer 4, i-In0.14Ga0.86N quantum well layer 5, GaN second barrier layer 6, i-In0.21Ga0.79N second isolation layer 7, N+-In0.21Ga0.79N emitter region layer 8, passivation layer 9, collector region metal electrode pin 10 and emitter region metal electrode pin 11.
The substrate has a thickness of 102-103The number of the i-GaN layer and the collector region layer of the micron meter is 10-2-100N of μm thickness+-In0.07Ga0.93N layer, first isolation layer is 100-101nm thick i-In0.07Ga0.93The N layer and the first barrier layer are i-Al with the thickness of 1.5-6nm0.1Ga0.9The N layer and the quantum well layer are 1.5-3nm thick i-In0.14Ga0.86N layer, i-GaN layer with second barrier layer thickness of 1.5-6nm, and second isolation layer of 0-101nm thick i-In0.21Ga0.79N layer, emitter layer 10-2-100N of μm thickness+-In0.21Ga0.79N layer, passivation layer 101AlN and Si with nm thickness3N4Or a silicon oxide layer. N in the emitter layer+-In0.21Ga0.79The N doping concentration is 1e18-1e19cm-3N in the collector layer+-In0.07Ga0.93The N doping concentration is 1e18-1e19cm-3。
The GaN substrate is used as a device carrier, and plays roles in determining the epitaxial growth direction of the device layer, supporting the device layer, isolating devices in the device layer, assisting the heat dissipation of the devices in work and the like;
n+-In0.07Ga0.93ohmic contact is formed between the outer region of the upper surface of the N collector region layer and the metal electrode of the collector region through heavily doping N+-In0.07Ga0.93N collector region layer collection and transmission first isolation layer i-In0.07Ga0.93Electron flow of the N layer; in thermal terms, n+-In0.07Ga0.93The N collector region layer is used as a first isolation layer I-In0.07Ga0.93A heat conduction medium is arranged between the N layer and the semi-insulating i-GaN substrate and between the N layer and the collector region metal electrode pins;
first isolation layer i-In0.07Ga0.93N layer connecting N on the device structure+-In0.07Ga0.93N collector region layer and first barrier layer i-Al0.1Ga0.9N layer of i-Al mainly penetrating the first barrier layer0.1Ga0.9The electrons of the N layer provide a transport path to the collector layer as N+-In0.07Ga0.93N collector region layer and first barrier layer i-Al0.1Ga0.9Heat transfer path between N layers, buffered heavy doping N+-In0.07Ga0.93I-Al of first barrier layer of N collector region layer electron direction0.1Ga0.9Diffusion in the N layer direction, and isolation of N+-In0.07Ga0.93I-Al of first barrier layer of quantum energy level pair in N collector region layer0.1Ga0.9The influence of quantum energy level relations at two sides of the N layer, the quantum regulation and control for assisting the electron transportation under the external bias voltage and the like;
first barrier layer i-Al0.1Ga0.9The N layer structurally isolates the first isolation layer i-In0.07Ga0.93N layer and i-In0.14Ga0.86N quantum well layer as first isolation layer i-In0.07Ga0.93N layer and i-In0.14Ga0.86The nanoscale thickness finite high barrier between the N quantum well layers, i.e. the first isolation layer i-In0.07Ga0.93N layer and i-In0.14Ga0.86Coulomb blockage and path of electron quantum resonant tunneling between the N quantum well layers;
i-In0.14Ga0.86the N quantum well layer is arranged between the first barrier layer i-Al0.1Ga0.9Between the N layer and the second barrier layer i-GaN layer, as the electron quantum well with limited depth and nanometer thickness, i-In is formed by quantum size effect0.14Ga0.86A discrete or quasi-continuous electron spectrum with a position-energy space quantized longitudinally along the energy direction in the N quantum well;
the second barrier layer I-GaN layer structurally isolates I-In0.14Ga0.86N quantum well layer and second isolation layer i-In0.21Ga0.79N layer as i-In0.14Ga0.86N quantum well layer and second isolation layer i-In0.21Ga0.79A nano-scale thickness finite high barrier between N layers, i.e. i-In0.14Ga0.86N quantum well layer and second isolation layer i-In0.21Ga0.79Coulomb blocking and path of electron quantum resonance tunneling between N layers;
second isolation layer i-In0.21Ga0.79The N layer is connected with the second barrier layer i-GaN layer and the N layer on the device structure+-In0.21Ga0.79N emitter layer, transporting mainly N from+-In0.21Ga0.79Electrons of the N emitter layer as the second barrier layer i-GaN layer and N+-In0.21Ga0.79Heat transfer path between N emitter layers, isolating N+-In0.21Ga0.79The influence of the quantum energy level in the N emission region layer on the quantum energy level relation on two sides of the second barrier layer i-GaN layer, the quantum regulation and control for assisting the electron transportation under the external bias and the like;
n+-In0.21Ga0.79an emitter ohmic contact is formed between the N emitter region layer and the metal electrode pin of the emitter region, and the second isolation layer i-In is connected0.21Ga0.79N layer and metal electrode pin of emitter region as second isolation layer i-In0.21Ga0.79A low resistance path and a heat transmission path of electron flow between the N layer and the metal electrode pin of the emission region.
Ohmic contact is formed between the metal electrode pin in the collector region and the collector region, and the collector region of the device is connected with an external circuit.
AlN、Si3N4Or SiO2The passivation layer isolates a part of the surface of the device, which needs to be protected, from the external environment and the electrodes, and passivates surface dangling bonds, thereby reducing the effects of surface leakage of the device and the like.
The AlN and Si3N4Or SiO2The passivation layer, the metal electrode pins in the collector region and the metal electrode pins in the emitter region form three concentric circles or concentric regular polygons.
And the emission region layer, the second isolation layer, the second barrier layer, the quantum well layer, the first barrier layer and the first isolation layer on the periphery of the core quantum structure region are realized by sequentially masking and selectively etching back by adopting a photoetching process after the extension of all device layers is finished.
The AlN and Si3N4Or SiO2The passivation layer is deposited on the outer upper surface and the side surface of the quantum structure region; then, an electrode contact opening at the etching part of the metal electrode contact hole mask of the emitting area/the collecting area is adopted, a metal film electrode is deposited and alloyed, and a metal electrode pin is formed by reverse etching of the metal electrode mask.
The upper surfaces of the collector region metal electrode pins and the emitter region metal electrode pins are flattened by adopting a chemical mechanical polishing process.
Aiming at the defects of the prior art, the GaN-based high-voltage resonant tunneling diode-HVRRTD with the forward high-voltage blocking characteristic and the reverse high-speed conduction characteristic is provided by adopting an InGaN/GaN/InGaN/AlGaN/InGaN double barrier quantum well structure based on a GaN-based micro-nano integrated device and a circuit technology. The electrical characteristics of the HVRRTD are particularly suitable for on-chip ESD protection application of GaN-based integrated devices and circuits, and can realize Human Body Mode (HBM) +/-2000V ESD discharge in an ideal 840ns time, so that the integrated devices and circuits to be protected are prevented from being damaged by the ESD, the compatibility of an integration manufacturing process is good, and the difficulty and trouble of adopting a silicon-based ESD protection device to protect the GaN-based integrated devices and circuits are avoided.
Drawings
FIG. 1 is a four-axis coordinate system of wurtzite;
FIG. 2 is a schematic view of the overall structure of the present invention;
FIG. 3 is a circuit topology diagram of the present invention applied to ESD protection of GaN-based integrated devices and I/O ports of a circuit;
fig. 4 is a schematic cross-sectional structure of an embodiment of the present invention.
Detailed Description
As shown in figure 2, the GaN-based high-voltage rectification resonance tunneling diode (HVRRTD) comprises an i-GaN semi-insulating substrate 1,n+-In0.07Ga0.93 N collector layer 2, i-In0.07Ga0.93N first isolation layer 3, i-Al0.1Ga0.9Nfirst barrier layer 4, i-In0.14Ga0.86N quantum well layer 5, i-GaN second barrier layer 6, i-In0.21Ga0.79N second isolation layer 7, N+-In0.21Ga0.79 N emitter layer 8, AlN, Si3N4Or SiO2Passivation layer 9, collector region metal electrode pin 10 and emitter region metal electrode pin 11. 300-500 mu m thick i-GaN substrate 1, 0.1-0.5 mu m thick n+-In0.07Ga0.93N collector region layer 2, i-In with the thickness of 24-60nm is extended on the middle part of the upper surface of the collector region layer 20.07Ga0.93N first isolation layer 3, 1.5-6nm thick i-Al0.1Ga0.9N first barrier layer 4, 1.5-3nm thick i-In0.14Ga0.86An N quantum well layer 5, an i-GaN second barrier layer 6 with the thickness of 1.5-6nm, and i-In with the thickness of 24-60nm0.21Ga0.79N second isolation layer 7 and 0.1-0.5 μm thick N+-In0.07Ga0.93An N emitter region layer 8; wherein, i-In0.07Ga0.93N first isolation layer 3, i-Al0.1Ga0.9Nfirst barrier layer 4, i-In0.14Ga0.86N quantum well layer 5, i-GaN second barrier layer 6, i-In0.21Ga0.79The N second isolation layer 7 forms a core quantum structure region of the high-voltage resonant tunneling diode. The upper surface of the core quantum structure region is n+-In0.21Ga0.79An N emitting region layer 8 with AlN and Si of 0.3-0.5 μm thickness deposited outside the core quantum structure region3N4Or SiO2Passivation layer 9, respectively at n using a passivation layer reverse etching mask+-In0.07Ga0.93Outer side of upper surface of N collector layer 2 and N+-In0.21Ga0.79Contact holes of a collector region metal electrode pin 10 and an emitter region metal electrode pin 11 are etched in the center of the upper surface of the N emitter region layer 8; depositing a metal film, forming a collector region metal electrode pin 10 and an emitter region metal electrode pin 11 with the thickness of 0.3-0.5 mu m by reverse etching by using a contact hole mask, and applying the CMP (chemical mechanical polishing) process to the upper surface of the HVRRTD device unitAnd (6) flattening the surface.
The GaN substrate is used as a device carrier, and plays roles in determining the epitaxial growth direction of the device layer, supporting the device layer, isolating devices in the device layer, assisting the heat dissipation of the devices in work and the like; n in collector layer+-In0.07Ga0.93 N collector layers 2 and N+-In0.21Ga0.79The doping concentration of the N emitter region layer 8 is 1e18-1e19cm-3。
n+-In0.07Ga0.93Ohmic contact is formed between the outer region of the upper surface of the N collector region layer and the metal electrode of the collector region through heavily doping N+-In0.07Ga0.93N collector region layer collection and transmission first isolation layer i-In0.07Ga0.93Electron flow of the N layer; in thermal terms, n+-In0.07Ga0.93The N collector region layer is used as a first isolation layer i-In0.07Ga0.93A heat conduction medium is arranged between the N layer and the semi-insulating i-GaN substrate and between the N layer and the collector region metal electrode pins;
first isolation layer i-In0.07Ga0.93N layer connecting N on the device structure+-In0.07Ga0.93N collector region layer and first barrier layer i-Al0.1Ga0.9N layer of i-Al mainly penetrating the first barrier layer0.1Ga0.9The electrons of the N layer provide a transport path to the collector layer as N+-In0.07Ga0.93N collector region layer and first barrier layer i-Al0.1Ga0.9Heat transfer path between N layers, buffered heavy doping N+-In0.07Ga0.93I-Al of first barrier layer of N collector region layer electron direction0.1Ga0.9Diffusion in the N layer direction, and isolation of N+-In0.07Ga0.93I-Al of first barrier layer of quantum energy level pair in N collector region layer0.1Ga0.9The influence of quantum energy level relations at two sides of the N layer, the quantum regulation and control for assisting the electron transportation under the external bias voltage and the like;
first barrier layer i-Al0.1Ga0.9The N layer structurally isolates the first isolation layer i-In0.07Ga0.93N layer and i-In0.14Ga0.86N quantum well layer as first isolation layer i-In0.07Ga0.93N layer and i-In0.14Ga0.86The nanoscale thickness finite high barrier between the N quantum well layers, i.e. the first isolation layer i-In0.07Ga0.93N layer and i-In0.14Ga0.86Coulomb blockage and path of electron quantum resonant tunneling between the N quantum well layers;
i-In0.14Ga0.86the N quantum well layer is arranged between the first barrier layer i-Al0.1Ga0.9Between the N layer and the second barrier layer i-GaN layer, as the electron quantum well with limited depth and nanometer thickness, i-In is formed by quantum size effect0.14Ga0.86A discrete or quasi-continuous electron spectrum with a position-energy space quantized longitudinally along the energy direction in the N quantum well;
the second barrier layer i-GaN layer structurally isolates i-In0.14Ga0.86N quantum well layer and second isolation layer i-In0.21Ga0.79N layer as i-In0.14Ga0.86N quantum well layer and second isolation layer i-In0.21Ga0.79A nano-scale thickness finite high barrier between N layers, i.e. i-In0.14Ga0.86N quantum well layer and second isolation layer i-In0.21Ga0.79Coulomb blocking and path of electron quantum resonance tunneling between N layers;
second isolation layer i-In0.21Ga0.79The N layer is connected with the second barrier layer i-GaN layer and the N layer on the device structure+-In0.21Ga0.79N emitter layer, transporting mainly N from+-In0.21Ga0.79Electrons of the N emitter layer as the second barrier layer i-GaN layer and N+-In0.21Ga0.79Heat transfer path between N emitter layers, isolating N+-In0.21Ga0.79The influence of the quantum energy level in the N emission region layer on the quantum energy level relation on two sides of the second barrier layer i-GaN layer, the quantum regulation and control for assisting the electron transportation under the external bias and the like;
n+-In0.21Ga0.79the N emitting region layer and the emitting region metal electrode pin form a light emitting deviceEmitter ohmic contact connected to the second isolation layer i-In0.21Ga0.79N layer and metal electrode pin of emitter region as second isolation layer i-In0.21Ga0.79A low resistance path and a heat transmission path of electron flow between the N layer and the metal electrode pin of the emission region.
Ohmic contact is formed between the metal electrode pin in the collector region and the collector region, and the collector region of the device is connected with an external circuit.
AlN、Si3N4Or SiO2The passivation layer isolates a part of the surface of the device, which needs to be protected, from the external environment and the electrodes, and passivates surface dangling bonds, thereby reducing the effects of surface leakage of the device and the like.
AlN、Si3N4Or SiO2The passivation layer, the metal electrode pins in the collector region and the metal electrode pins in the emitter region form three concentric circles or concentric regular polygons.
And the emission region layer, the second isolation layer, the second barrier layer, the quantum well layer, the first barrier layer and the first isolation layer on the periphery of the core quantum structure region are realized by sequentially masking and selectively etching back by adopting a photoetching process after the extension of all device layers is completed.
AlN、Si3N4Or SiO2The passivation layer is deposited on the outer upper surface and the side surface of the quantum structure region; and depositing a metal film electrode, alloying and reversely etching by adopting a metal electrode mask to form a metal electrode pin.
And the upper surfaces of the metal electrode pins of the collector region and the metal electrode pins of the emitter region are flattened by adopting a chemical mechanical polishing process.
FIG. 3 shows a circuit topology of the present invention applied to ESD protection of the I/O port of GaN-based integrated device and circuit. When the switches SW2 and SW3 in fig. 3 are open and SW1 is closed, the 2000V voltage source charges the left capacitor Cesd to 2000V through the resistor R3, and then the switch SW1 is opened; when the switches SW1 and SW3 are opened and SW2 is closed, the-2000V voltage source charges the right capacitor Cesd to-2000V through the resistor R3, and then the switch SW1 is opened; when the SW1 and the SW2 are opened and the SW3 is closed to the electric shock 1, the equivalent is that a device to be tested or a chip induces 2000V electrostatic shock instantly, the charges stored in the left capacitor Cesd are discharged to the +5V power supply generalized loop and the SW3 resistor R1-D2 to the ground generalized loop through the switch SW 3-the resistor R1-D1 at the same time, and the electrostatic discharge process is equivalent to first-order RC zero input response; when the SW1 and the SW2 are opened, and the SW3 is closed to the electric shock 2, the equivalent is that a device to be tested or a chip induces-2000V electrostatic shock instantly, the charges stored in the right capacitor Cesd are discharged to the +5V power supply generalized loop and the SW 3-the resistor R1-D2 to the ground generalized loop through the switch SW 3-the resistor R1-D1, and the electrostatic discharge process is also equivalent to first-order RC zero input response.
FIG. 4 shows the results of TCAD testing of the voltage-current characteristics of 3 GaN-based high-voltage resonant tunneling diode-HVRRTD samples according to this example. It can be seen that: the forward blocking voltage can reach more than 7.2V, the reverse blocking voltage can be quickly conducted, the large current transmission bias voltage is not higher than 2.7V, the on-state resistance is extremely low, the on-state resistance can be ignored compared with the 1.5k omega electrostatic discharge resistance in a human body mode speaking point discharge model, and the ESD protection circuit is just suitable for ESD protection application of GaN-based semiconductor devices and chips below a +/-5V power supply.
Claims (5)
1. A GaN-based high-voltage rectification resonance tunneling diode is characterized in that: comprises that
Surface GaN substrate, n+-In0.07Ga0.93N collector layer, i-In0.07Ga0.93A first N isolation layer, a first AlGaN barrier layer, and i-In0.14Ga0.86N quantum well layer, GaN second barrier layer, i-In0.21Ga0.79N second isolation layer, N+-In0.21Ga0.79N emission region layers, passivation layers, collector region metal electrode pins and emission region metal electrode pins; said
Epitaxial n on upper surface of surface GaN substrate+-In0.07Ga0.93N collector layer，n+-In0.07Ga0.93Sequentially extending i-In on the upper surface of the N collector region layer0.07Ga0.93A first N isolation layer, a first AlGaN barrier layer, and i-In0.14Ga0.86N quantum well layer, GaN second barrier layer, i-In0.21Ga0.79N second isolation layer and N+-In0.21Ga0.79An N emitter region layer; n is+-In0.07Ga0.93N collector layer, i-In0.07Ga0.93N first isolation layer, i-Al0.1Ga0.9N first barrier layer, i-In0.14Ga0.86N quantum well layer, i-GaN second barrier layer, and i-In0.21Ga0.79N second isolation layer, N+-In0.21Ga0.79The N emitting region layer forms a core quantum structure region of the resonant tunneling diode; the upper surface of the core quantum structure region is provided with an emitting region metal electrode pin, the outer side of the core quantum structure region is deposited with a passivation layer, and the outer side of the passivation layer is provided with a collecting region metal electrode pin;
the substrate has a thickness of 102-103The number of the i-GaN layer and the collector region layer of the micron meter is 10-2-100N of μm thickness+-In0.07Ga0.93N layer, first isolation layer is 100-101nm thick i-In0.07Ga0.93The N layer and the first barrier layer are i-Al with the thickness of 1.5-6nm0.1Ga0.9The N layer and the quantum well layer are 1.5-3nm thick i-In0.14Ga0.86N layer, i-GaN layer with second barrier layer thickness of 1.5-6nm, and second isolation layer of 0-101nm thick i-In0.21Ga0.79N layer, emitter layer 10-2-100N of μm thickness+-In0.21Ga0.79N layer, passivation layer 101AlN and Si with nm thickness3N4Or a silicon oxide layer; n in the emitter layer+-In0.21Ga0.79The N doping concentration is 1e18-1e19cm-3N in the collector layer+-In0.07Ga0.93The N doping concentration is 1e18-1e19cm-3；
The GaN substrate is used as a device carrier, and plays roles in determining the epitaxial growth direction of the device layer, supporting the device layer, isolating devices in the device layer and dissipating heat of the devices in auxiliary work;
n+-In0.07Ga0.93ohmic contact is formed between the outer region of the upper surface of the N collector region layer and the metal electrode of the collector region through heavily doping N+-In0.07Ga0.93N collector region layer collection and transmission first isolation layer i-In0.07Ga0.93Electron flow of the N layer; in thermal terms, n+-In0.07Ga0.93The N collector region layer is used as a first isolation layer i-In0.07Ga0.93A heat conduction medium is arranged between the N layer and the semi-insulating i-GaN substrate and between the N layer and the collector region metal electrode pins;
first isolation layer i-In0.07Ga0.93N layer connecting N on the device structure+-In0.07Ga0.93N collector region layer and first barrier layer i-Al0.1Ga0.9N layer of i-Al mainly penetrating the first barrier layer0.1Ga0.9The electrons of the N layer provide a transport path to the collector layer as N+-In0.07Ga0.93N collector region layer and first barrier layer i-Al0.1Ga0.9Heat transfer path between N layers, buffered heavy doping N+-In0.07Ga0.93I-Al of first barrier layer of N collector region layer electron direction0.1Ga0.9Diffusion in the N layer direction, and isolation of N+-In0.07Ga0.93I-Al of first barrier layer of quantum energy level pair in N collector region layer0.1Ga0.9The influence of quantum energy level relations at two sides of the N layer and the quantum regulation and control function of assisting electron distribution under the external bias voltage;
first barrier layer i-Al0.1Ga0.9The N layer structurally isolates the first isolation layer i-In0.07Ga0.93N layer and i-In0.14Ga0.86N quantum well layer as first isolation layer i-In0.07Ga0.93N layer and i-In0.14Ga0.86The nanoscale thickness finite high barrier between the N quantum well layers, i.e. the first isolation layer i-In0.07Ga0.93N layer and i-In0.14Ga0.86Coulomb of electron quantum resonant tunneling between N quantum well layersBlocking and routing;
i-In0.14Ga0.86the N quantum well layer is arranged between the first barrier layer i-Al0.1Ga0.9Between the N layer and the second barrier layer i-GaN layer, as the electron quantum well with limited depth and nanometer thickness, i-In is formed by quantum size effect0.14Ga0.86A discrete or quasi-continuous electron spectrum with a position-energy space quantized longitudinally along the energy direction in the N quantum well;
the second barrier layer i-GaN layer structurally isolates i-In0.14Ga0.86N quantum well layer and second isolation layer i-In0.21Ga0.79N layer as i-In0.14Ga0.86N quantum well layer and second isolation layer i-In0.21Ga0.79A nano-scale thickness finite high barrier between N layers, i.e. i-In0.14Ga0.86N quantum well layer and second isolation layer i-In0.21Ga0.79Coulomb blocking and path of electron quantum resonance tunneling between N layers;
second isolation layer i-In0.21Ga0.79The N layer is connected with the second barrier layer i-GaN layer and the N layer on the device structure+-In0.21Ga0.79N emitter layer, transporting mainly N from+-In0.21Ga0.79Electrons of the N emitter layer as the second barrier layer i-GaN layer and N+-In0.21Ga0.79Heat transfer path between N emitter layers, isolating N+-In0.21Ga0.79The influence of the quantum energy level in the N emission region layer on the quantum energy level relation on two sides of the second barrier layer i-GaN layer and the quantum regulation and control function for assisting the electron transportation under the external bias voltage are realized;
n+-In0.21Ga0.79an emitter ohmic contact is formed between the N emitter region layer and the metal electrode pin of the emitter region, and the second isolation layer i-In is connected0.21Ga0.79N layer and metal electrode pin of emitter region as second isolation layer i-In0.21Ga0.79A low resistance path and a heat transmission path of electron flow between the N layer and the metal electrode pin of the emission region;
ohmic contact is formed between the metal electrode pin of the collector region and the collector region, and the collector region of the device is connected with an external circuit;
AlN、Si3N4or SiO2The passivation layer isolates the part of the surface of the device needing protection from the external environment and the electrodes, and passivates the surface dangling bond, thereby reducing the surface leakage effect of the device.
2. The GaN-based high voltage rectifying resonant tunneling diode of claim 1, wherein: the AlN and Si3N4Or SiO2The passivation layer, the metal electrode pins in the collector region and the metal electrode pins in the emitter region form three concentric circles or concentric regular polygons.
3. The GaN-based high voltage rectifying resonant tunneling diode of claim 1, wherein: and the emission region layer, the second isolation layer, the second barrier layer, the quantum well layer, the first barrier layer and the first isolation layer on the periphery of the core quantum structure region are realized by sequentially masking and selectively etching back by adopting a photoetching process after the extension of all device layers is finished.
4. The GaN-based high voltage rectifying resonant tunneling diode of claim 1, wherein: the AlN and Si3N4Or SiO2The passivation layer is deposited on the outer upper surface and the side surface of the quantum structure region; and depositing a metal film electrode, alloying and reversely etching by adopting a metal electrode mask to form a metal electrode pin.
5. The GaN-based high-voltage rectifying resonant tunneling diode of claim 4, wherein: the upper surfaces of the collector region metal electrode pins and the emitter region metal electrode pins are flattened by adopting a chemical mechanical polishing process.
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