CN109524038B - Single-event upset reinforced storage unit and storage array - Google Patents
Single-event upset reinforced storage unit and storage array Download PDFInfo
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- CN109524038B CN109524038B CN201811222394.XA CN201811222394A CN109524038B CN 109524038 B CN109524038 B CN 109524038B CN 201811222394 A CN201811222394 A CN 201811222394A CN 109524038 B CN109524038 B CN 109524038B
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Abstract
The embodiment of the invention discloses a single-particle upset reinforced storage unit, and belongs to the field of integrated circuit anti-irradiation design. The storage unit comprises a first storage unit, a second storage unit and a first isolation unit, wherein the first isolation unit is used for isolating the first storage unit from the second storage unit; the cross coupling unit is used for separating or combining signals and providing feedback for the first isolation unit; the bias unit is used for providing bias voltage for the first isolation unit and the cross coupling unit; and a second isolation unit for isolating the cross-coupling unit and the bias unit. According to the scheme, the first isolation unit is additionally arranged on the common storage unit to form a main storage unit, the redundant storage node is introduced, and information is stored through the mutual feedback effect among different units, so that the storage unit has quicker turnover recovery time. The embodiment of the invention also discloses a storage array.
Description
Technical Field
The invention belongs to the technical field of integrated circuit anti-irradiation design, and particularly relates to a single-particle upset reinforced storage unit and a single-particle upset reinforced storage array.
Background
With the development of space technology, nuclear technology, and strategic weaponry, various electronic devices have been widely used in satellite vehicles, space vehicles, launch vehicles, remote missiles, and nuclear weapon control systems. The integration of semiconductor devices for spacecraft is continuously improved, the characteristic size is smaller and smaller, the working voltage is lower and smaller, correspondingly, the critical charge is smaller and smaller, and the single event effect is easier and easier to occur.
Single event upset is the most common single event effect in integrated circuits under irradiation conditions, which can cause data errors in memory cells. The radiation resistance of the memory cell as a basic instruction memory device of the electronic control systems is particularly important, because the data stored in the device can directly cause system failure once the data is in error. Therefore, ruggedization of memory cells is a crucial issue that needs to be addressed for space electronics applications.
However, in the current common scheme of irradiation-resistant reinforcement, the process reinforcement can effectively reduce the charge collection on a single particle track, but the manufacturing cost is high, the selectable process lines are few, and most of various reinforcement schemes have the problems that the turnover is not easy to recover or the turnover recovery time is long.
Disclosure of Invention
The embodiment of the invention provides a single event upset reinforced storage unit and a storage array, wherein after one node is overturned, the level of an inversion node can be fed back through other nodes, so that the storage unit has shorter overturn recovery time.
The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.
According to a first aspect of the embodiments of the present invention, a single event upset ruggedized memory cell is provided.
In some optional embodiments, the single event upset strengthened memory cell provided by the present application includes a first memory cell and a second memory cell, and further includes: the first isolation unit is used for isolating the first storage unit from the second storage unit; the cross coupling unit is used for separating or combining signals and providing feedback for the first isolation unit; the bias unit is used for providing bias voltage for the first isolation unit and the cross coupling unit; and a second isolation unit for isolating the cross-coupling unit and the bias unit.
According to a second aspect of the invention, a memory array is provided.
In some optional embodiments, the memory array includes a plurality of the above-mentioned single event upset reinforced memory cell memory cells, and the memory cells are arranged in rows and columns; also includes a plurality of bit lines and word lines; the memory cells in the same row share a word line, and the memory cells in the same column share a bit line.
By adopting the optional embodiment, the first isolation unit is additionally arranged in the common storage unit to form a main storage unit, the redundant storage nodes are introduced, the stored information is reinforced through the mutual feedback effect among different units, when any node in a single storage unit is in state reversal, the reversal node can recover the normal level of the node through the feedback of other nodes in the storage unit and the conduction of the associated pipeline, the anti-single-particle reinforcement of the internal node is realized, the single storage unit has quicker reversal recovery time, the anti-single-particle reinforcement of the storage unit in the storage array formed by the storage units can be further realized, and the integral single-particle reversal recovery time of the storage array is quicker.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
FIG. 1 is a schematic diagram of an alternative embodiment of a single event upset ruggedized memory cell
FIG. 2 is a circuit diagram of an alternative embodiment of a single event upset ruggedized memory cell.
FIG. 3 is a circuit diagram of another alternative embodiment of a single event upset ruggedized memory cell.
The memory cell comprises a 1-first memory cell, a 2-second memory cell, a 3-first isolation cell, a 4-cross coupling cell, a 5-second isolation cell and a 6-biasing cell.
Detailed Description
The following description and the drawings sufficiently illustrate specific embodiments of the invention to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. The examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. The scope of embodiments of the invention encompasses the full ambit of the claims, as well as all available equivalents of the claims. Embodiments may be referred to herein, individually or collectively, by the term "invention" merely for convenience and without intending to voluntarily limit the scope of this application to any single invention or inventive concept if more than one is in fact disclosed. Herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method or apparatus that comprises the element. The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. As for the methods, products and the like disclosed by the embodiments, the description is simple because the methods correspond to the method parts disclosed by the embodiments, and the related parts can be referred to the method parts for description.
FIG. 1 illustrates an alternative embodiment of a single event upset ruggedized memory cell provided by the present invention.
In this optional embodiment, the single event upset hardened memory cell includes:
a first isolation unit 3 for isolating the first memory unit 1 and the second memory unit 2;
the cross coupling unit 4 is used for separating or combining signals and providing feedback for the first isolation unit 3;
a bias unit 6 for providing bias voltages to the first isolation unit 3 and the cross-coupling unit 4; and
a second isolation unit 5 for isolating the cross-coupling unit 4 and the bias unit 6; wherein the content of the first and second substances,
the first isolation unit 3 includes a first storage node Q, a second storage node Qb; the input end of the first isolation unit 3 is connected with the first storage unit 1, and the output end of the first isolation unit is connected with the second storage unit 2;
the cross-coupling unit 4 includes a first node n1, a second node n 2; the input end of the cross coupling unit 4 is connected with a power supply, and the output end of the cross coupling unit is connected with the input end of the second isolation unit 5; the first isolation unit 3 and the cross coupling unit 4 are connected to the first node n1 and the second node n 2;
the output end of the second isolation unit 5 is connected with the input end of the bias unit 6; the second isolation unit 5 is connected to the first storage node Q and the second storage node Qb;
the output end of the bias unit 6 is grounded; the bias unit 6 and the first isolation unit 3 are connected to the first storage node Q and the second storage node Qb;
the states of the first node n1 and the second node n2 are related to the states of the second isolation unit 5 and the bias unit 6; the first node n1 and the second node n2 control the state of the first isolation unit 3; the first and second storage nodes Q and Qb control the on state of the bias unit 6.
Optionally, the first isolation unit 3 includes a seventh transistor MP7 and an eighth transistor MP8, and the first storage node Q and the second storage node Qb are disposed between the seventh transistor MP7 and the eighth transistor MP 8; the seventh transistor MP7 is connected to the first node n1, and the eighth transistor MP8 is connected to the second node n 2.
Optionally, the seventh Transistor MP7 and the eighth Transistor MP8 are Metal-Oxide-Semiconductor Field-Effect transistors MOSFET, Metal-Oxide-Semiconductor Field-Effect Transistor.
Specifically, the seventh transistor MP7 and the eighth transistor MP8 are PMOS, Positive Channel Metal-Oxide-Semiconductor transistors.
Optionally, the cross-coupling unit 4 further includes a first transistor MP1 and a second transistor MP2, where the first transistor MP1 and the second transistor MP2 are both PMOS transistors;
specifically, the source of the first transistor MP1 is connected to the power supply, the drain is connected to the second isolation unit 5, and the gate is connected to the drain of the second transistor MP2 to the second node n 2;
the source of the second transistor MP2 is connected to the power source, the drain is connected to the second isolation unit 5, and the gate is connected to the drain of the first transistor MP1 to the first node n 1.
Optionally, the main storage unit includes a first isolation unit 3, a first storage unit 1, a second storage unit 2, a first storage node Q, and a second storage node Qb;
the first memory cell 1 includes a third transistor MP3 and a fourth transistor MP 4; the second memory cell 2 comprises a fifth transistor MN5, a sixth transistor MN 6;
the source of the third transistor MP3 is connected to the power supply, the drain is connected to the drain of the seventh transistor MP7, and the gate is connected to the second storage node Qb;
the source of the fourth transistor MP4 is connected to the power supply, the drain is connected to the drain of the eighth transistor MP8, and the gate is connected to the first storage node Q;
the source of the fifth transistor MN5 is grounded, the drain is connected to the source of the first transistor MP1, and the gate is connected to the second storage node Qb;
the sixth transistor MN6 has a source connected to ground, a drain connected to the source of the second transistor MP2, and a gate connected to the first storage node Q.
Specifically, the third transistor MP3 and the fourth transistor MP4 are PMOS transistors; the fifth transistor MN5 and the sixth transistor MN6 are NMOS, Negative channel Metal-Oxide-Semiconductor transistors.
Optionally, the second isolation unit 5 is configured to isolate the cross-coupling unit 4 from the bias unit 6, and includes a ninth transistor MP9 and a tenth transistor MP10, wherein the ninth transistor MP9 is connected to the first storage node Q, and the tenth transistor MP10 is connected to the second storage node Qb.
Specifically, the ninth transistor MP9 and the tenth transistor MP10 are PMOS transistors.
Specifically, the source of the ninth transistor MP9 is connected to the drain of the first transistor MP1 to the first node n1, and the gate is connected to the second storage node Qb;
the tenth transistor MP10 has a source connected to the drain of the second transistor MP2 to the second node n2 and a gate connected to the first storage node Q.
Optionally, the bias unit 6 includes a third bias transistor MN3 and a fourth bias transistor MN4, and the third bias transistor MN3 and the fourth bias transistor MN4 are both connected to the second isolation unit 5 and are respectively connected to the first storage node Q and the second storage node Qb.
Specifically, the third bias transistor MN3 and the fourth bias transistor MN4 are NMOS transistors.
Specifically, the source of the third bias transistor MN3 is grounded, the drain is connected to the drain of the ninth transistor MP9, and the gate is connected to the first storage node Q;
the fourth bias transistor MN4 has a source connected to ground, a drain connected to the drain of the tenth transistor MP10, and a gate connected to the second storage node Qb.
Optionally, the memory cell further includes a read-write control unit, where the read-write control unit includes a first read-write transistor MN1 and a second read-write transistor MN 2;
the source of the first read-write transistor MN1 is connected to the first bit line BL, the drain is connected to the first storage node Q, and the gate is connected to the word line WL;
the second read/write transistor MN2 has a source connected to the second storage node Qb, a drain connected to the second bit line NBL, and a gate connected to the word line WL.
Specifically, the first read/write transistor MN1 and the second read/write transistor MN2 are NMOS transistors.
The following describes each component of the memory cell provided in the present embodiment in detail with reference to fig. 2.
The main storage unit comprises a PMOS tube MP3, a PMOS tube MP4, an NMOS tube MN5, an NMOS tube MN6, an NMOS tube MN7 and an NMOS tube MN 8;
the source electrode of the PMOS tube MP3 is connected with a power supply, the drain electrode of the PMOS tube MP3 is connected with the drain electrode of the NMOS tube MN7, and the grid electrode of the PMOS tube MP3 is connected with a second storage node Qb;
the source electrode of the PMOS tube MP4 is connected with a power supply, the drain electrode of the PMOS tube MP4 is connected with the drain electrode of the NMOS tube MN8, and the grid electrode of the PMOS tube MP4 is connected with a first storage node Q;
the source electrode of the NMOS transistor MN5 is grounded, and the grid electrode is connected to the second storage node Qb;
the source electrode of the NMOS transistor MN6 is grounded, and the grid electrode is connected to a first storage node Q;
the source electrode of the NMOS tube MN7 is connected with the drain electrode of the NMOS tube MN 5;
the source of the NMOS transistor MN8 is connected to the drain of the NMOS transistor MN 6.
The cross coupling unit 4 comprises a PMOS tube MP1, a PMOS tube MP2, a first node n1 and a second node n 2;
the source electrode of the PMOS transistor MP1 is connected with the power supply, and the grid electrode is connected with the drain electrode of the PMOS transistor MP2 to the second node n 2; the grid electrode is also connected with the grid electrode of the NMOS tube MN7 to a second node n 2;
the source electrode of the PMOS transistor MP2 is connected with a power supply, and the grid electrode of the PMOS transistor MP1 is connected with the drain electrode of the PMOS transistor MP1 to the first node n 1; the gate also connects the gate of the NMOS transistor MN8 to the first node n 1.
The second isolation unit 5 comprises a PMOS tube MP9 and a PMOS tube MP 10;
the source electrode of the PMOS tube MP9 is connected with the drain electrode of the PMOS tube MP1 to the first node n1, and the grid electrode is connected with the second storage node Qb;
the source of the PMOS transistor MP10 is connected to the drain of the PMOS transistor MP2 to the second node n2, and the gate is connected to the first storage node Q.
The bias unit 6 comprises an NMOS transistor MN3 and an NMOS transistor MN 4;
the source electrode of the NMOS transistor MN3 is grounded, the drain electrode of the NMOS transistor MN 9 is connected with the drain electrode of the PMOS transistor MP9, and the grid electrode of the NMOS transistor MN is connected with a first storage node Q;
the source of the NMOS transistor MN4 is grounded, the drain is connected to the drain of the PMOS transistor MP10, and the gate is connected to the second storage node Qb.
The read-write control module comprises an NMOS tube MN1 and an NMOS tube MN 2;
the source electrode of the NMOS tube MN1 is connected with a first bit line BL, the drain electrode is connected with a first storage node Q, and the grid electrode is connected with a word line WL;
the source of the NMOS transistor MN2 is connected to the second bit line NBL, the drain is connected to the second storage node Qb, and the gate is connected to the word line WL.
In this alternative embodiment, when the clock signal WL is 0, the single event upset hardened memory cell is in the data retention state. At this time, assuming that the first storage node Q is 1 and the second storage node Qb is 0, the first storage node Q is in a high state, so that the NMOS transistors MN7, MN6, and MN3 are turned on, the PMOS transistors MP3, MP9, and MP2 are turned on, and the other MOS transistors are turned off. Since the NMOS transistor MN6 is turned on, the state Qb of the second storage node Qb is maintained at 0; similarly, the state Q of the first storage node Q is also maintained at 1 due to the conduction of the PMOS transistor MP3 and the NMOS transistor MN 7. In which case the memory operation of the memory cell is completed.
When the memory cell provided by the alternative embodiment is irradiated by heavy ions, the sensitive nodes are the drain of the NMOS transistor MN5 and the drain of the PMOS transistor MP1 which are in the off state.
When the drain of the NMOS transistor MN5 of the main memory unit is subjected to heavy ion bombardment, the level of the first storage node Q changes from high to low, Q is 0, and the first node n1 of the cross-coupling unit 4 changes to a high-impedance state; at this time, since the PMOS transistor MP3 and the NMOS transistor MN7 are still turned on, the level of the first storage node Q of the main memory cell will be restored to a high level after the heavy ion disturbance is over.
Similarly, when the drain of the PMOS transistor MP1 is subjected to heavy ion bombardment, the level of the first node n1 changes from low to high, and the second node n2 of the cross-coupling unit 4 changes to a high-impedance state; at this time, the PMOS transistor MP9 and the NMOS transistor MN3 are still turned on, so the level of the first node n1 of the cross-coupling unit 4 is restored to the low level after the heavy ion disturbance is finished.
Compared with the ordinary memory cell, the optional embodiment shown in fig. 1 to 2 is adopted, the optional embodiment adds the first isolation unit 3 on the ordinary memory cell to form a main memory cell, introduces a redundant memory node, enables the states of the first node n1 and the second node n2 to be related to the states of the second isolation unit 5 and the bias unit 6 through the connection relationship, the first node n1 and the second node n2 can control the state of the first isolation unit 3, the first memory node Q and the second memory node Qb can control the conduction state of the bias unit 6, the mutual feedback effect between the units in the memory cell stores information, when any one node in the memory cell has the state inversion, the level of the inversion node can recover the normal level through the feedback of other nodes in the memory cell and the pipeline conduction, and realizes the single event resistance reinforcement of the internal node, therefore, the memory cell has a faster flip recovery time, and the memory state of the memory cell is maintained.
FIG. 3 illustrates another alternative embodiment of a single event upset ruggedized memory cell.
In this optional embodiment, the single event upset hardened memory cell includes:
a main storage unit, a cross coupling unit 4, a second isolation unit 5 and a bias unit 6; wherein the content of the first and second substances,
the main storage unit comprises a first isolation unit 3, a first storage node Q and a second storage node Qb; the cross-coupling unit 4 includes a first node n1, a second node n 2;
the states of the first storage node Q, the second storage node Qb, the first node n1, and the second node n2 are related to the states of the second isolation unit 5 and the bias unit 6.
The memory cell further comprises a read/write control unit which realizes the read/write function of the memory cell by controlling the level of the grid electrode of the read/write MOS and the bit line.
Specifically, the following describes each component of the memory cell provided in the present embodiment in detail.
A main storage unit comprising:
the first storage unit 1 comprises an NMOS transistor MN3 and an NMOS transistor MN 4;
the second storage unit 2 comprises a PMOS tube MP5 and a PMOS tube MP 6;
the first isolation unit 3 comprises a PMOS tube MP7 and a PMOS tube MP 8;
the source electrode of the NMOS transistor MN3 is grounded, the drain electrode is connected with the drain electrode of the PMOS transistor MP7, and the grid electrode is connected with a second storage node Qb;
the source electrode of the NMOS transistor MN4 is grounded, the drain electrode of the NMOS transistor MN8 is connected with the drain electrode of the PMOS transistor MP8, and the grid electrode of the NMOS transistor MN is connected with a first storage node Q;
the source electrode of the PMOS tube MP5 is connected with a power supply, and the grid electrode is connected to the second storage node Qb;
the source electrode of the PMOS tube MP6 is connected with a power supply, and the grid electrode is connected to a first storage node Q;
the source electrode of the PMOS tube MP7 is connected with the drain electrode of the PMOS tube MP5 to the first storage node Q;
the source of the PMOS transistor MP8 is connected to the drain of the PMOS transistor MP6 to the second storage node Qb.
The cross coupling unit 4 comprises an NMOS transistor MN1, an NMOS transistor MN2, a first node n1 and a second node n 2;
the source electrode of the NMOS transistor MN1 is grounded, and the grid electrode of the NMOS transistor MN2 is connected with the drain electrode of the NMOS transistor MN2 to a second node n 2; the grid is also connected with the grid of the PMOS tube MP7 to a second node n 2;
the source electrode of the NMOS transistor MN2 is grounded, and the grid electrode of the NMOS transistor MN1 is connected with the drain electrode of the NMOS transistor MN1 to a first node n 1; the gate also connects the gate of the PMOS transistor MP8 to the first node n 1.
The second isolation unit 5 comprises an NMOS transistor MN5 and an NMOS transistor MN 6;
the source electrode of the NMOS transistor MN5 is connected with the drain electrode of the NMOS transistor MN1 to the first node n1, and the grid electrode of the NMOS transistor MN is connected with the second storage node Qb;
the source electrode of the NMOS transistor MN6 is connected with the drain electrode of the NMOS transistor MN2 to the second node n2, and the grid electrode of the NMOS transistor MN is connected with the first storage node Q;
the bias unit 6 comprises a PMOS tube MP3 and a PMOS tube MP 4;
the source electrode of the PMOS tube MP3 is connected with a power supply, the drain electrode of the PMOS tube MP3 is connected with the drain electrode of the NMOS tube MN5, and the grid electrode of the PMOS tube MP3 is connected with a first storage node Q;
the source of the PMOS transistor MP4 is connected to the power supply, the drain is connected to the drain of the NMOS transistor MN6, and the gate is connected to the second storage node Qb.
The read-write control unit comprises a PMOS tube MP1 and a PMOS tube MP 2;
the source electrode of the PMOS pipe MP1 is connected with a first storage node Q, the drain electrode is connected with a first bit line BL, and the grid electrode is connected with a word line WL;
the source of the PMOS transistor MP2 is connected to the second storage node Qb, the drain is connected to the second bit line NBL, and the gate is connected to the word line WL.
In this alternative embodiment, when the clock signal WL is 1, the single event upset hardened memory cell is in the data retention state. At this time, assuming that the first storage node Q is 1 and the second storage node Qb is 0, the first storage node Q is in a high state, so that the NMOS transistors MN4, MN6, and MN1 are turned on, the PMOS transistors MP5, MP4, and MP8 are turned on, and the other MOS transistors are turned off. Since the NMOS transistor MN4 and the PMOS transistor MP8 are turned on, the state Qb of the second storage node Qb is maintained at 0; similarly, the state Q of the first storage node Q is also maintained at 1 due to the conduction of the PMOS transistor MP 5. In which case the memory operation of the memory cell is completed.
When the memory cell provided by the alternative embodiment is irradiated by heavy ions, the sensitive nodes are the drain of the PMOS transistor MP6 and the drain of the NMOS transistor MN2 in the off state.
When the drain of the PMOS transistor MP6 of the main memory unit is subjected to heavy ion bombardment, the level of the second storage node Qb changes from low to high, Qb is 1, and the second node n2 of the cross-coupling unit 4 changes to a high-impedance state; at this time, since the PMOS transistor MP8 and the NMOS transistor MN4 still maintain the conducting state, the level of the second storage node Qb of the main memory cell will be restored to the high level after the heavy ion disturbance is over.
Similarly, when the drain of the NMOS transistor MN2 is subjected to heavy ion bombardment, the level of the second node n2 changes from high to low, and the first node n1 of the cross-coupling unit 4 changes to a high-impedance state, at this time, since the PMOS transistor MP4 and the NMOS transistor MN6 are still kept in a conducting state, the level of the second node n2 of the cross-coupling unit 4 returns to a high level after the heavy ion bombardment is completed.
The alternative embodiment shown in fig. 3 is adopted and comprises a main storage unit, a cross coupling unit 4, a second isolation unit 5, a biasing unit 6 and a read/write control unit. In contrast to the alternative embodiment shown in fig. 1, the first isolation unit 3, the second isolation unit 5, the bias unit 6 and the cross-coupling unit 4 in this alternative embodiment are replaced by devices of the opposite type to the embodiment shown in fig. 1, and some of the wiring lines are adjusted. Compared with a common storage unit, the optional embodiment introduces redundant storage nodes, stores information through mutual feedback action among different units, and when any node in the storage unit is in a state reversal state, the level of the reversal node can be restored to the normal level through the feedback of other nodes, so that the correct state of the storage unit is maintained. The scheme is improved on the technology of the common storage unit, is basically consistent with the read/write speed of the common storage unit, and can be used for design reinforcement of a high-speed and high-reliability memory. In addition, the invention is realized by adopting a commercial process, has low manufacturing cost, simultaneously has small quiescent current of the memory unit and faster turnover recovery time, and can be applied to the irradiation resistance reinforcement of deep submicron integrated circuits.
An alternative embodiment of a memory array.
In this alternative embodiment, the memory array includes a plurality of single event upset ruggedized memory cells of the alternative embodiment shown in fig. 2; the memory cells are arranged in rows and columns; the memory cell array further comprises a plurality of bit lines and word lines, wherein the memory cells on the same row share one word line, and the memory cells on the same column share one bit line.
Specifically, the single event upset reinforced memory cells forming the memory array comprise main memory cells, and the main memory cells comprise:
the first storage unit 1 comprises a PMOS tube MP3 and a PMOS tube MP 4;
the second storage unit 2 comprises an NMOS transistor MN5 and an NMOS transistor MN 6;
the first isolation unit 3 comprises an NMOS transistor MN7 and an NMOS transistor MN 8;
the source electrode of the PMOS tube MP3 is connected with a power supply, the drain electrode of the PMOS tube MP3 is connected with the drain electrode of the NMOS tube MN7, and the grid electrode of the PMOS tube MP3 is connected with a second storage node Qb;
the source electrode of the PMOS tube MP4 is connected with a power supply, the drain electrode of the PMOS tube MP4 is connected with the drain electrode of the NMOS tube MN8, and the grid electrode of the PMOS tube MP4 is connected with a first storage node Q;
the source electrode of the NMOS transistor MN5 is grounded, and the grid electrode is connected to the second storage node Qb;
the source electrode of the NMOS transistor MN6 is grounded, and the grid electrode is connected to a first storage node Q;
the source electrode of the NMOS tube MN7 is connected with the drain electrode of the NMOS tube MN 5;
the source of the NMOS transistor MN8 is connected to the drain of the NMOS transistor MN 6.
The cross coupling unit 4 comprises a PMOS tube MP1, a PMOS tube MP2, a first node n1 and a second node n 2;
the source electrode of the PMOS transistor MP1 is connected with the power supply, and the grid electrode is connected with the drain electrode of the PMOS transistor MP2 to the second node n 2; the grid electrode is also connected with the grid electrode of the NMOS tube MN7 to a second node n 2;
the source electrode of the PMOS transistor MP2 is connected with a power supply, and the grid electrode of the PMOS transistor MP1 is connected with the drain electrode of the PMOS transistor MP1 to the first node n 1; the gate also connects the gate of the NMOS transistor MN8 to the first node n 1.
The second isolation unit 5 comprises a PMOS tube MP9 and a PMOS tube MP 10;
the source electrode of the PMOS tube MP9 is connected with the drain electrode of the PMOS tube MP1 to the first node n1, and the grid electrode is connected with the second storage node Qb;
the source of the PMOS transistor MP10 is connected to the drain of the PMOS transistor MP2 to the second node n2, and the gate is connected to the first storage node Q.
The bias unit 6 comprises an NMOS transistor MN3 and an NMOS transistor MN 4;
the source electrode of the NMOS transistor MN3 is grounded, the drain electrode of the NMOS transistor MN 9 is connected with the drain electrode of the PMOS transistor MP9, and the grid electrode of the NMOS transistor MN is connected with a first storage node Q;
the source of the NMOS transistor MN4 is grounded, the drain is connected to the drain of the PMOS transistor MP10, and the gate is connected to the second storage node Qb.
The read-write control module comprises an NMOS tube MN1 and an NMOS tube MN 2;
the source electrode of the NMOS tube MN1 is connected with a first bit line BL, the drain electrode is connected with a first storage node Q, and the grid electrode is connected with a word line WL;
the source of the NMOS transistor MN2 is connected to the second bit line NBL, the drain is connected to the second storage node Qb, and the gate is connected to the word line WL.
The memory array provided by the optional embodiment is formed by arranging a plurality of memory cells in rows and columns, the memory cells are realized on the basis of improvement of common memory cells, the read/write speed of the memory array is basically consistent with that of the common memory cells, and the memory array can be used for design reinforcement of a high-speed and high-reliability memory; meanwhile, the manufacturing cost is reduced by adopting a commercial process. The storage unit introduces redundant storage nodes, the storage information can be reinforced through the mutual feedback effect among different units, when any one node in a single storage unit is in state reversal, the reversal node can recover the normal level of the node through the feedback of other nodes in the storage unit and the conduction of a pipeline, the anti-single-event reinforcement of an internal node is realized, the single storage unit has quick reversal recovery time, the anti-single-event reinforcement of the storage unit in the array is further realized, and the integral single-event reversal recovery time of the storage array is quick.
Another alternative embodiment of a memory array.
In this alternative embodiment, the memory array includes a plurality of single event upset ruggedized memory cells of the alternative embodiment shown in fig. 3; the memory cells are arranged in rows and columns; the memory cell array further comprises a plurality of bit lines and word lines, wherein the memory cells on the same row share one word line, and the memory cells on the same column share one bit line.
Specifically, the single event upset reinforced memory cells forming the memory array comprise: a main storage unit comprising:
the first storage unit 1 comprises an NMOS transistor MN3 and an NMOS transistor MN 4;
the second storage unit 2 comprises a PMOS tube MP5 and a PMOS tube MP 6;
the first isolation unit 3 comprises a PMOS tube MP7 and a PMOS tube MP 8;
the source electrode of the NMOS transistor MN3 is grounded, the drain electrode is connected with the drain electrode of the PMOS transistor MP7, and the grid electrode is connected with a second storage node Qb;
the source electrode of the NMOS transistor MN4 is grounded, the drain electrode of the NMOS transistor MN8 is connected with the drain electrode of the PMOS transistor MP8, and the grid electrode of the NMOS transistor MN is connected with a first storage node Q;
the source electrode of the PMOS tube MP5 is connected with a power supply, and the grid electrode is connected to the second storage node Qb;
the source electrode of the PMOS tube MP6 is connected with a power supply, and the grid electrode is connected to a first storage node Q;
the source electrode of the PMOS tube MP7 is connected with the drain electrode of the PMOS tube MP5 to the first storage node Q;
the source of the PMOS transistor MP8 is connected to the drain of the PMOS transistor MP6 to the second storage node Qb.
The cross coupling unit 4 comprises an NMOS transistor MN1, an NMOS transistor MN2, a first node n1 and a second node n 2;
the source electrode of the NMOS transistor MN1 is grounded, and the grid electrode of the NMOS transistor MN2 is connected with the drain electrode of the NMOS transistor MN2 to a second node n 2; the grid is also connected with the grid of the PMOS tube MP7 to a second node n 2;
the source electrode of the NMOS transistor MN2 is grounded, and the grid electrode of the NMOS transistor MN1 is connected with the drain electrode of the NMOS transistor MN1 to a first node n 1; the gate also connects the gate of the PMOS transistor MP8 to the first node n 1.
The second isolation unit 5 comprises an NMOS transistor MN5 and an NMOS transistor MN 6;
the source electrode of the NMOS transistor MN5 is connected with the drain electrode of the NMOS transistor MN1 to the first node n1, and the grid electrode of the NMOS transistor MN is connected with the second storage node Qb;
the source electrode of the NMOS transistor MN6 is connected with the drain electrode of the NMOS transistor MN2 to the second node n2, and the grid electrode of the NMOS transistor MN is connected with the first storage node Q;
the bias unit 6 comprises a PMOS tube MP3 and a PMOS tube MP 4;
the source electrode of the PMOS tube MP3 is connected with a power supply, the drain electrode of the PMOS tube MP3 is connected with the drain electrode of the NMOS tube MN5, and the grid electrode of the PMOS tube MP3 is connected with a first storage node Q;
the source of the PMOS transistor MP4 is connected to the power supply, the drain is connected to the drain of the NMOS transistor MN6, and the gate is connected to the second storage node Qb.
The read-write control unit comprises a PMOS tube MP1 and a PMOS tube MP 2;
the source electrode of the PMOS pipe MP1 is connected with a first storage node Q, the drain electrode is connected with a first bit line BL, and the grid electrode is connected with a word line WL;
the source of the PMOS transistor MP2 is connected to the second storage node Qb, the drain is connected to the second bit line NBL, and the gate is connected to the word line WL.
The single-event upset reinforced storage unit adopted in the optional embodiment reinforces the stored information through the mutual feedback effect among different units, when any node in a single storage unit is in state upset, the upset node can recover the normal level of the single-event upset reinforced storage unit through the feedback of other nodes in the single storage unit and the conduction of a pipeline, and the single-event upset resistance reinforcement of internal nodes is realized, so that the single storage unit has quick upset recovery time, the single-event upset resistance reinforcement of the storage units in the array is further realized, and the whole single-event upset recovery time of the storage array is quick.
In summary, according to the single-event upset reinforced memory cell provided by the invention, information is stored through mutual feedback interaction between different cells, and when any node in the memory cell has a state upset, the level of the upset node can be restored to the normal level through feedback of other nodes, so that the correct state of the memory cell is maintained. The invention adopts commercial process, has low manufacturing cost and small quiescent current of the memory unit, ensures that the memory unit has faster turnover recovery time due to the mutual feedback effect among the units, has high read-write speed and can be used for the design reinforcement of a high-speed and high-reliability memory.
In alternative embodiments disclosed herein, it should be understood that the disclosed articles of manufacture (including but not limited to devices, apparatuses, etc.) may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form. The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment. In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
It is to be understood that the present invention is not limited to the procedures and structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the invention is limited only by the appended claims.
Claims (7)
1. The utility model provides a reinforced memory cell of single event upset, includes first memory cell and second memory cell, its characterized in that still includes:
a first isolation unit for isolating the first memory unit from the second memory unit; the first isolation unit comprises a first storage node and a second storage node; the input end of the first isolation unit is connected with the first storage unit, and the output end of the first isolation unit is connected with the second storage unit;
the cross coupling unit is used for separating or combining signals and providing feedback for the first isolation unit; the input end of the cross coupling unit is connected with a power supply, and the output end of the cross coupling unit is connected with the input end of the second isolation unit; the first isolation unit is connected to a first node and a second node of the cross coupling unit;
a bias unit for providing bias voltages for the first isolation unit and the cross-coupling unit; and
a second isolation unit for isolating the cross-coupling unit and the bias unit;
the output end of the second isolation unit is connected with the input end of the bias unit; the second isolation unit is connected to the first storage node and the second storage node; the output end of the bias unit is grounded; the bias unit and the first isolation unit are connected to the first storage node and the second storage node;
the first isolation unit comprises a seventh transistor and an eighth transistor, and the first storage node and the second storage node are arranged between the seventh transistor and the eighth transistor; the first storage unit comprises a third transistor and a fourth transistor; the second storage unit comprises a fifth transistor and a sixth transistor;
an output end of the seventh transistor is connected with an input end of the fifth transistor to the first storage node, and an input end of the seventh transistor is connected with an output end of the third transistor;
an output end of the eighth transistor is connected with an input end of the sixth transistor to the second storage node, and an input end of the eighth transistor is connected with an output end of the fourth transistor;
the input end of the third transistor is connected with a power supply, and the grid electrode of the third transistor and the grid electrode of the fifth transistor are connected to the second storage node;
the input end of the fourth transistor is connected with a power supply, and the grid electrode of the fourth transistor and the grid electrode of the sixth transistor are connected to the first storage node; the output end of the fifth transistor is grounded; the output end of the sixth transistor is grounded.
2. The single event upset ruggedized memory cell of claim 1, wherein the cross-coupled cell comprises a first transistor, a second transistor, a first node, a second node;
the input end of the first transistor is connected with a power supply, and the grid electrode of the first transistor is connected with the grid electrode of the seventh transistor and the output end of the second transistor to the second node;
the input end of the second transistor is connected with a power supply, and the grid electrode of the second transistor is connected with the grid electrode of the eighth transistor and the output end of the first transistor to the first node.
3. The single event upset ruggedized memory cell of claim 2, wherein the second isolation cell comprises a ninth transistor, a tenth transistor;
the input end of the ninth transistor and the output end of the first transistor are connected to the first node, and the grid electrode of the ninth transistor is connected to the second storage node;
an input end of the tenth transistor and an output end of the second transistor are connected to the second node, and a gate is connected to the first storage node.
4. The single event upset ruggedized memory cell of claim 3, wherein the bias cell comprises a third bias transistor, a fourth bias transistor;
the input end of the third bias transistor is connected with the output end of the ninth transistor, the output end of the third bias transistor is grounded, and the grid electrode of the third bias transistor is connected with the first storage node;
the input end of the fourth bias transistor is connected with the output end of the tenth transistor, the output end of the fourth bias transistor is grounded, and the grid electrode of the fourth bias transistor is connected with the second storage node.
5. The single event upset ruggedized memory cell of claim 1, further comprising a read-write control unit to control a level of the bit line to implement read-write functionality of the memory cell.
6. The single event upset ruggedized memory cell of claim 5, wherein the read-write control unit comprises a first read-write transistor, a second read-write transistor;
the input end of the first read-write transistor is connected with a first bit line, the output end of the first read-write transistor is connected with a first storage node, and the grid of the first read-write transistor is connected with a word line;
the input end of the second reading and writing transistor is connected with the second storage node, the output end of the second reading and writing transistor is connected with the second bit line, and the grid of the second reading and writing transistor is connected with the word line.
7. A memory array, characterized by: the method comprises the following steps:
the single event upset ruggedized memory cell of any of claims 1 to 6, the memory cells arranged in rows and columns;
a plurality of bit lines and word lines;
the memory cells in the same row share a word line, and the memory cells in the same column share a bit line.
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| US8472271B2 (en) * | 2011-02-18 | 2013-06-25 | International Business Machines Corporation | Systems and methods for memory device precharging |
| CN102723109B (en) * | 2012-06-29 | 2015-03-04 | 西安交通大学 | Novel static random access memory (SRAM) storage unit preventing single particle from turning |
| CN103778954B (en) * | 2014-02-24 | 2016-08-31 | 哈尔滨工业大学 | The memorizer of anti-multiple node upset |
| CN104392745B (en) * | 2014-11-27 | 2017-04-26 | 西安交通大学 | SRAM unit with high writing speed, low static power consumption and single-particle overturning resistance |
| CN106328189B (en) * | 2015-06-25 | 2019-07-05 | 中国科学院电子学研究所 | Primary particle inversion resistant reinforcing SRAM circuit |
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