CN109522130A - Reverse dispatching method based on shared buffer memory - Google Patents
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Abstract
The invention discloses a kind of reverse dispatching method based on shared buffer memory towards wideband satellite communication system Onboard switching, this method mainly includes four steps: being primarily based on shared buffer memory and provides a shared buffer memory on the basis of joint input crosspoint is lined up (CICQ) for every row crosspoint, forms the internal crossbar fabric (BCSB) with shared buffer memory；Then it sends and caches according to the request of input stage module (IM) cell；And then IM cell sends the request matching internal in intergrade module (CM)；Finally, returning to Authorization result by CM, IM instructs cell Lothrus apterus to forward according to Authorization result.The star loading exchanging method of satellite communication is used for compared to other, shared buffer memory is applied to multistage nonblocking switching (Clos) network by this method, and combine reverse dispatching algorithm, while guaranteeing the performances such as exchange throughput, utilization rate, dispatching efficiency and the scalability of resource are improved.
Description
Technical field
The present invention relates to satellite communication fields, are to be related to a kind of reverse dispatching party based on shared buffer memory more specifically
Method is a kind of for resource critical constraints, the star loading exchanging method of the demanding spaceborne switched environment of system effectiveness.
Background technique
First existed based on the reverse dispatching algorithm of input and output grade buffer queue-multistage nonblocking switching (MSM-Clos) network
Intergrade module requests cell to carry out matching internal, then instructs the cell of input stage module to send with this, and tune greatly improved
Efficiency is spent, the spaceborne exchange of large capacity is suitable for.But its input stage module is only with pseudo receptor model (VOQ) and polling dispatching, if
It introduces joint input crosspoint queuing (CICQ) and is then conducive to its input, output end distributed scheduling, scalability is strong.But intersect
The number of queues that point is lined up (CQ) is proportional to product n × m of input, output port number, and resource utilization is low.
In conventional belt caching corsspoint switch matrix (Crossbar) switching fabric, spatial cache is big on each crosspoint
Small and utilization rate is to influence two important indicators of performance.But for high performance pursuit, especially using extensive
When crossbar fabric, to avoid queue overflow packet loss, CQ spatial cache is forced to increase.As for caching utilization rate, only flowing
When amount is uniformly distributed, each CQ space utilization rate is just almost the same.And in flow non-uniform Distribution, it is largely handed in Crossbar
The Buffer Utilization of crunode is lower, and hardware spending and the wasting of resources and hardware design complexity is caused to increase sharply.
Summary of the invention
Present invention aim to address traditional spaceborne exchange algorithms cannot take into account asking for dispatching efficiency and resource utilization
Topic, provides a kind of reverse dispatching method based on shared buffer memory.
To achieve the above object, technical solution provided by the invention is as follows:
A kind of reverse dispatching method based on shared buffer memory, under the reverse dispatching method based on shared buffer memory includes
Column step:
S1, to corsspoint switch matrix structure, be that every row crosspoint mentions on the basis of being lined up based on joint input crosspoint
For a shared buffer memory, the internal corsspoint switch matrix structure with shared buffer memory is formed, i.e. BCSB, the structure is first in input terminal
Using pseudo receptor model queue, then respectively every row crosspoint provides shared buffer memory, is finally arbitrated and is dispatched by input and output
Device come complete input terminal and export client information scheduling；
S2, cell make requests transmission and caching in IM, wherein IM is input stage module；
The request that S3, cell are sent in IM is matched in the inside of CM, wherein CM is intergrade module, the matching
Interchanger is cached referring to input rank, internal CI is completed using the scheduling cached based on input rankj,iWith COj,kMatching,
Wherein CIj,iIndicate i-th of input terminal of j-th of CM, COj,kIndicate k-th of output end of j-th of CM；
S4, CM return to Authorization result to IM according to the matching result in step S3；
S5, IM instruct cell Lothrus apterus to forward according to the Authorization result in step S4.
Further, the step S2 is specifically included:
S21, when cell reach IIi,gAfterwards, IIi,gIt is according to the serial number k of the affiliated OM of cell, cell deposit is corresponding virtual defeated
It is lined up out, wherein OM is output module, IIi,gIndicate g-th of input terminal of i-th of IM；
S22、IMiInput terminal { IIi,g| 1≤g≤n } IO selected by polli,j, and the purpose OM that cell will be contained only
The request of serial number is with selected IOi.jIt is sent to connected CMj, wherein IMiIndicate i-th of IM, IOi,jIndicate IMiJ-th
Output end, CMjIndicate j-th of CM；
S23、CIj,iAfter receiving cell request, according to the purpose OM serial number k of cell by corresponding counter cnti,kAdd one,
Wherein CIj,iIndicate CMjI-th of input terminal, CNTi,kK-th of counter for indicating i-th of input terminal of a CM, falls into a trap
Number device records the request number for needing to go to the cell of k-th of OM.
Further, the step S4 is specifically included:
If S41, CIj,iWith COj,kSuccessful match, then CIj,iCorresponding counter cnti,kValue subtract one, while to IMi
Authorization message is returned to, wherein authorization message only includes cell purpose OM serial number k, and length isBit, wherein COj,kIt indicates
CMjK-th of output end, r indicate input module number；
S42、IOi,jAfter receiving response, the serial number k of the purpose OM of cell is forwarded to corresponding pseudo receptor model, virtually
Output work queue will be in next time slot to IOi,jIt is formal to send data packet.
Compared with prior art, the beneficial effects of the present invention are:
1, the reverse dispatching method disclosed by the invention based on shared buffer memory is compared to most of traditional spaceborne exchange side
For method, the advantage for having both shared buffer memory, inversely dispatching substantially reduces hardware complexity, improves scalability, it is tight to be suitable for resource
It is limited again, the spaceborne exchange high to efficiency requirements.
2, the reverse dispatching method disclosed by the invention based on shared buffer memory, compared to most of tradition without under caching and
1 (CRRD of row poll distribution algorithms (CRRD) iterationI=1), reverse dispatching algorithm (REV), be based on shared buffer memory (SB) CRRD
And its algorithm containing speed-up ratio (SB-CRRD and SB-CRRDS), based on shared buffer memory it is reverse scheduling and its algorithm containing speed-up ratio
(SB-REV and SB-REVS), the CRRD dispatching algorithm based on CICQ structure, method of the invention only needs the acceleration of S≤1.05
Than other above-mentioned algorithms can be better than on time delay, throughput.
Detailed description of the invention
Fig. 1 is the process step figure of the reverse dispatching algorithm proposed by the present invention based on shared buffer memory；
Fig. 2 is BCSB switching fabric schematic diagram；
Fig. 3 (a) is the IM throughput comparison diagram of algorithms of different under bernoulli business；
Fig. 3 (b) is every row average queue length comparison diagram of algorithms of different under bernoulli business；
Fig. 3 (c) is the cell delay comparison diagram of algorithms of different under bernoulli business；
Fig. 3 (d) is every row maximum queue length comparison diagram of algorithms of different under bernoulli business；
Fig. 4 is the SB-CRRD as bernoulli traffic intensity λ=1SWith SB-REVSSpeed-up ratio convergence comparison diagram.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer and more explicit, right as follows in conjunction with drawings and embodiments
The present invention is further described.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and do not have to
It is of the invention in limiting.
Embodiment one
The present embodiment devises a kind of reverse dispatching method based on shared buffer memory.The processing of method is exchanged in the present embodiment
Process the following steps are included:
S1, the resource utilization in order to improve switching fabric intersect corsspoint switch matrix structure based on joint input
A shared buffer memory is provided for every row crosspoint on the basis of point queuing, forms the internal corsspoint switch matrix with shared buffer memory
Structure, i.e. BCSB, the structure first use pseudo receptor model queue in input terminal, and then respectively every row crosspoint provides shared
Caching finally arbitrates scheduler by input and output to complete input terminal and export the scheduling of client information, and the structure is compared to biography
The crosspoint of system is lined up, and is highly improved in terms of resource utilization；
S2, cell make requests transmission and caching in IM module, wherein IM is input stage module.Wherein, step S2
Specific implementation process is as follows:
S21, when cell reach IIi,gAfterwards, by the serial number k of the affiliated OM of cell, by the corresponding virtual output row of cell deposit
Team, wherein OM is output level module, IIi,gIndicate g-th of input terminal of i-th of IM；
S22、IMiInput terminal { IIi,g| 1≤g≤n } IO selected by polli,j, and the purpose OM that cell will be contained only
The request of serial number is with selected IOi.jIt is sent to connected CMj, wherein IMiIndicate i-th of IM, IOi,jIndicate IMiJ-th
Output end, CM indicate intergrade module, CMjIndicate j-th of CM；
S23、CIj,iAfter receiving cell request, according to the purpose OM serial number k of cell by corresponding counter cnti,kValue add
One, wherein CIj,iIndicate CMjI-th of input terminal, CNTi,kIndicate k-th of counter of i-th of input terminal of a CM,
Middle counter records the cell request number for needing to go to k-th of OM.
The request that S3, IM cell are sent is matched in the inside of CM, which caches interchanger referring to input rank, is adopted
Internal CI is completed with the scheduling cached based on input rankj,iWith COj,kMatching, wherein COj,kIndicate CMjK-th output
End；
S4, CM return to Authorization result to IM according to the matching result of S3；
Wherein, the specific implementation process of step S4 is as follows:
If S41, CIj,iWith COj,kSuccessful match, then counter cnti,kValue subtract one, while to IMiReturn to authorization
Information, wherein authorization message only includes the purpose OM serial number k of cell, and length isThe number of bit, r expression input module；
S42、IOi,jAfter receiving response, the purpose OM serial number k of cell is forwarded to corresponding pseudo receptor model, it is virtual defeated
Being lined up out will be in next time slot to IOi,jIt is formal to send data packet.
S5, IM instruct cell Lothrus apterus to forward according to the Authorization result of S4.
Step S2 to S5 is to solve the problems, such as dispatching efficiency, uses reverse dispatching method, this method is compared to traditional
Parallel polling distribution algorithms are reduced to 3 times by original 5 times on number shaking hands, and do not need the process of iteration, big in this way
Amplitude improves the efficiency of scheduling.The present invention proposes one kind from solving resource utilization and two aspect of dispatching efficiency
Reverse dispatching method based on shared buffer memory, in conjunction with above-mentioned steps, the advantage that this method has had both shared buffer memory, inversely dispatched,
While guaranteeing the performances such as exchange throughput, utilization rate, dispatching efficiency and the scalability of resource are improved.
Embodiment two
The present embodiment is combined attached Fig. 1 to Fig. 4 and is proposed with a specific star loading exchanging method case study on implementation to the present invention
The reverse dispatching method based on shared buffer memory be once described in detail.
Consider that system model is as follows: respectively containing the MSM- of the C (8,8,8) of 8 modules using input, intermediate, output three-level
Clos network model, crossbar fabric therein are 16 × 16.Meanwhile in order to preferably test shared buffer memory in practice
The value that size should be arranged, the shared buffer memory queue that BCSB internal switching structure is arranged in simulations is infinity, to measure
The upper limit of actually required queue spatial cache.In addition, because the every a line of BCSB all uses shared buffer memory, multiple output schedulings at this time
(OS) cell in same shared buffer memory may be dispatched simultaneously, will lead to congestion, and shared buffer memory can be improved to solve the conflict
Read and write rate (inside accelerate also have certain overhead, smaller speed-up ratio is more conducive to extend).
The cell of input stage module uses length for 256bits (fixed length, containing data content, destination node, cell ID and hair
Send the information such as time) the bernoulli business of intensity λ=1, the business duration is 10000 time slots.When cell reaches IMiInput terminal
IIi,gAfterwards, by the affiliated OM of cellkCell is stored in corresponding pseudo receptor model by module.IMiInput terminal { IIi,g| 1≤g≤n } it is logical
Overpolling selects output end IOi,j, and by the request of cell with selected IOi.j(transmission that output end needs to collect input terminal is asked
It asks and request list is periodically sent to CMjFor authorization, and empty when time request list) it is sent to connected CMj。CMj
Each input terminal CIj,iAfter receiving cell request, according to its purpose OM serial number k, by corresponding counter cnti,kAdd one.
Input stage module cell sends request and is matched in the inside of intergrade module, which is similar to input rank
Interchanger is cached, internal CI is completed using the scheduling cached based on input rankj,iWith COj,kMatching；
If inputting CI inside CMj,iExport COj,kSuccessful match then corresponds to counter cnti,kValue subtract one, while to
IMiAuthorization message is returned to, wherein authorization message only includes the purpose OM serial number k of cell, and length isBit, r indicate input
The number of module.IMiOutput end IOi,jAfter receiving response, information OM serial number k therein is forwarded to corresponding virtual output and is arranged
Team, pseudo receptor model will be in next time slots to IOi,jIt is formal to send data packet.
Input stage module finally instructs cell Lothrus apterus to forward according to Authorization result.
Fig. 3 analysis the result shows that, in terms of throughput, remove CRRDI=1, outside SB-CRRD, SB-REV, other algorithms tend to
100%.SB-CRRD throughput is even lower than CRRDI=1, this is because SB-CRRD, SB-REV take with entire shared buffer memory
For the mechanism of polling object, non-oldest cell in queue is caused to have no right to participate in matching, but simultaneously improves polling efficiency to m
(line number of Crossbar) times.Different from CICQ, the cell in shared buffer memory can go to any output port, therefore shared slow
Deposit non-empty and there are delivery outlet it is idle in the case where, can improve throughput by speed-up ratio, and CICQ be then limited to it is fixed
Output port rate and throughput can not be improved by speed-up ratio.As shown in Fig. 3 (a), SB-CRRD can be reached by internal acceleration
To 100% throughput, and speed-up ratio needed for SB-CRRD at this time as shown in Figure 4 converges on S=1.208.
Similarly SB-REV algorithm IM throughput when not accelerating is 98.4%, and SB-REV is only at this time as shown in Figure 4
Need the speed-up ratio of S=1.05 that can be attained by 8 kinds of algorithms on throughput, queue overhead optimal, on Cell delay variation, most
3.3 time slots of more backward REV algorithms.As shown in Fig. 3 (a), (c), CICQ throughput is that 100%, delay performance is optimal, still
Find out from Fig. 3 (b), (d), it is SB-CRRD that queue resource consumption is largerS2.9 times, SB-REVS2.83 times.
To sum up, in the case where traffic intensity is 1 bernoulli business, queue is improved to shared buffer memory not using when same algorithm
It must can optimize performance, but under same queue structure dispatching algorithm is improved to reverse scheduling that various aspects of performance can be made to obtain is excellent
Change.Wherein SB-REVSOverall performance is optimal.
The above embodiment is a preferred embodiment of the present invention, but embodiments of the present invention are not by above-described embodiment
Limitation, other any changes, modifications, substitutions, combinations, simplifications made without departing from the spirit and principles of the present invention,
It should be equivalent substitute mode, be included within the scope of the present invention.
Claims (3)
1. a kind of reverse dispatching method based on shared buffer memory, which is characterized in that the reverse scheduling based on shared buffer memory
Method includes the following steps:
S1, to corsspoint switch matrix structure, provide one on the basis of being lined up based on joint input crosspoint for every row crosspoint
A shared buffer memory, forms the internal corsspoint switch matrix structure with shared buffer memory, i.e. BCSB, which first uses in input terminal
Pseudo receptor model queue, then respectively every row crosspoint provides shared buffer memory, finally by input and output arbitrate scheduler
It completes input terminal and exports the scheduling of client information；
S2, cell make requests transmission and caching in IM, wherein IM is input stage module；
The request that S3, cell are sent in IM is matched in the inside of CM, wherein CM is intergrade module, the matching reference
Input rank caches interchanger, and internal CI is completed using the scheduling cached based on input rankj,iWith COj,kMatching, wherein
CIj,iIndicate i-th of input terminal of j-th of CM, COj,kIndicate k-th of output end of j-th of CM；
S4, CM return to Authorization result to IM according to the matching result in step S3；
S5, IM instruct cell Lothrus apterus to forward according to the Authorization result in step S4.
2. the reverse dispatching method according to claim 1 based on shared buffer memory, which is characterized in that the step S2 tool
Body includes:
S21, when cell reach IIi,gAfterwards, IIi,gAccording to the serial number k of the affiliated OM of cell, by the corresponding virtual output row of cell deposit
Team, wherein OM is output module, IIi,gIndicate g-th of input terminal of i-th of IM；
S22、IMiInput terminal { IIi,g| 1≤g≤n } IO selected by polli,j, and the purpose OM serial number of cell will be contained only
Request is with selected IOi.jIt is sent to connected CMj, wherein IMiIndicate i-th of IM, IOi,jIndicate IMiJ-th of output end,
CMjIndicate j-th of CM；
S23、CIj,iAfter receiving cell request, according to the purpose OM serial number k of cell by corresponding counter cnti,kAdd one, wherein
CIj,iIndicate CMjI-th of input terminal, CNTi,kIndicate k-th of counter of i-th of input terminal of a CM, wherein counter
Record the request number for needing to go to the cell of k-th of OM.
3. the reverse dispatching method according to claim 2 based on shared buffer memory, which is characterized in that the step S4 tool
Body includes:
If S41, CIj,iWith COj,kSuccessful match, then CIj,iCorresponding counter cnti,kValue subtract one, while to IMiReturn is awarded
Information is weighed, wherein authorization message only includes cell purpose OM serial number k, and length isWherein COj,kIndicate CMjKth
A output end, r indicate the number of input module；
S42、IOi,jAfter receiving response, the serial number k of the purpose OM of cell is forwarded to corresponding pseudo receptor model, it is virtual to export
Being lined up will be in next time slot to IOi,jIt is formal to send data packet.
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