CN114257557A - Data packet switching system and method - Google Patents
Data packet switching system and method Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/20—Support for services
- H04L49/201—Multicast operation; Broadcast operation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/24—Traffic characterised by specific attributes, e.g. priority or QoS
- H04L47/2425—Traffic characterised by specific attributes, e.g. priority or QoS for supporting services specification, e.g. SLA
- H04L47/2433—Allocation of priorities to traffic types
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3072—Packet splitting
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
Abstract
The invention provides a data packet switching method and a system, which comprises the steps of constructing a switching system consisting of a plurality of sub-switching modules, wherein the sub-switching modules of the switching system are arranged according to a row-column rule, each row of sub-switching modules is provided with an input distribution module, and the sub-switching modules in each row in the switching system are connected in pairs; data packets to be exchanged enter the exchange system through the input distribution module, the data packets are distributed to the sub-exchange modules in the row of the input distribution module and serve as the initial exchange module according to the destination addresses carried by the data packets, and the initial exchange module stores the data packets in a single queue to wait for port arbitration authorization; after the data packet is authorized, the data packet is distributed to a sub-switch module of a certain row in the switch system according to the destination address and serves as a destination sub-switch module, the destination sub-switch module stores the data packet to another independent queue, and the data packet is output after the output port is arbitrated.
Description
Technical Field
The present invention belongs to the field of computer network, and is especially data packet switching system and method.
Background
At present, the data switching network has the characteristics of large data exchange quantity and complex bearing service types, wherein the multicast function is widely used in various services such as distributed computing, machine learning and the like. Existing multicast schemes optimize the multicast functionality primarily from the network transport protocol and mechanism layer.
A method for processing multicast messages and a processing device thereof in terms of transmission mechanism are disclosed in the patent "method for processing multicast messages and switching access device" (CN 102594650 a). Firstly, searching a corresponding multicast destination address in a multicast routing table according to a multicast address of a multicast message; broadcasting the destination address in the unicast routing list according to the multicast destination address; searching a corresponding available link according to the unicast destination address; and finally, selecting a sending link from the available links, copying the multicast message into multiple copies, and sending the multicast message according to the sending mode of the unicast message. The method reduces the processing difficulty of the multicast message, and can share a unicast routing table with the unicast message; however, the patent increases the resource overhead of the memory in the network chip when the multicast message is copied, and increases the probability of conflict with the unicast message during arbitration.
In a patent "cell processing method and device of switching network chip" (CN 102281192 a), a method and device for processing multicast data packet (data packet in network) by a switching network chip are disclosed, the data packet is generally generated by a network card end of a server, the data packet is generally composed of a packet header and a packet load, the packet header includes key information such as an original address, a destination address, a transmission protocol, etc., and the packet load mainly includes specific data content to be transmitted. In the patent, a switching network chip receives a data packet and extracts a destination port representation and an input link number of the data packet; the switching network chip searches a multicast routing table to determine a first bit bitmap; and carrying out load balancing processing according to the first bit bitmap to obtain a second bit bitmap, and copying and forwarding the multicast packet to an output port according to the second bit bitmap. The invention can adjust the output port of the multicast grouping according to the port load condition, and the switching network chip can adapt to different working modes. But it may cause a problem for multicast packets to block subsequent packets during the duplicate forwarding process because the output ports are not all used simultaneously.
A queue management method for improving the problem of head-of-line blocking caused by multicast packets is disclosed in the patent "queue management method for improving the blocking of multicast service HOL" (CN 111131089 a). The method realizes the secondary multicast sending queue, preferentially reads the scheduling information of the secondary multicast sending queue, if all target ports in the secondary scheduling information are idle, the multicast packet is copied and forwarded, otherwise, the first-stage scheduling information is read, if the target ports in the first-stage scheduling information are partially idle, the multicast packet is forwarded to the idle ports, and the unrewarded target ports are recorded in the secondary scheduling information to wait for next scheduling. The invention can relieve the problem of head-of-line blocking caused by the fact that the multicast packet can not be forwarded to all destination ports, but the invention needs 2 times of arbitration, increases the switching time delay and the logic complexity, and simultaneously needs additional cache resources to store second-level scheduling information and the multicast packet which is not forwarded in time, and increases the resource overhead.
It was found that the handling of multicast packets in the prior art is mainly two technical routes: the routing strategy of the multicast packets is optimized from the transmission mechanism, and the replication forwarding process of the multicast packets is optimized on the scheduling mechanism. The existing switch chip architecture generally stores multicast packets and unicast packets into a queue in a unified way when caching the multicast packets and the unicast packets, and the unicast packets are blocked when the multicast packets are duplicated and transmitted due to optimization on a transmission mechanism; meanwhile, the existing switching chip architecture usually adopts a centralized arbitration and distribution mode, the head packets of the queues of all input ports compete for output port arbitration, and the optimization of the scheduling mechanism leads to more complex scheduling and arbitration logic and occupies more cache resources.
Disclosure of Invention
The invention aims to overcome the blocking influence on multicast grouping in the existing multicast grouping processing process, and simultaneously reduces the complexity of arbitration logic by a distributed two-stage arbitration mode, and provides a multicast grouping switching method and a system.
In view of the deficiencies of the prior art, the present invention provides a data packet switching method, which comprises:
and 3, after the data packet is authorized, distributing the data packet to a sub-switching module in a certain row in the switching system according to the destination address and using the data packet as a destination sub-switching module, wherein the destination sub-switching module stores the data packet to another independent queue, and outputs the data packet after waiting for output port arbitration.
The data packet switching method, wherein the sub-switching module comprises: the system comprises an input buffer queue In _ Q, an input queue arbitration module In _ Arb, a Sub-switching system Sub _ Xbr, a Sub-port arbitration module P _ Arb, an output queue buffer Out _ Q, an output queue arbitration module Out _ Arb, a Row multicast packet control module Row _ Ctrl and a column multicast packet control module Col _ Ctrl;
each sub-switching module corresponds to an input port, after a data packet enters the sub-switching module from the input port, the row multicast packet control module buffers the data packet into a corresponding input buffer queue according to the packet type of the data packet, each sub-switching module has a plurality of input buffer queues in total, and each input buffer queue stores the data packet in a first-in first-out mode; head grouping competition input queue arbitration module of each input buffer queue authorizes, wherein competition priority of multicast grouping is higher than that of unicast grouping, the input queue arbitration module, the sub-port arbitration module and the row multicast grouping control module authorize according to whether the target port of each head grouping participating in competition is idle or not, all arbitration results are authorized to the head grouping of the corresponding input buffer queue, the authorized data grouping is stored in the output buffer queue according to the data grouping type, and each output buffer queue stores the data grouping according to a first-in first-out mode; the head packet of each output queue buffer competes for the authorization of the output queue arbitration module, and the head packet of the output queue buffer is output after being authorized to reach an output port to finish transmission.
The row multicast grouping control module and the column multicast grouping control module are used for distributing and authorizing multicast groups, when the multicast groups enter the sub-switching modules, the row multicast grouping control module simultaneously distributes the multicast groups to the corresponding sub-switching modules in the same row according to address bitmaps carried by the multicast groups, meanwhile, the row multicast grouping control module intercepts corresponding parts from the address bitmaps to form new bitmap information, and the bitmap information enters the sub-switching modules along with the multicast groups; after the multicast packet enters the sub-switching module, the multicast packet can enter the sub-switching system to be transmitted to a target sub-switching module only by authorization of the sub-port arbitration module, the output queue arbitration module and the row multicast packet control module, wherein the row multicast packet control module judges whether a port corresponding to the target sub-switching module is idle or not according to the bitmap information, so that the authorization result of the multicast packet is determined.
The data packet switching method, wherein the arbitration specific process comprises:
step S1, the input queue arbitration module sequentially checks whether all input buffer queues have queue head data packets according to the sequence from high priority to low priority, if yes, then step S2 is executed; otherwise, continuing the next round of inspection;
step S2, the input queue arbitration module extracts the row _ route _ map of the head packet and passes it to the sub-port arbitration module, and executes step S3;
step S3, the sub-port arbitration module compares the row _ route _ map with the states of each output port in the sub-switching system, if each valid row number in the row _ route _ map and the output port of the sub-switching system corresponding to the valid row number are in the idle state, the arbitration is successful, and step S4 is executed; otherwise, the arbitration fails, and step S1 is executed;
step S4, the sub-port arbitration module gives the row _ route _ map to the row multicast grouping control module for arbitration, and executes step S5;
step S5, the row multicast grouping control module compares the row _ route _ map with the corresponding output queue buffer status of the destination sub-switch module of the corresponding row, if each valid row number in the row _ route _ map and the output queue buffer status corresponding to the valid row number is idle, the arbitration is successful, and step S6 is executed; otherwise, executing step S1;
step S6, after the head group of the queue gets the arbitration authorization, it is output to the sub-exchange system from the input buffer queue, and step S7 is executed;
step S7, the sub-switching system directly distributes the corresponding effective line number in the row _ route _ map of the data packet to the corresponding output port, and executes step S8;
step S8, the data packet is forwarded to the destination sub-switch module through the sub-switch system and stored in the corresponding output queue buffer, and step S9 is executed;
step S9, the output queue arbitration module checks in turn whether there is a queue head data packet in each output queue buffer according to the sequence of the priority from high to low, until detecting the first head data packet, then executes step S10; otherwise, continuing the next round of inspection;
and step S10, the data packet at the head of the queue is arbitrated and authorized by the output queue arbitration module, and the data packet at the head of the queue is transmitted to the output bus to finish the transmission.
5. The data packet switching method according to claim 4, wherein the address bitmap has a length of N x M, M and N are the number of rows and columns of the switching system, respectively, destination ports are marked as 0 to N x M-1, port status is represented by 1bit data, 1 represents valid, 0 represents invalid; after the data packet enters the sub-switching module located in the ith row and the jth column, the row multicast packet control module respectively extracts the port state of each field in the address bitmap, and performs bitwise OR operation on each section of data to obtain the col _ route _ map; wherein i is more than or equal to 0 and less than or equal to M-1, j is more than or equal to 0 and less than or equal to N-1, and i and j are integers.
The invention also provides a data packet switching system, which comprises:
the module 1 is used for constructing an exchange system consisting of a plurality of sub-exchange modules, the sub-exchange modules of the exchange system are arranged according to a row-column rule, each row of sub-exchange modules is provided with an input distribution module, and the sub-exchange modules in each row of the exchange system are connected in pairs;
a module 2, configured to enter a data packet to be exchanged into the switching system through an input distribution module, and according to a destination address carried by the data packet, distribute the data packet to a certain sub-switching module in a row in which the input distribution module is located and use the sub-switching module as an initial switching module, where the initial switching module stores the data packet in a single queue to wait for port arbitration authorization;
and the module 3 is used for distributing the data packet to a sub-switch module in a certain row in the switching system according to the destination address after the data packet is authorized, and using the data packet as a destination sub-switch module, wherein the destination sub-switch module stores the data packet into another independent queue, and outputs the data packet after waiting for output port arbitration.
The data packet switching system, wherein the sub-switching module comprises: the system comprises an input buffer queue In _ Q, an input queue arbitration module In _ Arb, a Sub-switching system Sub _ Xbr, a Sub-port arbitration module P _ Arb, an output queue buffer Out _ Q, an output queue arbitration module Out _ Arb, a Row multicast packet control module Row _ Ctrl and a column multicast packet control module Col _ Ctrl;
each sub-switching module corresponds to an input port, after a data packet enters the sub-switching module from the input port, the row multicast packet control module buffers the data packet into a corresponding input buffer queue according to the packet type of the data packet, each sub-switching module has a plurality of input buffer queues in total, and each input buffer queue stores the data packet in a first-in first-out mode; head grouping competition input queue arbitration module of each input buffer queue authorizes, wherein competition priority of multicast grouping is higher than that of unicast grouping, the input queue arbitration module, the sub-port arbitration module and the row multicast grouping control module authorize according to whether the target port of each head grouping participating in competition is idle or not, all arbitration results are authorized to the head grouping of the corresponding input buffer queue, the authorized data grouping is stored in the output buffer queue according to the data grouping type, and each output buffer queue stores the data grouping according to a first-in first-out mode; the head packet of each output queue buffer competes for the authorization of the output queue arbitration module, and the head packet of the output queue buffer is output after being authorized to reach an output port to finish transmission.
The row multicast grouping control module and the column multicast grouping control module are used for distributing and authorizing multicast groups, when the multicast groups enter the sub-switching modules, the row multicast grouping control module simultaneously distributes the multicast groups to the corresponding sub-switching modules in the same row according to address bitmaps carried by the multicast groups, meanwhile, the row multicast grouping control module intercepts corresponding parts from the address bitmaps to form new bitmap information, and the bitmap information enters the sub-switching modules along with the multicast groups; after the multicast packet enters the sub-switching module, the multicast packet can enter the sub-switching system to be transmitted to a target sub-switching module only by authorization of the sub-port arbitration module, the output queue arbitration module and the row multicast packet control module, wherein the row multicast packet control module judges whether a port corresponding to the target sub-switching module is idle or not according to the bitmap information, so that the authorization result of the multicast packet is determined.
The data packet switching system, wherein the arbitration specifically comprises:
a module S1, configured to check sequentially, according to the order of priority from high to low, whether all input buffer queues have a queue head data packet, and if yes, invoke a module S2; otherwise, continuing the next round of inspection;
a module S2, configured to extract the row _ route _ map of the header packet and submit the same to the sub-port arbitration module, and invoke the module S3;
a module S3, configured to compare the state of the row _ route _ map with the state of each output port in the sub-switching system, and if each valid row number in the row _ route _ map and the output port of the sub-switching system corresponding to the valid row number is in an idle state, the arbitration is successful, and a module S4 is invoked; otherwise, the arbitration fails, and the module S1 is called;
a module S4, configured to give row _ route _ map to the row multicast group control module for arbitration, and invoke the module S5;
a module S5, configured to compare the row _ route _ map with the corresponding output queue cache state of the destination sub-switch module of the corresponding row, if each valid row number in the row _ route _ map and the output queue cache state corresponding to the valid row number is idle, the arbitration is successful, and a module S6 is invoked; otherwise, calling the module S1;
a module S6, configured to output the packet from the input buffer queue to the sub-switching system after the head packet of the queue gets the arbitration grant, and invoke the module S7;
a module S7, configured to enable the sub-switching system to directly distribute to a corresponding output port according to the valid line number corresponding to the row _ route _ map of the data packet, and invoke the module S8;
a module S8, configured to forward the data packet to a destination sub-switching module through the sub-switching system, store the data packet in a corresponding output queue buffer, and invoke the module S9;
a module S9, configured to check sequentially, according to the order of priority from high to low, whether each output queue buffer has a queue header data packet, and call a module S10 until a first header data packet is detected; otherwise, continuing the next round of inspection;
and a module S10, configured to enable the data packet at the head of the queue to obtain the arbitration grant of the output queue arbitration module, and transmit the data packet at the head of the queue to the output bus, so as to complete transmission.
In the data packet switching system, the length of the address bitmap is N × M, M and N are the number of rows and columns of the switching system respectively, a destination port is marked as 0 to N × M-1, the port state is represented by 1bit data, 1 represents valid, and 0 represents invalid; after the data packet enters the sub-switching module located in the ith row and the jth column, the row multicast packet control module respectively extracts the port state of each field in the address bitmap, and performs bitwise OR operation on each section of data to obtain the col _ route _ map; wherein i is more than or equal to 0 and less than or equal to M-1, j is more than or equal to 0 and less than or equal to N-1, and i and j are integers.
According to the scheme, the invention has the advantages that:
the invention starts from a switching chip architecture belonging to a hardware bottom layer, and designs a switching architecture consisting of distributed sub-switching modules. Compared with the existing multicast grouping transmission optimization technology based on a centralized arbitration distribution switching architecture, the invention divides the complex centralized arbitration logic into two-stage distributed arbitration, thereby reducing the arbitration complexity; in the invention, the multicast packet and the unicast packet are respectively cached to different input cache queues and output cache queues, thereby avoiding the problem that the subsequent unicast packet transmission is influenced due to the blockage of the multicast packet, simultaneously improving the arbitration priority of the multicast packet and improving the transmission efficiency of the switching architecture; the invention divides the distribution process into 2 stages, improves the distribution efficiency, and saves the storage resource by adopting the same route _ map format.
Drawings
FIG. 1 is a schematic diagram of the system of the present invention;
FIG. 2 is a schematic diagram of a sub-switch module of the present invention;
FIG. 3 is a schematic diagram of route _ map, col _ route _ map, and row _ route _ map according to the present invention;
FIG. 4 is an arbitration flow chart of the present invention.
Detailed Description
The inventor finds that the above technical problem can be solved by optimally designing the switch chip architecture on the hardware level by studying the switch chip architecture and fully understanding the processing flow of the data packet in the switch chip on the hardware level. In the invention, the switching chip architecture is composed of a plurality of sub-switching modules, the sub-switching modules are arranged in order according to rows and columns, and multicast packets enter from one sub-switching module and reach an output port after passing through two stages of sub-switching modules. The technical difficulty of the invention is mainly that the switching system is divided into a plurality of sub-switching modules, and the complex arbitration and scheduling process of multicast grouping is dispersed into two stages of sub-switching modules, thereby reducing the logic complexity of scheduling and arbitration; meanwhile, the invention adopts the design of multi-queue storage of multicast packets and unicast packets, reduces the influence of the multicast packets on the unicast packets, and avoids the head of the queue from being blocked due to the multicast packets. In order to achieve the above technical effects, the present application proposes the following key points:
the key point 1 is that the switching system is divided into a plurality of sub-switching modules, the sub-switching modules are arranged according to the row and column rule, the whole switching system has P ports, and is divided into N × M sub-switching modules, wherein P is N × M, M is the number of rows, N is the number of columns, and M and N are positive integers greater than or equal to 1. Each sub-switch module corresponds to an input port and an output port of the switch system, and the sub-switch modules are connected through a connecting line. The data packet enters the switching system from the input port at first, and the input distribution module of the row where the input port is located distributes the data packet to the sub-switching module of the row destination of the row according to the destination address carried by the data packet. After receiving the data packet, the row-purpose sub-switching module stores the data packet into a single storage queue to wait for the authorization of the port arbitration module, and after being authorized, the data packet is distributed to the row-purpose sub-switching module in a certain row; the column-destination sub-switch module stores the data packet into a separate queue after receiving the data packet, and outputs the data packet to the output port after waiting for the output port arbitration.
The switching system composed of the sub-switching modules can split the complex centralized arbitration logic into two-stage distributed arbitration, reduces the number of queues competing each-stage arbitration, and reduces the arbitration complexity of each stage, thereby improving the arbitration efficiency of the whole architecture.
The key point 2, the sub-switching module includes: the system comprises an input buffer queue In _ Q, an input queue arbitration module In _ Arb, a Sub-switching system Sub _ Xbr, a Sub-port arbitration module P _ Arb, an output queue buffer Out _ Q, an output queue arbitration module Out _ Arb, a Row multicast packet control module Row _ Ctrl, a column multicast packet control module Col _ Ctrl and the like. According to the key point 1, each sub-switch module corresponds to an input port, after a data packet enters the sub-switch module from the input port, a Row _ Ctrl is cached In a corresponding In _ Q according to the multicast or unicast packet type of the data packet, each sub-switch module has a × N In _ Q, a is a positive integer greater than 1, each In _ Q stores the data packet In a first-In first-out manner, wherein the multicast packet and the unicast packet are respectively stored In different In _ Q; head packets of each In _ Q compete for authorization of the In _ Arb, wherein the competition priority of multicast packets is higher than that of unicast packets, the In _ Arb, the P _ Arb and the Col _ Ctrl are authorized according to whether a destination port of each head packet participating In competition is idle or not, the head packets of the corresponding In _ Q are authorized by integrating the arbitration results of the 3 modules, the authorized data packets enter Sub _ Xbr and are transmitted to corresponding destination Sub-switching modules, the data packets enter the destination Sub-modules and are stored into Out _ Q according to the types of the data packets, each Sub-switching module has b × M Out _ Q, and b is a positive integer greater than 1; wherein, the multicast grouping and the unicast grouping are respectively stored into different Out _ Q, and each Out _ Q stores the data grouping according to a first-in first-Out mode; head packets of each Out _ Q compete for authorization of the Out _ Arb, wherein the competition priority of the multicast packets is higher than that of the unicast packets, and the head packets are output after being authorized by the Out _ Arb and reach an output port to finish transmission.
The sub-switching module respectively caches the multicast packet and the unicast packet to different input cache queues and output cache queues, so that the competition of other unicast packets can not be influenced even if the competition is not successful in the competition arbitration of the multicast packet, and the problem that the subsequent unicast packet transmission is influenced due to the blockage of the multicast packet is solved; meanwhile, considering that the multicast grouping can be authorized only by one idle destination port in the arbitration process of the unicast grouping, and the multicast grouping generally needs a plurality of idle destination ports to complete the authorization.
And the key point 3, according to the sub-switching module and the data packet transmission process described in the key point 1 and the key point 2, wherein the Row multicast packet control module Row _ Ctrl and the column multicast packet control module Col _ Ctrl are mainly responsible for distribution and authorization control of multicast packets. After the multicast packet enters the sub-switching module, the Row _ Ctrl module simultaneously distributes the multicast packet to the corresponding sub-switching modules in the same Row according to the address bitmap information route _ map carried by the multicast packet, and meanwhile, the Row _ Ctrl module intercepts the corresponding part from the route _ map to form new bitmap information col _ map, and the col _ map enters the sub-switching module along with the multicast packet; after the multicast packet enters the Sub-switch module, the authorization of the 3 modules, i.e., In _ Arb, P _ Arb, and Col _ Ctrl, is required to enter Sub-Xbr for transmission to the destination Sub-switch module, where Col _ Ctrl determines whether the port corresponding to the destination Sub-switch module is idle according to Col _ map, thereby determining the authorization result of the multicast packet.
In order to save precious storage resources, the multicast packet and the unicast packet adopt the same route _ map format, and the Row _ Ctrl and the Col _ Ctrl also process the unicast packet, namely the unicast packet is regarded as the multicast packet with only 1 destination port. The Row _ Ctrl and the Col _ Ctrl designed by the invention divide the multi-time distribution of the multicast grouping into 2 stages, and compared with a centralized arbitration and distribution mechanism of the existing exchange architecture, the arbitration complexity is reduced, and the distribution efficiency is improved; meanwhile, the multicast grouping and the unicast grouping adopt the same route _ map format, and compared with the mode of respectively maintaining the multicast grouping routing table and the unicast grouping routing table in the existing switching architecture, the complexity of reading the routing information is reduced, and precious storage resources are saved.
In order to make the aforementioned features and effects of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 is a configuration diagram of a switching system according to an embodiment of the present invention. The switching system comprises M multiplied by N sub-switching modules, wherein M is a row number and is a positive integer larger than 1, and N is a column number and is a positive integer larger than 1. Each row is provided with 1 input distribution module 11, the input distribution module is connected with N input ports 10 corresponding to N sub-switching modules 12 in the row, and the input distribution module receives data packets input from the input ports; the input distribution module outputs N data buses, and each sub-switching module of the row is connected with the corresponding data bus; the data packet is input from the input port, distributed to the corresponding sub-switching module 12 through the input distribution module, routed and transmitted in the sub-switching module, and finally reaches the target sub-switching module; each row is provided with N output ports 13, and the output ports are connected with the output of each sub-switching module of the row through a data bus; and after the data packet is output from the target sub-switching module, the data packet reaches an output port through a data bus, and the data transmission is completed.
For example, as shown in fig. 1, if the input port enters an input port from port number 0 (corresponding to the sub-switch module in the first row and column 1 in the figure) and outputs from port N +1 (corresponding to the sub-switch module in the second row and column 2 in the figure), the flow is as follows: the data packet is sent from the input port 10 (i.e. the input port 10 in the figure), and then the input distribution module distributes the data packet to the row-destination sub-switch module of row 0 and column 1 (i.e. the sub-switch module of the first row and column 2 in the figure) according to the output port number, and then the data packet is switched and forwarded to the column-destination sub-switch module of the first row and column 1 (i.e. the sub-switch module of the second row and column 2 in the figure) in the row-destination sub-switch module, and then the data packet is output to the output port through the column-destination sub-switch module, so that the transmission is completed.
Specifically, fig. 2 is a system configuration diagram of an embodiment of a sub-switch module according to the present invention. Each input port is connected with an input port bus of a Row of the sub-switching module through a Row multicast packet control module Row _ Ctrl 201, receives data packets from an input distribution module, and then stores the data packets into corresponding In _ Q; each output port receives data packets from other sub-switching modules in the same column as the sub-switching module, which are controlled by the column multicast packet control module Col _ Ctrl 204, and then stores the received data packets into corresponding Out _ Q; after entering the In _ Q, the data packets are stored according to a first-In first-out rule, and the head-of-line data packets of a In _ Q of each input port participate In arbitration of the In _ Arb 203 at the same time; after a certain In _ Q head-of-line data packet is arbitrated and authorized, the data packet enters Sub _ Xbar 207, and is forwarded by Sub _ Xbar, distributed to an output port of a destination Sub-switch module and stored In a corresponding Out _ Q; b queue head data packets of Out _ Q of each output port simultaneously participate in the arbitration of the Out _ Arb 206; and when the head of queue data packet of a certain Out _ Q is authorized by arbitration, outputting the data packet to finish the data exchange.
Further, the Row multicast packet control module Row _ Ctrl 201 and the column multicast packet control module Col _ Ctrl 204 of the sub-switch module need to distribute and arbitrate data according to the destination address information of the data packet. In order to save storage resources and improve arbitration efficiency, the unicast packets and the multicast packets in the present invention use a uniform format route _ map as shown in fig. 3 to represent address information. In this embodiment, the route _ map length of the data packet is N × M, the destination port is recorded as 0 to N × M-1, the port status is represented by 1bit data, 1 represents valid, i.e. the port is the destination port of the data packet, and 0 represents invalid, i.e. the port is not the destination port of the data packet. After a data packet enters a sub-switch module located in the ith Row and jth column (i is more than or equal to 0 and less than or equal to M-1, j is more than or equal to 0 and less than or equal to N-1, and i and j are integers), the Row _ Ctrl respectively extracts port states of route _ map [0, N,2N, …, Nx (M-1) ], [1, N +1,2N +1, …, Nx (M-1) +1], …, [ N-1,2N-1,3N-1, …, N × M-1] fields, and performs bitwise OR operation on each piece of data to obtain col _ route _ map, wherein the length of col _ route _ map is N, each bit is represented by 1bit, 1 represents valid, namely the column contains a target sub-switch module, 0 represents invalid, namely the column does not contain the target sub-switch module. As shown in fig. 3, Row _ Ctrl distributes the data packet to the sub-switch module in the corresponding local Row whose column state is valid according to the state corresponding to each bit in col _ route _ map, and Row _ Ctrl distributes the corresponding field of route _ map in the column where the extracted target sub-switch module is located to the Row routing bit bitmap Row _ route _ map to the corresponding sub-switch module along with the data packet, in this embodiment, if the c-th bit (c is greater than or equal to 0 and less than or equal to N-1, and c is an integer) in col _ route _ map is valid, then Row _ Ctrl extracts the field of route _ map [ c, c + N, c +2N, …, c + N × (M-1) ] as Row _ route _ map. The row _ route _ map format is shown in fig. 3, where the row _ route _ map is M in length, where each bit is represented by 1bit, 1 represents that the row is valid, i.e., the row contains the destination sub-switch module, and 0 represents that the row does not contain the destination sub-switch module.
The data packets are queued In In _ Q for arbitration of In _ Arb, P _ Arb and Col _ Ctrl, wherein Col _ Ctrl is judged according to the state of the destination sub-switch module of each row In row _ route _ map, if the corresponding Out _ Q of the destination sub-switch module of all the valid rows In row _ route _ map is In the idle state, the arbitration is successful, otherwise the arbitration fails.
Further, the arbitration process of the data packet In _ Q mainly includes queue arbitration In _ Arb, port arbitration P _ Arb and Col _ Ctrl arbitration In Sub _ Xbr, wherein the specific flow of arbitration is shown In fig. 4.
Step S1, the In _ Arb checks whether a In _ Q packets have queue head data packets In sequence according to the order of priority from high to low, until detecting the first head data packet, then execute step S2; otherwise, continuing the next round of inspection;
step S2, the In _ Arb extracts the row _ route _ map of the header packet to be handed to the P _ Arb, and step S3 is executed;
step S3, P _ Arb compares the output port status of each of the row _ route _ map and Sub _ Xbar, if the valid row number of each bit in the row _ route _ map and the corresponding output port of Sub _ Xbar is in idle status, P _ Arb arbitration succeeds, and step S4 is executed; otherwise, the P _ Arb arbitration fails, go to step S1;
step S4, the P _ Arb gives the row _ route _ map to the Col _ Ctrl arbitration, and step S5 is executed;
step S5, comparing the Col _ Ctrl with the row _ route _ map and the corresponding Out _ Q state of the destination sub-switch module of the corresponding row, if each valid row number in the row _ route _ map and the corresponding Out _ Q state is idle, the Col _ Ctrl arbitration succeeds, and step S6 is executed; otherwise, executing step S1;
step S6, after the head group of the queue gets the arbitration authorization, the head group is outputted from In _ Q to Sub _ Xbar, and step S7 is executed;
step S7, directly distributing the Sub _ Xbar to the corresponding output port according to the corresponding valid line number in the row _ route _ map of the data packet, and executing step S8;
step S8, the data packet is forwarded to the destination Sub-switch module through Sub _ Xbar and stored into corresponding Out _ Q, and step S9 is executed;
step S9, the Out _ Arb checks if b Out _ Q have queue head data packets according to the sequence of the priority from high to low, until the first head data packet is detected, then step S10 is executed; otherwise, continuing the next round of inspection;
and step S10, obtaining the Out _ Arb arbitration for the data packet at the head of the queue, transmitting the data packet to an output bus, and finishing transmission.
The following are system examples corresponding to the above method examples, and this embodiment can be implemented in cooperation with the above embodiments. The related technical details mentioned in the above embodiments are still valid in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related-art details mentioned in the present embodiment can also be applied to the above-described embodiments.
The invention also provides a data packet switching system, which comprises:
the module 1 is used for constructing an exchange system consisting of a plurality of sub-exchange modules, the sub-exchange modules of the exchange system are arranged according to a row-column rule, each row of sub-exchange modules is provided with an input distribution module, and the sub-exchange modules in each row of the exchange system are connected in pairs;
a module 2, configured to enter a data packet to be exchanged into the switching system through an input distribution module, and according to a destination address carried by the data packet, distribute the data packet to a sub-switching module in a row in which the input distribution module is located and use the sub-switching module as an initial switching module, where the initial switching module stores the data packet in a single queue to wait for port arbitration authorization;
and the module 3 is used for distributing the data packet to a sub-switch module in a certain row in the switching system according to the destination address after the data packet is authorized, and using the data packet as a destination sub-switch module, wherein the destination sub-switch module stores the data packet into another independent queue, and outputs the data packet after waiting for output port arbitration.
The data packet switching system, wherein the sub-switching module comprises: the system comprises an input buffer queue In _ Q, an input queue arbitration module In _ Arb, a Sub-switching system Sub _ Xbr, a Sub-port arbitration module P _ Arb, an output queue buffer Out _ Q, an output queue arbitration module Out _ Arb, a Row multicast packet control module Row _ Ctrl and a column multicast packet control module Col _ Ctrl;
each sub-switching module corresponds to an input port, after a data packet enters the sub-switching module from the input port, the row multicast packet control module buffers the data packet into a corresponding input buffer queue according to the packet type of the data packet, each sub-switching module has a plurality of input buffer queues in total, and each input buffer queue stores the data packet in a first-in first-out mode; head grouping competition input queue arbitration module of each input buffer queue authorizes, wherein competition priority of multicast grouping is higher than that of unicast grouping, the input queue arbitration module, the sub-port arbitration module and the row multicast grouping control module authorize according to whether the target port of each head grouping participating in competition is idle or not, all arbitration results are authorized to the head grouping of the corresponding input buffer queue, the authorized data grouping is stored in the output buffer queue according to the data grouping type, and each output buffer queue stores the data grouping according to a first-in first-out mode; the head packet of each output queue buffer competes for the authorization of the output queue arbitration module, and the head packet of the output queue buffer is output after being authorized to reach an output port to finish transmission.
The row multicast grouping control module and the column multicast grouping control module are used for distributing and authorizing multicast groups, when the multicast groups enter the sub-switching modules, the row multicast grouping control module simultaneously distributes the multicast groups to the corresponding sub-switching modules in the same row according to address bitmaps carried by the multicast groups, meanwhile, the row multicast grouping control module intercepts corresponding parts from the address bitmaps to form new bitmap information, and the bitmap information enters the sub-switching modules along with the multicast groups; after the multicast packet enters the sub-switching module, the multicast packet can enter the sub-switching system to be transmitted to a target sub-switching module only by authorization of the sub-port arbitration module, the output queue arbitration module and the row multicast packet control module, wherein the row multicast packet control module judges whether a port corresponding to the target sub-switching module is idle or not according to the bitmap information, so that the authorization result of the multicast packet is determined.
The data packet switching system, wherein the arbitration specifically comprises:
a module S1, configured to check sequentially, according to the order of priority from high to low, whether all input buffer queues have a queue head data packet, and if yes, invoke a module S2; otherwise, continuing the next round of inspection;
a module S2, configured to extract the row _ route _ map of the header packet and submit the same to the sub-port arbitration module, and invoke the module S3;
a module S3, configured to compare the state of the row _ route _ map with the state of each output port in the sub-switching system, and if each valid row number in the row _ route _ map and the output port of the sub-switching system corresponding to the valid row number is in an idle state, the arbitration is successful, and a module S4 is invoked; otherwise, the arbitration fails, and the module S1 is called;
a module S4, configured to give row _ route _ map to the row multicast group control module for arbitration, and invoke the module S5;
a module S5, configured to compare the row _ route _ map with the corresponding output queue cache state of the destination sub-switch module of the corresponding row, if each valid row number in the row _ route _ map and the output queue cache state corresponding to the valid row number is idle, the arbitration is successful, and a module S6 is invoked; otherwise, calling the module S1;
a module S6, configured to output the packet from the input buffer queue to the sub-switching system after the head packet of the queue gets the arbitration grant, and invoke the module S7;
a module S7, configured to enable the sub-switching system to directly distribute to a corresponding output port according to the valid line number corresponding to the row _ route _ map of the data packet, and invoke the module S8;
a module S8, configured to forward the data packet to a destination sub-switching module through the sub-switching system, store the data packet in a corresponding output queue buffer, and invoke the module S9;
a module S9, configured to check sequentially, according to the order of priority from high to low, whether each output queue buffer has a queue header data packet, and call a module S10 until a first header data packet is detected; otherwise, continuing the next round of inspection;
and a module S10, configured to enable the data packet at the head of the queue to obtain the arbitration grant of the output queue arbitration module, and transmit the data packet at the head of the queue to the output bus, so as to complete transmission.
In the data packet switching system, the length of the address bitmap is N × M, M and N are the number of rows and columns of the switching system respectively, a destination port is marked as 0 to N × M-1, the port state is represented by 1bit data, 1 represents valid, and 0 represents invalid; after the data packet enters the sub-switching module located in the ith row and the jth column, the row multicast packet control module respectively extracts the port state of each field in the address bitmap, and performs bitwise OR operation on each section of data to obtain the col _ route _ map; wherein i is more than or equal to 0 and less than or equal to M-1, j is more than or equal to 0 and less than or equal to N-1, and i and j are integers.
Claims (10)
1. A method of data packet switching, comprising:
step 1, constructing an exchange system consisting of a plurality of sub-exchange modules, wherein the sub-exchange modules of the exchange system are arranged according to a row-column rule, each row of sub-exchange modules is provided with an input distribution module, and the sub-exchange modules in each row in the exchange system are connected in pairs.
Step 2, the data packet to be exchanged enters the exchange system through an input distribution module, and is distributed to a sub-exchange module in a row of the input distribution module and serves as an initial exchange module according to a destination address carried by the data packet, and the initial exchange module stores the data packet in a single queue to wait for port arbitration authorization;
and 3, after the data packet is authorized, distributing the data packet to a sub-switching module in a certain row in the switching system according to the destination address and using the data packet as a destination sub-switching module, wherein the destination sub-switching module stores the data packet to another independent queue, and outputs the data packet after waiting for output port arbitration.
2. The data packet switching method of claim 1, wherein the sub-switching module comprises: the system comprises an input buffer queue In _ Q, an input queue arbitration module In _ Arb, a Sub-switching system Sub _ Xbr, a Sub-port arbitration module P _ Arb, an output queue buffer Out _ Q, an output queue arbitration module Out _ Arb, a Row multicast packet control module Row _ Ctrl and a column multicast packet control module Col _ Ctrl;
each sub-switching module corresponds to an input port, after a data packet enters the sub-switching module from the input port, the row multicast packet control module buffers the data packet into a corresponding input buffer queue according to the packet type of the data packet, each sub-switching module has a plurality of input buffer queues in total, and each input buffer queue stores the data packet in a first-in first-out mode; head grouping competition input queue arbitration module of each input buffer queue authorizes, wherein competition priority of multicast grouping is higher than that of unicast grouping, the input queue arbitration module, the sub-port arbitration module and the row multicast grouping control module authorize according to whether the target port of each head grouping participating in competition is idle or not, all arbitration results are authorized to the head grouping of the corresponding input buffer queue, the authorized data grouping is stored in the output buffer queue according to the data grouping type, and each output buffer queue stores the data grouping according to a first-in first-out mode; the head packet of each output queue buffer competes for the authorization of the output queue arbitration module, and the head packet of the output queue buffer is output after being authorized to reach an output port to finish transmission.
3. The data packet switching method according to claim 2, wherein the row multicast packet control module and the column multicast packet control module are configured to perform distribution and authorization control on the multicast packets, and when a multicast packet enters a sub-switch module, the row multicast packet control module simultaneously distributes the multicast packet to the corresponding sub-switch modules in the same row according to an address bitmap carried by the multicast packet, and the row multicast packet control module intercepts a corresponding portion from the address bitmap to form new bitmap information, and the bitmap information enters the sub-switch modules along with the multicast packet; after the multicast packet enters the sub-switching module, the multicast packet can enter the sub-switching system to be transmitted to a target sub-switching module only by authorization of the sub-port arbitration module, the output queue arbitration module and the row multicast packet control module, wherein the row multicast packet control module judges whether a port corresponding to the target sub-switching module is idle or not according to the bitmap information, so that the authorization result of the multicast packet is determined.
4. The data packet switching method of claim 3, wherein the specific flow of arbitration comprises:
step S1, the input queue arbitration module sequentially checks whether all input buffer queues have queue head data packets according to the sequence from high priority to low priority, if yes, then step S2 is executed; otherwise, continuing the next round of inspection;
step S2, the input queue arbitration module extracts the row _ route _ map of the head packet and passes it to the sub-port arbitration module, and executes step S3;
step S3, the sub-port arbitration module compares the row _ route _ map with the states of each output port in the sub-switching system, if each valid row number in the row _ route _ map and the output port of the sub-switching system corresponding to the valid row number are in the idle state, the arbitration is successful, and step S4 is executed; otherwise, the arbitration fails, and step S1 is executed;
step S4, the sub-port arbitration module gives the row _ route _ map to the row multicast grouping control module for arbitration, and executes step S5;
step S5, the row multicast grouping control module compares the row _ route _ map with the corresponding output queue buffer status of the destination sub-switch module of the corresponding row, if each valid row number in the row _ route _ map and the output queue buffer status corresponding to the valid row number is idle, the arbitration is successful, and step S6 is executed; otherwise, executing step S1;
step S6, after the head group of the queue gets the arbitration authorization, it is output to the sub-exchange system from the input buffer queue, and step S7 is executed;
step S7, the sub-switching system directly distributes the corresponding effective line number in the row _ route _ map of the data packet to the corresponding output port, and executes step S8;
step S8, the data packet is forwarded to the destination sub-switch module through the sub-switch system and stored in the corresponding output queue buffer, and step S9 is executed;
step S9, the output queue arbitration module checks in turn whether there is a queue head data packet in each output queue buffer according to the sequence of the priority from high to low, until detecting the first head data packet, then executes step S10; otherwise, continuing the next round of inspection;
and step S10, the data packet at the head of the queue is arbitrated and authorized by the output queue arbitration module, and the data packet at the head of the queue is transmitted to the output bus to finish the transmission.
5. The data packet switching method according to claim 4, wherein the address bitmap has a length of nxm, M and N are the number of rows and columns of the switching system, respectively, the destination ports are marked as 0 to nxm-1, the port status is represented by 1bit data, 1 represents valid, and 0 represents invalid; after the data packet enters the sub-switching module located in the ith row and the jth column, the row multicast packet control module respectively extracts the port state of each field in the address bitmap, and performs bitwise OR operation on each section of data to obtain the col _ route _ map; wherein i is more than or equal to 0 and less than or equal to M-1, j is more than or equal to 0 and less than or equal to N-1, and i and j are integers.
6. A data packet switching system, comprising:
the module 1 is used for constructing an exchange system consisting of a plurality of sub-exchange modules, the sub-exchange modules of the exchange system are arranged according to a row-column rule, each row of sub-exchange modules is provided with an input distribution module, and the sub-exchange modules in each row of the exchange system are connected in pairs;
a module 2, configured to enter a data packet to be exchanged into the switching system through an input distribution module, and according to a destination address carried by the data packet, distribute the data packet to a sub-switching module in a row in which the input distribution module is located and use the sub-switching module as an initial switching module, where the initial switching module stores the data packet in a single queue to wait for port arbitration authorization;
and the module 3 is used for distributing the data packet to a sub-switch module in a certain row in the switching system according to the destination address after the data packet is authorized, and using the data packet as a destination sub-switch module, wherein the destination sub-switch module stores the data packet into another independent queue, and outputs the data packet after waiting for output port arbitration.
7. The data packet switching system of claim 6, wherein the sub-switching module comprises: the system comprises an input buffer queue In _ Q, an input queue arbitration module In _ Arb, a Sub-switching system Sub _ Xbr, a Sub-port arbitration module P _ Arb, an output queue buffer Out _ Q, an output queue arbitration module Out _ Arb, a Row multicast packet control module Row _ Ctrl and a column multicast packet control module Col _ Ctrl;
each sub-switching module corresponds to an input port, after a data packet enters the sub-switching module from the input port, the row multicast packet control module buffers the data packet into a corresponding input buffer queue according to the packet type of the data packet, each sub-switching module has a plurality of input buffer queues in total, and each input buffer queue stores the data packet in a first-in first-out mode; head grouping competition input queue arbitration module of each input buffer queue authorizes, wherein competition priority of multicast grouping is higher than that of unicast grouping, the input queue arbitration module, the sub-port arbitration module and the row multicast grouping control module authorize according to whether the target port of each head grouping participating in competition is idle or not, all arbitration results are authorized to the head grouping of the corresponding input buffer queue, the authorized data grouping is stored in the output buffer queue according to the data grouping type, and each output buffer queue stores the data grouping according to a first-in first-out mode; the head packet of each output queue buffer competes for the authorization of the output queue arbitration module, and the head packet of the output queue buffer is output after being authorized to reach an output port to finish transmission.
8. The data packet switching system according to claim 7, wherein the row multicast packet control module and the column multicast packet control module are configured to perform distribution and authorization control on the multicast packets, and when the multicast packets enter the sub-switching modules, the row multicast packet control module simultaneously distributes the multicast packets to the corresponding sub-switching modules in the same row according to the address bitmap carried by the multicast packets, and the row multicast packet control module intercepts corresponding parts from the address bitmap to form new bitmap information, and the bitmap information enters the sub-switching modules along with the multicast packets; after the multicast packet enters the sub-switching module, the multicast packet can enter the sub-switching system to be transmitted to a target sub-switching module only by authorization of the sub-port arbitration module, the output queue arbitration module and the row multicast packet control module, wherein the row multicast packet control module judges whether a port corresponding to the target sub-switching module is idle or not according to the bitmap information, so that the authorization result of the multicast packet is determined.
9. The data packet switching system according to claim 8, wherein the arbitration specifically comprises:
a module S1, configured to check sequentially, according to the order of priority from high to low, whether all input buffer queues have a queue head data packet, and if yes, invoke a module S2; otherwise, continuing the next round of inspection;
a module S2, configured to extract the row _ route _ map of the header packet and submit the same to the sub-port arbitration module, and invoke the module S3;
a module S3, configured to compare the state of the row _ route _ map with the state of each output port in the sub-switching system, and if each valid row number in the row _ route _ map and the output port of the sub-switching system corresponding to the valid row number is in an idle state, the arbitration is successful, and a module S4 is invoked; otherwise, the arbitration fails, and the module S1 is called;
a module S4, configured to give row _ route _ map to the row multicast group control module for arbitration, and invoke the module S5;
a module S5, configured to compare the row _ route _ map with the corresponding output queue cache state of the destination sub-switch module of the corresponding row, if each valid row number in the row _ route _ map and the output queue cache state corresponding to the valid row number is idle, the arbitration is successful, and a module S6 is invoked; otherwise, calling the module S1;
a module S6, configured to output the packet from the input buffer queue to the sub-switching system after the head packet of the queue gets the arbitration grant, and invoke the module S7;
a module S7, configured to enable the sub-switching system to directly distribute to a corresponding output port according to the valid line number corresponding to the row _ route _ map of the data packet, and invoke the module S8;
a module S8, configured to forward the data packet to a destination sub-switching module through the sub-switching system, store the data packet in a corresponding output queue buffer, and invoke the module S9;
a module S9, configured to check sequentially, according to the order of priority from high to low, whether each output queue buffer has a queue header data packet, and call a module S10 until a first header data packet is detected; otherwise, continuing the next round of inspection;
and a module S10, configured to enable the data packet at the head of the queue to obtain the arbitration grant of the output queue arbitration module, and transmit the data packet at the head of the queue to the output bus, so as to complete transmission.
10. The data packet switching system of claim 8 wherein the address bitmap has a length of nxm, M and N are the number of rows and columns of the switching system, respectively, destination ports are numbered 0 to nxm-1, port status is indicated by 1bit data, 1 indicates valid, and 0 indicates invalid; after the data packet enters the sub-switching module located in the ith row and the jth column, the row multicast packet control module respectively extracts the port state of each field in the address bitmap, and performs bitwise OR operation on each section of data to obtain the col _ route _ map; wherein i is more than or equal to 0 and less than or equal to M-1, j is more than or equal to 0 and less than or equal to N-1, and i and j are integers.
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