CN109509759B - Array substrate, preparation method thereof, display panel and display device - Google Patents
Array substrate, preparation method thereof, display panel and display device Download PDFInfo
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- CN109509759B CN109509759B CN201910008261.0A CN201910008261A CN109509759B CN 109509759 B CN109509759 B CN 109509759B CN 201910008261 A CN201910008261 A CN 201910008261A CN 109509759 B CN109509759 B CN 109509759B
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- 239000000758 substrate Substances 0.000 title claims abstract description 100
- 238000002360 preparation method Methods 0.000 title claims abstract description 23
- 125000006850 spacer group Chemical group 0.000 claims abstract description 61
- 239000010409 thin film Substances 0.000 claims abstract description 26
- 239000010408 film Substances 0.000 claims abstract description 14
- 239000012212 insulator Substances 0.000 claims description 9
- 230000035939 shock Effects 0.000 claims description 9
- 238000000034 method Methods 0.000 abstract description 24
- 239000010410 layer Substances 0.000 description 130
- 230000000994 depressogenic effect Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000000059 patterning Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 241000251468 Actinopterygii Species 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000007888 film coating Substances 0.000 description 2
- 238000009501 film coating Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000012044 organic layer Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000006748 scratching Methods 0.000 description 2
- 230000002393 scratching effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention relates to the technical field of display, and discloses an array substrate, a preparation method of the array substrate, a display panel and a display device. The array substrate comprises thin film transistors distributed in an array, and an organic insulating layer, a first electrode layer and a first insulating layer which are laminated on the thin film transistors, wherein: at least one of the organic insulating layer, the first electrode layer and the first insulating layer is provided with a slot corresponding to the position of the spacer, so that a concave part is formed on the surface of the array substrate at the position corresponding to the spacer. The concave part is formed on the surface of the array substrate, and when the array substrate is used for box alignment, the top of the spacer can be inserted into the concave part, so that the spacer is limited and is not easy to slide, the alignment film in the display area can be prevented from being scratched by the spacer, and the yield and the stability of products are improved. Compared with the array substrate preparation process in the prior art, the preparation process of the array substrate is not added with process flows, and the preparation process is not changed, so that the method has a great cost advantage.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a preparation method of the array substrate, a display panel and a display device.
Background
At present, an organic insulating film layer is generally adopted for covering a thin film transistor array in a high-resolution array substrate product, the stress of the organic insulating film after coating, exposure, development and curing is very low, but the thickness can reach more than 3.0um, the capacitance can be effectively reduced, and the product requirements of high resolution and low power consumption are met. However, the organic film coating has a high step coverage, and the upper surface of the organic film coating is smooth, so that the surface of the finally formed array substrate is smooth, and after the array substrate and the color film substrate are aligned, the top of the spacer (PS) is not fixed, so that the PS is easy to slide on the surface of the array substrate, and the alignment film in the display area is scratched, thereby causing light leakage in the display area.
Disclosure of Invention
The invention discloses an array substrate, a preparation method of the array substrate, a display panel and a display device, and aims to enhance the stability of a spacer and prevent the spacer from moving to scratch an alignment film.
In order to achieve the purpose, the invention provides the following technical scheme:
an array substrate comprises thin film transistors distributed in an array, and an organic insulating layer, a first electrode layer and a first insulating layer which are sequentially stacked on the thin film transistors, wherein:
at least one of the organic insulating layer, the first electrode layer and the first insulating layer is provided with a slot corresponding to the position of the spacer, so that a concave part is formed on the surface of the array substrate corresponding to the position of the spacer.
Above-mentioned array substrate surface is formed with the depressed part on the position that corresponds with the shock insulator, and when to the box, the top of shock insulator can be inserted in this depressed part to by spacing, difficult production slides, and then can avoid shock insulator fish tail display area to join in marriage the membrane, promote product yield and stability. Compared with the array substrate preparation process in the prior art, the preparation process of the array substrate is not added with a process flow, and the preparation process is not changed, and the preparation of the array substrate can be realized only by correspondingly changing the mask pattern of at least one layer of the organic insulating layer, the first electrode layer and the first insulating layer, so that the preparation process has a great cost advantage.
Optionally, a slot corresponding to the position of the spacer is formed in the organic insulating layer, and the slot is a groove.
Optionally, the inner surface of the groove is an arc-shaped surface.
Optionally, a slot corresponding to the position of the spacer is formed in the first insulating layer, and the slot is a via hole.
Optionally, the first insulating layer and the first electrode layer are both provided with a slot corresponding to the position of the spacer, and the slot is a via hole.
Optionally, a second electrode layer stacked on the first insulating layer is further disposed on the array substrate; and the second electrode layer is provided with a via hole corresponding to the position of the spacer, or the second electrode layer covers the depressed part region.
Optionally, when the second electrode layer covers the recessed portion region, the via holes of the first insulating layer and the first electrode layer are trepanning holes.
Optionally, the first electrode layer is a common electrode, and the second electrode layer is a pixel electrode.
Optionally, the projection of the spacer on the array substrate is located in the projection of the thin film transistor on the array substrate.
A display panel, comprising the array substrate according to any one of the above technical solutions, further comprising: the color film substrate is arranged in a box-to-box mode with the array substrate, and the spacers are arranged between the array substrate and the color film substrate, and one end, close to the array substrate, of each spacer is inserted into the corresponding concave portion.
A display device comprises the display panel in the technical scheme.
A preparation method of an array substrate comprises the following steps:
preparing thin film transistors distributed in an array on a substrate;
forming an organic insulating layer on the thin film transistor;
forming a first electrode layer on the organic insulating layer;
forming a first insulating layer on the first electrode layer;
at least one of the organic insulating layer, the first electrode layer and the first insulating layer is provided with a slot corresponding to the position of the spacer, so that a concave part is formed on the surface of the array substrate corresponding to the position of the spacer.
Drawings
Fig. 1 is a schematic partial structural view of an array substrate according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of a display panel along the direction A-A in FIG. 1 according to an embodiment of the present invention;
fig. 3 is a schematic cross-sectional view of an array substrate along the direction a-a in fig. 1 according to an embodiment of the invention;
fig. 4 is a schematic cross-sectional view of an array substrate along the direction a-a in fig. 1 according to another embodiment of the present invention;
fig. 5 is a schematic cross-sectional view of an array substrate according to an embodiment of the invention;
FIG. 6 is a schematic view illustrating a process of preparing a pattern on the array substrate of FIG. 5 by using a patterning process;
fig. 7 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1 to 5, an embodiment of the present invention provides an array substrate, including thin film transistors 1 distributed in an array, and an organic insulating layer 2, a first electrode layer 3, and a first insulating layer 4 sequentially stacked on the thin film transistors 1, wherein:
at least one of the organic insulating layer 2, the first electrode layer 3 and the first insulating layer 4 is provided with a slot corresponding to the position of the spacer 7, so that a recess 100 is formed on the surface of the array substrate at the position corresponding to the spacer 7.
Above-mentioned array substrate surface is formed with depressed part 100 on the position that corresponds with shock insulator 7, and when to the box, the top of shock insulator 7 can be inserted in this depressed part 100 to by spacing, difficult production slides, and then can avoid shock insulator 7 fish tail display area to join in marriage the membrane, promote product yield and stability. Compared with the array substrate preparation process in the prior art, the process flow is not increased in the array substrate preparation process, the preparation process is not changed, and the array substrate can be prepared only by correspondingly changing the mask patterns of at least one of the organic insulating layer 2, the first electrode layer 3 and the first insulating layer 4, so that the method has a great cost advantage.
Specifically, in the above description, the position of the surface of the array substrate corresponding to the spacer 7 specifically refers to the projection area of the spacer 7 on the surface of the array substrate; similarly, the positions of the organic insulating layer 2, the first electrode layer 3 and the first insulating layer 4 corresponding to the spacer 7 refer to the projection areas of the spacer 7 on the above layers. In addition, the organic insulating layer 2 covers the thin film transistor 1, and can cover and fill the channel region and the step region formed by the thin film transistor 1, which can be called as a 'flat layer'; the first insulating layer 4 may be only one or more inorganic insulating layers (PVX), or may be a multilayer alternating structure of inorganic insulating layers and organic insulating layers, and the material and the number of structural layers are not limited in the embodiment of the present application.
Next, an example of a method of forming the array substrate front surface depression 100 will be described.
In a specific embodiment, as shown in fig. 3, the first insulating layer 4 is provided with first via holes corresponding to the positions of the spacers 7, thereby resulting in the formation of the depressions 100 on the surface of the finally formed array substrate.
In a specific embodiment, as shown in fig. 4, the first insulating layer 4 and the first electrode layer 3 are provided with via holes corresponding to the positions of the spacers 7, so that the surface of the finally formed array substrate is formed with a recess 100.
In a specific embodiment, as shown in fig. 5, the organic insulating layer 2 is provided with a groove 101 corresponding to the position of the spacer 7, thereby resulting in a recess 100 formed on the surface of the finally formed array substrate. Because the organic insulating layer 2 has larger thickness, the shallow groove 101 is formed on the organic insulating layer to limit the spacer 7, so that the situation that the spacer 7 is inserted into the array substrate deeply to influence the thickness of the cell can be avoided.
In a specific embodiment, both the first insulating layer 4 and/or the first electrode layer 3 are provided with vias and the organic insulating layer 2 is provided with grooves 101, and the recess 100 on the surface of the array substrate is formed by the vias and the grooves 101.
In practical applications, which embodiment is specifically selected can be determined according to the depth requirement of the recess 100 and the convenience requirement of mask processing and substrate preparation processes.
In a specific embodiment, as shown in fig. 2, a second electrode layer 5 stacked on the first insulating layer 4 may be further disposed on the array substrate. Specifically, the second electrode layer 5 may be provided with a via hole corresponding to the position of the spacer 7, that is, the recess 100 may be formed by providing a via hole on the second electrode layer 5. Alternatively, the second electrode layer 5 may also directly cover the area of the recess 100 to serve as a protection layer in the hole, and at this time, the recess 100 on the surface of the array substrate is formed on the surface of the second electrode layer 5, as is the case with the structure shown in fig. 2.
Specifically, as shown in fig. 2, when the second electrode layer 5 covers the area of the recess 100, the vias of the first insulating layer 4 and the first electrode layer 3 are trepanned, i.e., the via of the first insulating layer 4 is nested in the via of the first electrode layer 3. The trepanning design can avoid forming electric connection between the first electrode layer 3 and the second electrode layer 5, and avoid short circuit.
In a specific embodiment, the first electrode layer 3 may be a common electrode, and the second electrode layer 5 may be a pixel electrode.
Of course, the first electrode layer 3 may be a pixel electrode, and the second electrode layer 5 may be a common electrode; at this time, the second electrode layer 5 may also be disposed on the color filter substrate 6.
As shown in fig. 1 to 4, in a specific embodiment, the thin film transistors 1 are disposed at the crossing positions of the gate lines 8 and the data lines 9, and each thin film transistor 1 includes a gate electrode 11, an active layer 12, a source electrode 13, a drain electrode 14, and other functional structures, and further includes a gate insulating layer 15, a passivation layer 16, and other insulating layers between the functional structural layers. Specifically, in order to increase the aperture ratio, the position of the spacer 7 corresponds to the position of the thin film transistor 1, that is, the projection of the spacer 7 on the substrate 10 is located within the projection of the thin film transistor 1 on the substrate 10, and accordingly, the recess 100 is also formed on the thin film transistor 1, that is, within the projection range of the thin film transistor 1.
In an alternative embodiment, the inner surface of the recess 100 is an arcuate surface. Thus, the contact area between the recessed portion 100 and the spacer 7 is large, and the friction is large, so that the spacer 7 is less likely to slide. Specifically, as shown in fig. 5, a groove 101 having an arc-shaped inner surface may be formed in the organic insulating layer 2, and then, after deposition of each layer on the organic insulating layer 2, the inner surface of the final recess 100 may be an arc-shaped surface.
In addition, as shown in fig. 1, an embodiment of the present invention further provides a display panel, including the array substrate of any one of the embodiments; further, the display panel further includes: the color film substrate 6 is arranged in a box-to-box mode with the array substrate, and the spacers 7 are arranged between the array substrate and the color film substrate 6, and one end, close to the array substrate, of each spacer 7 is inserted into the corresponding concave portion 100. One end of the spacer 7 close to the array substrate is inserted into the concave part 100, so that the spacer is limited and is not easy to slide, and light leakage caused by scratching of the alignment film in the display area by the spacer 7 can be avoided.
The embodiment of the invention also provides a display device which comprises the display panel in the embodiment.
Furthermore, based on the array substrate in the above embodiments, an embodiment of the present invention further provides a method for manufacturing an array substrate, as shown in fig. 7, the method includes the following steps:
at least one of the organic insulating layer, the first electrode layer and the first insulating layer is provided with a slot corresponding to the position of the spacer, so that a concave part is formed on the surface of the array substrate corresponding to the position of the spacer.
As shown in fig. 2-5, the array substrate formed by the above-mentioned preparation method has a recessed portion 100 formed on the surface thereof at a position corresponding to the spacer, and when the cell is aligned, the top of the spacer 7 can be inserted into the recessed portion 100, so that the cell is limited and does not easily slide, thereby preventing the spacer 7 from scratching the alignment film in the display region and improving the yield and stability of the product. Compared with the array substrate preparation process in the prior art, the process flow is not increased in the array substrate preparation process, the preparation process is not changed, and the array substrate can be prepared only by correspondingly changing the mask pattern of at least one of the organic insulating layer, the first electrode layer and the first insulating layer, so that the method has a great cost advantage.
Optionally, step 101 specifically includes the steps of preparing a gate electrode, a gate insulating layer, an active layer, a source electrode, a drain electrode, a passivation layer, and the like.
In a specific embodiment, the recess finally formed on the surface of the array substrate may be formed by a groove formed on the organic insulating layer. At this time, the specific process of step 102 includes: and preparing an organic layer on the thin film transistor, and forming a groove on the position of the organic layer corresponding to the spacer by a composition process.
Alternatively, as shown in fig. 6, a half-tone mask plate 111 may be used in the patterning process, so that a via hole 102 and a cambered groove 101 are formed in the organic insulating layer, specifically, the via hole 102 is formed in a portion corresponding to the full light-transmitting region C of the mask plate 111 for connection between signal layers, the groove 101 is formed in a portion corresponding to the semi-light-transmitting region B, the size of the groove 101 depends on the size of the semi-light-transmitting region B of the mask plate 111, and the depth depends on the ultraviolet light (UV light) transmittance of the semi-light-transmitting region B. And finally, the cambered concave part can be formed on the surface of the array substrate, the contact area of the cambered concave part and the spacer is large, the friction is large, and therefore the spacer is not easy to slide.
Alternatively, as shown in fig. 3, the recess 100 formed on the surface of the array substrate may be formed by a via hole formed on the first insulating layer 4. At this time, the specific process of step 103 includes: and preparing an electrode layer on the organic insulating layer, and forming a via hole at a position of the electrode layer corresponding to the spacer by a composition process.
Alternatively, as shown in fig. 4, the recess 100 formed on the surface of the array substrate may be formed by the first insulating layer 4 and the via hole formed in the first electrode layer 3. In this case, on the basis of the step 103, the specific flow of the step 104 may include: and preparing an inorganic insulating layer on the first electrode layer, and forming a via hole in a position of the inorganic insulating layer corresponding to the spacer by a composition process.
Specifically, the patterning process in the embodiment of the present invention is a process for forming a structural pattern by one or more steps of process steps such as photoresist coating, exposure, etching, and developing.
In a specific embodiment, the method for manufacturing an array substrate according to an embodiment of the present invention further includes the following steps: a second electrode layer is prepared on the first insulating layer.
Optionally, when the second electrode layer is patterned by the patterning process, a via hole pattern corresponding to the position of the spacer may be formed at the same time, that is, a recess may also be formed by providing a via hole on the second electrode layer; alternatively, as shown in fig. 2, the second electrode layer 5 may directly cover the original recess region, that is, the pattern of the second electrode layer 2 is not changed.
In a specific embodiment, as shown in fig. 2, when the second electrode layer 5 covers the recess region, the via holes of the first insulating layer 4 and the first electrode layer 3 are trepanned holes. The trepanning design can avoid forming electric connection between the first electrode layer 3 and the second electrode layer 5, and avoid short circuit.
In a specific embodiment, as shown in fig. 2, the first electrode layer 3 is a common electrode, and the second electrode layer 5 is a pixel electrode. Alternatively, the first electrode layer 3 may be a pixel electrode, and the second electrode layer 5 may be a common electrode; at this time, the second electrode layer 5 may also be disposed on the color filter substrate 6.
It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (6)
1. The array substrate comprises thin film transistors distributed in an array manner, and an organic insulating layer, a first electrode layer and a first insulating layer which are sequentially stacked on the thin film transistors, and is characterized in that:
at least one of the organic insulating layer, the first electrode layer and the first insulating layer is provided with a slot corresponding to the position of the spacer, so that a concave part is formed on the surface of the array substrate at the position corresponding to the spacer;
the organic insulating layer is provided with a slotted hole corresponding to the position of the shock insulator, and the slotted hole is a groove;
the array substrate is also provided with a second electrode layer laminated on the first insulating layer; a through hole corresponding to the position of the spacer is formed in the second electrode layer;
the inner surface of the groove is an arc-shaped surface;
a slotted hole corresponding to the position of the shock insulator is formed in the first insulating layer and is a through hole;
or, the first insulating layer and the first electrode layer are both provided with a slotted hole corresponding to the position of the spacer, and the slotted hole is a through hole; when the second electrode layer covers the sunken part region, the through holes of the first insulating layer and the first electrode layer are trepanning holes.
2. The array substrate of claim 1, wherein the first electrode layer is a common electrode and the second electrode layer is a pixel electrode.
3. The array substrate of claim 1, wherein a projection of the spacer on the array substrate is within a projection of the thin film transistor on the array substrate.
4. A display panel comprising the array substrate according to any one of claims 1 to 3, further comprising: the color film substrate is arranged in a box-to-box mode with the array substrate, and the spacers are arranged between the array substrate and the color film substrate, and one end, close to the array substrate, of each spacer is inserted into the corresponding concave portion.
5. A display device characterized by comprising the display panel according to claim 4.
6. The preparation method of the array substrate is characterized by comprising the following steps:
preparing thin film transistors distributed in an array on a substrate;
forming an organic insulating layer on the thin film transistor;
forming a first electrode layer on the organic insulating layer;
forming a first insulating layer on the first electrode layer;
forming a second electrode layer on the first insulating layer;
at least one of the organic insulating layer, the first electrode layer and the first insulating layer is provided with a slot corresponding to the position of the spacer, so that a concave part is formed on the surface of the array substrate at the position corresponding to the spacer;
the organic insulating layer is provided with a slotted hole corresponding to the position of the shock insulator, and the slotted hole is a groove;
a through hole corresponding to the position of the spacer is formed in the second electrode layer;
the inner surface of the groove is an arc-shaped surface.
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| CN202720426U (en) * | 2012-08-10 | 2013-02-06 | 京东方科技集团股份有限公司 | Liquid crystal display (LCD) substrate and LCD device |
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| CN104834137B (en) * | 2015-05-07 | 2018-02-16 | 合肥京东方光电科技有限公司 | Array base palte, color membrane substrates, display panel and display device |
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