CN109509498B - Memristor read-write circuit applied to digital recognition - Google Patents
Memristor read-write circuit applied to digital recognition Download PDFInfo
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- CN109509498B CN109509498B CN201811358268.7A CN201811358268A CN109509498B CN 109509498 B CN109509498 B CN 109509498B CN 201811358268 A CN201811358268 A CN 201811358268A CN 109509498 B CN109509498 B CN 109509498B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/60—Memory management
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- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
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- G11C13/0069—Writing or programming circuits or methods
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Abstract
The memristor read-write circuit applied to digital identification comprises a first digital circuit, a digital-to-analog converter, a memristor unit, a current-voltage converter, an analog-to-digital converter and a second digital circuit which are sequentially coupled. By means of the scheme, the memristor information can be read.
Description
Technical Field
The invention belongs to the technical field of digital identification, and particularly relates to a memristor read-write circuit applied to digital identification.
Background
With the development of the artificial intelligence industry, the application of the image recognition algorithm is more and more extensive. Most developers can select a mature SDK suite, and a machine learning algorithm is operated by means of a CPU and a GPU so as to realize an image recognition function. However, in the field of terminal devices, although CPUs and GPUs have excellent data processing capabilities, they have not been fully popularized due to limitations in cost, power consumption, size, and the like.
As early as 1971, professor zeisure speculates from the basic theory of circuitry that a basic circuit element, a memristor, characterizing the relationship between charge and magnetic flux should also exist. However, until 2008, HP laboratory succeeded in manufacturing memristor objects, which confirmed the guess of professor cai, and after two years, researchers at the university of rice in usa pointed out in journal of nano promissory of the american society of chemistry that they have successfully manufactured memristors with widths of only 5 nm, while the most advanced transistor process has not broken through the gate length of 7 nm. As the memristor has the characteristics of small volume, high integration level, low power consumption and the like, more memristors are easier to package on one chip, and the memristor can possibly replace a transistor so as to continue writing the Morse law.
The existing memristor read-write circuit is generally directed at the switching characteristic of the memristor, and the memristor is equivalent to a switching resistance at this time. For example, chinese patent publication No. 201710142907.5 discloses a "read/write circuit for a four-valued memristor" which completes information reading through a voltage comparator and a decoder. However, since the resistance states of some memristors with multi-level storage characteristics continuously change and have no fixed resistance state, information cannot be read by using the circuit.
Disclosure of Invention
The invention solves the technical problem of how to read memristor information.
In order to achieve the above object, the present invention provides a memristor read-write circuit applied to digital identification, which includes a first digital circuit, a digital-to-analog converter, a memristor unit, a current-to-voltage converter, an analog-to-digital converter, and a second digital circuit, which are coupled in sequence;
the first digital circuit is suitable for carrying out binarization processing on the acquired image data to obtain a digital signal carrying binarized image data and sending the digital signal to the digital-to-analog converter;
the digital-to-analog converter is suitable for reducing the voltage of the received digital signal, converting the digital signal into a corresponding pulse signal and outputting the pulse signal to the memristor;
the memristor unit is suitable for converting a received pulse signal into a corresponding current signal and sending the current signal to the current-voltage conversion circuit;
the current-voltage conversion circuit is suitable for converting a current signal output by the memristor into a corresponding voltage signal and outputting the voltage signal to the analog-to-digital converter;
the analog-to-digital converter is suitable for converting the voltage signal of the voltage-to-current conversion circuit side into a corresponding digital signal and sending the digital signal to the second digital circuit;
and the second digital circuit is suitable for matching the digital signal sent by the analog-to-digital converter with the digital signal in the database to obtain a corresponding image identification result.
Optionally, the first digital circuit employs an FPGA blackgold AX150 development board.
Optionally, the digital-to-analog converter includes a digital-to-analog conversion module and an operational amplifier module;
the digital-to-analog conversion module comprises a digital-to-analog conversion chip, a first resistor R1, a second resistor R2 and a third resistor R3; the operational amplifier module comprises a first operational amplifier and a second operational amplifier;
the digital-to-analog conversion circuit comprises a digital-to-analog conversion chip, a first resistor, a second resistor, a resistor and a resistor, wherein 8 input ends of the digital-to-analog conversion chip are respectively coupled with eight pins of an 8-pin header, a CS end, a WR end, a GND end, a WR2 end, an XFER end and an Iout2 end of the digital-to-analog conversion chip are all grounded, a VCC end, an ILE end and a Vref end of the digital-to-analog conversion chip are respectively coupled with a +5V direct-current power supply and are used as input ends of the digital-to-analog converter to be coupled with an output end of the first digital circuit, and the Vref end of the digital-to-analog conversion chip is coupled with a first end of the first resistor;
an inverting input end of a first operational amplifier of the operational amplifier module is coupled to a first end of the first resistor, a VCC end of the digital-to-analog conversion module and an ILE end, and an output end of the first operational amplifier is coupled to a first end of the second resistor and serves as an output end of the digital-to-analog converter; the positive input end of the first operational amplifier is coupled with a +5V direct-current power supply; the inverting input end of the second operational amplifier is coupled with the Iout1 end of the digital-to-analog conversion module, and the positive input end of the second operational amplifier and the Iout2 end of the digital-to-analog conversion module are both coupled with a +5V direct-current power supply; the output end of the second operational amplifier is coupled with the Rfb end of the digital-to-analog conversion module and the first end of the third resistor; the second end of the first resistor is coupled with the second end of the second resistor and the second end of the third resistor.
Optionally, the digital-to-analog converter is adapted to step down and convert the received digital signal into a corresponding pulse signal by using the following formula:
wherein, VoutIndicating the converted pulse signal, VinRepresenting the received digital signal.
Optionally, the memristor cells comprise four-way memristors;
the input ports of the four memristors are respectively coupled with the output ends of the four digital-to-analog converters which are connected in parallel, and the output ends of the four memristors are mutually coupled to serve as the total output port of the memristors.
Optionally, the voltage-to-current converter comprises a fifth operational amplifier and a sixth operational amplifier;
the V-end of the fifth operational amplifier is coupled with the third pin of the first four-pin header, the first ends of the first capacitor and the second capacitor, the third pin of the first four-pin header is also coupled with a-5V external direct current power supply, and the second ends of the first capacitor and the second capacitor are both grounded; the-INA end of the fifth operational amplifier is coupled with the fourth pin of the first four-pin header, the first end of a fifth capacitor and the first end of a fourth resistor respectively, the fourth pin of the first four-pin header is further coupled with the output end of the memristor unit, the second end of the fifth capacitor is coupled with the OUT _ A end of the fifth operational amplifier, the first end of a fifth resistor and the first end of a sixth resistor respectively, the second end of the fourth resistor is coupled with the second end of the fifth resistor and the first end of a seventh resistor respectively, and the second end of the seventh resistor is grounded; the + INA end of the fifth operational amplifier is grounded;
the OUT _ B end of the sixth operational amplifier is coupled to the second end of the sixth resistor; the V + end of the sixth operational amplifier is coupled with the second pin of the first four-pin header, the first end of the third capacitor and the first end of the fourth capacitor respectively; the second pins of the first four-pin header are also respectively coupled with a +5V external direct current power supply, and the second ends of the third capacitor and the fourth capacitor are both grounded; the + INB terminals of the sixth operational amplifier are all grounded, the-INB terminal of the sixth operational amplifier is coupled with the first terminal of the sliding resistor, and the second terminal of the sliding resistor is also coupled with the OUT _ B terminal of the sixth operational amplifier to serve as an output port of the current-voltage converter.
Optionally, the analog-to-digital converter is composed of a voltage reference circuit and an analog-to-digital conversion circuit;
the voltage reference circuit comprises a first diode, an eighth resistor, a ninth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a three-end adjustable shunt reference voltage source, a sixth capacitor and a seventh capacitor; a positive terminal of the first diode is coupled to a VCC terminal of the voltage reference circuit, a negative terminal of the first diode is coupled to a first terminal of an eighth resistor, a second terminal of the eighth resistor is coupled to a first terminal of a sixth capacitor and a first terminal of a ninth resistor, a second terminal of the sixth capacitor is grounded, a second terminal of the ninth resistor is coupled to a first terminal of an eleventh resistor, a second terminal of the eleventh resistor is coupled to a reference electrode of a three-terminal adjustable shunt reference voltage source and a first terminal of a twelfth resistor respectively, a cathode of the three-terminal adjustable shunt reference voltage source is coupled to a first terminal of a thirteenth resistor, a second terminal of the thirteenth resistor is coupled to a first terminal of a seventh capacitor and is coupled to the analog-to-digital conversion circuit as a reference voltage output port of the voltage reference circuit, and an anode of the three-terminal adjustable shunt reference voltage source and a second terminal of the twelfth resistor R12 are both grounded;
the analog-to-digital conversion circuit comprises an analog-to-digital conversion chip, a fourteenth resistor, a fifteenth resistor, a sixteen resistor R5, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, an eighth capacitor and a ninth capacitor; the VDD end of the analog-to-digital conversion chip is coupled with the output end of the voltage reference circuit, the grounding end of the analog-to-digital conversion chip is grounded, a DOUT end, a DIN end and an ADDR end are respectively coupled with the data end, the clock end and the address selection end of the second digital circuit, the ADDR end is further coupled with a first end of a fourteenth resistor, and a second end of the fourteenth resistor is coupled with the ADDR end; the DIN terminal of the analog-to-digital conversion chip is also coupled with the first terminal of a fifteenth resistor, and the second terminal of the fifteenth resistor is coupled with the DOUT terminal; the DOUT end of the analog-to-digital conversion chip is also coupled with one end of a sixteenth resistor, and the second end of the sixteenth resistor is coupled with the DIN end; the RDY end of the analog-to-digital conversion chip is grounded; the AIN0 terminal of the analog-to-digital conversion chip is coupled with the first terminal of the seventeenth resistor, and the AIN0 terminal is further coupled with the second terminal of the seventeenth resistor to serve as a channel 0; the AIN1 end of the analog-to-digital conversion chip is coupled with the first end of an eighteenth resistor, and the AIN1 end is further coupled with the second end of the eighteenth resistor to serve as a channel 1; the AIN2 terminal of the analog-to-digital conversion chip is coupled with the first terminal of a nineteenth resistor, and the AIN0 terminal is further coupled with the second terminal of the nineteenth resistor to serve as a channel 2; the AIN2 terminal of the analog-to-digital conversion chip is coupled with the first terminal of the twentieth resistor, and the AIN2 terminal is further coupled with the second terminal of the twentieth resistor to serve as a channel 3; the first end of the nineteenth resistor is further coupled to the first end of an eighth capacitor, and the second end of the eighth capacitor is grounded; the first end of the twentieth resistor is further coupled to the first end of the ninth capacitor, and the second end of the ninth capacitor is grounded.
Compared with the prior art, the invention has the beneficial effects that:
in the scheme, the collected image data is binarized by the first digital circuit to obtain a digital signal carrying binarized image data and is sent to the digital-to-analog converter, the digital-to-analog converter is used for reducing the voltage of the received digital signal and converting the digital signal into a corresponding pulse signal to be output to the memristor, the memristor unit is used for converting the received pulse signal into a corresponding current signal and sending the current signal to the current-voltage conversion circuit, the current-voltage conversion circuit is used for converting the current signal output by the memristor into a corresponding voltage signal and outputting the voltage signal to the analog-to-digital converter, the analog-to-digital converter is used for converting the voltage signal in the voltage-current conversion circuit into a corresponding digital signal and sending the digital signal to the second digital circuit, and the second digital circuit is used for matching the digital signal sent by the analog-to-digital converter with the digital, and obtaining a corresponding image recognition result, and reading memristor information.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.
FIG. 1 is a schematic diagram showing a framework structure of a memristor read-write circuit applied to digital identification in an embodiment of the present invention;
fig. 2 shows a schematic structural diagram of a digital-to-analog converter in an embodiment of the present invention;
fig. 3 is a circuit diagram illustrating the operation of the digital-to-analog conversion module in an embodiment of the present invention;
FIG. 4 illustrates a structural schematic of the memristor cell in an embodiment of the present disclosure;
fig. 5 shows a circuit diagram of a voltage-to-current converter in an embodiment of the invention;
FIG. 6 shows a circuit diagram of a voltage reference circuit in an embodiment of the invention;
fig. 7 shows a schematic structural diagram of an analog-to-digital conversion circuit in the embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. The directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship between the components, the movement, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indication is changed accordingly.
As described in the background art, the gesture recognition technology based on computer vision in the prior art is affected by conditions such as skin color, illumination, posture and the like, and has the problems of inaccurate gesture recognition result and high cost.
According to the technical scheme, the acquired image data is subjected to binarization processing through the first digital circuit, a digital signal carrying binarized image data is obtained and sent to the digital-to-analog converter, the digital-to-analog converter is used for carrying out voltage reduction on the received digital signal and converting the digital signal into a corresponding pulse signal to be output to the memristor, the memristor unit is used for converting the received pulse signal into a corresponding current signal and sending the current signal to the current-voltage conversion circuit, the current-voltage conversion circuit is used for converting the current signal output by the memristor into a corresponding voltage signal and outputting the voltage signal to the analog-to-digital converter, the analog-to-digital converter is used for converting the voltage signal in the voltage-current conversion circuit into a corresponding digital signal and sending the digital signal to the second digital circuit, and the second digital circuit is used for matching the digital signal sent by the analog-to-digital converter with the digital signal in a database, the corresponding image recognition result is obtained, and the reading of the memristor information can be realized
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 shows a schematic diagram of a framework structure of a memristor read-write circuit applied to digital recognition in an embodiment of the present invention.
Referring to fig. 1, the memristor read-write circuit applied to digital identification in the embodiment of the present invention includes a first digital circuit 11, a digital-to-analog converter 12, a memristor unit 13, a current-to-voltage converter 14, an analog-to-digital converter 15, and a second digital circuit 16, which are coupled in sequence. Wherein:
the first digital circuit 11 performs binarization processing on the acquired image data to obtain a digital signal carrying binarized image data and sends the digital signal to the digital-to-analog converter; the digital-to-analog converter 12 steps down the received digital signal and converts the digital signal into a corresponding pulse signal, and outputs the pulse signal to the memristor unit 13; the memristor unit 13 converts the received pulse signal into a corresponding current signal and sends the current signal to the current-voltage conversion circuit 14; the current-voltage conversion circuit 14 converts the current signal output by the memristor unit into a corresponding voltage signal and outputs the voltage signal to the analog-to-digital converter 15; the analog-to-digital converter 15 converts the voltage signal of the voltage-to-current conversion circuit side into a corresponding digital signal and sends the digital signal to the second digital circuit 16; the second digital circuit 16 matches the digital signal sent by the analog-to-digital converter with the digital signal in the database to obtain a corresponding image recognition result.
In an embodiment of the present invention, the first digital circuit 11 employs an FPGA blackgold AX150 development board.
In an embodiment of the present invention, the digital-to-analog converter 12 steps down the received digital signal and converts the digital signal into a corresponding pulse signal by using the following formula:
wherein, VoutIndicating the converted pulse signal, VinRepresenting the received digital signal.
Referring to fig. 2, in an embodiment of the present invention, the digital-to-analog converter includes a digital-to-analog conversion module 121 and an operational amplifier module 122 coupled to each other.
Referring to fig. 3, the digital-to-analog conversion module includes a digital-to-analog conversion chip 123, a first resistor R1, a second resistor R2, and a third resistor R3; the operational amplifier module includes a first operational amplifier 124 and a second operational amplifier 125. The 8 input ends of the digital-to-analog conversion chip 123 are coupled with eight pins of the 8-pin header P1, the CS end, WR end, GND end, WR2 end, XFER end and Iout2 end of the digital-to-analog conversion chip 123 are all grounded, the VCC end, ILE end, Vref end of the digital-to-analog conversion chip 123 are coupled with +5V dc power supply, and serve as the input end of the digital-to-analog converter is coupled with the output end of the first digital circuit, and the Vref end of the digital-to-analog conversion chip 123 is coupled with the first end of the first resistor R1. An inverting input terminal of the first operational amplifier 124 is coupled to the first terminal of the first resistor R1, the VCC terminal of the digital-to-analog conversion module 123, and the ILE terminal, and an Output terminal of the first operational amplifier 124 is coupled to the first terminal of the second resistor R2 and serves as an Output1 of the digital-to-analog converter; the positive input terminal of the first operational amplifier 124 is coupled to a +5V dc power supply; the inverting input terminal of the second operational amplifier 125 is coupled to the Iout1 terminal of the digital-to-analog conversion module, and the positive input terminal of the second operational amplifier 125 and the Iout2 terminal of the digital-to-analog conversion module are both coupled to a +5V dc power supply; an output terminal of the second operational amplifier 125 is coupled to an Rfb terminal of the digital-to-analog conversion module and a first terminal of the third resistor R3; the second terminal of the first resistor R1 is coupled to the second terminal of the second resistor R2 and the second terminal of the third resistor R3.
The working principle of the digital-to-analog conversion chip 123 is as follows:
GND terminal: and the wire grounding end is used as a zero point reference point of the circuit.
VCC: the power supply end is externally connected with +5V direct current input voltage in the circuit.
And a CS terminal: the chip selection end is effective in low level and is grounded in the circuit, namely the digital-to-analog conversion chip is selected; WR end: the write signal terminal 1, the low level is effective, grounded in this circuit; an ILE end: the input register allows, high is active, and is connected to +5V in the circuit.
When the CS terminal, the WR terminal, and the ILE terminal are all valid, the "input register" in the digital-to-analog conversion chip 123 may be successfully written with a signal.
XFER end: the transfer control signal end is active at low level and grounded in the circuit;
WR2 end: the write signal terminal 2, active low, is grounded in this circuit;
when the XFER terminal and the WR2 terminal are both active, the DAC register in the digital-to-analog converter can be successfully written with signals.
A Vref terminal: a reference voltage terminal. The DAC0832 digital-to-analog conversion chip is an 8-bit digital-to-analog conversion chip, 8 bits are 8-bit binary numbers, the highest bit can reach 8' 1111_1111 (decimal is 255), Vref in the circuit is terminated with +5V, namely +5V is used as the reference voltage of the circuit, namely the distinguishable minimum voltage of the circuit is 5/255(1/51) V.
Iout 1: a current signal output terminal 1; iout 2: a current signal output terminal 2.
The sum (Iout1+ Iout2) of the output currents of the two current output ends Iout1 and Iout2 is a constant, in this experiment, the terminal Iout2 is grounded, and the current signal output by the terminal Iout1 is the conversion result of the DAC chip.
Rfb: the feedback signal input end is internally provided with a feedback resistor, the feedback signal input end is directly connected with the Iout1 end from the inside of a chip in the circuit, and the other end of the feedback signal input end is connected with the output end of the second operational amplifier to form a feedback loop so as to realize the current-voltage conversion function.
DI 0-DI 7: the signal input ends 0-7 are connected with an external digital circuit in the circuit, D0-D7 respectively correspond to 8 bits from low to high of 8-bit input signals, and the size of an output signal is determined according to the product of 8-bit binary numbers represented by the input signals and the minimum voltage (5/255) distinguishable by the circuit.
The operational principle of the operational amplifier is as follows: in the circuit, only a first operational amplifier and a second operational amplifier of a TL084 operational amplifier chip are used, wherein the second operational amplifier is externally connected with a feedback resistor (the resistor is an Rfb end built-in resistor) and used as a current-voltage converter, and the resistor R3 plays a role of isolating impedance at an output port of the second operational amplifier.
The first operational amplifier of the TL084 constitutes an adder providing a dc bias to the current-to-voltage converter constituted by the second operational amplifier.
In an embodiment of the present invention, the digital-to-analog conversion chip 123 is a DAC0832 chip, and the operational amplifier module employs a TL084 chip.
Referring to FIG. 4, the memristor cell 14 includes four- way memristors 141, 142, 143, and 144. Input ports of the four- way memristors 141, 142, 143 and 144 are respectively coupled with Output ends of four-way digital-to-analog converters connected in parallel, and Output ends of the four- way memristors 141, 142, 143 and 144 are mutually coupled to serve as a total Output port Output2 of the memristor unit.
Referring to fig. 5, in an embodiment of the present invention, the voltage-to-current converter includes a fifth operational amplifier 141 and a sixth operational amplifier 142. The V-terminal of the fifth operational amplifier 141 is coupled to the third pin 3 of the first four-pin bank P41, the first terminals of the first capacitor C1 and the second capacitor C2, the third pin 3 of the first four-pin bank is further coupled to a-5V external dc power supply, and the second terminals of the first capacitor C1 and the second capacitor C2 are both grounded; the-INA terminal of the fifth operational amplifier 141 is coupled to the fourth pin 4 of the first four-pin bank, the first terminal of the fifth capacitor C5, and the first terminal of the fourth resistor R4, respectively, the fourth pin 4 of the first four-pin bank P41 is further coupled to the output terminal of the memristor cell, the second terminal of the fifth capacitor C5 is coupled to the OUT _ a terminal of the fifth operational amplifier 141, the first terminal of the fifth resistor R5, and the first terminal of the sixth resistor R6, respectively, the second terminal of the fourth resistor R4 is coupled to the second terminal of the fifth resistor R5 and the first terminal of the seventh resistor R7, respectively, and the second terminal of the seventh resistor R7 is grounded; the + INA terminal of the fifth operational amplifier 141 is grounded; the terminal OUT _ B of the sixth operational amplifier 142 is coupled to the second terminal of the sixth resistor R6; the V + terminal of the sixth operational amplifier 142 is coupled to the first terminals of the second pin 2, the third capacitor C3 and the fourth capacitor C4 of the first four-pin P41, respectively; the second pin 2 of the first four-pin header P41 is further coupled to a +5V external dc power supply, and the second terminals of the third capacitor C3 and the fourth capacitor C4 are both grounded; the + INB terminals of the sixth operational amplifier 162 are all connected to the GND, the-INB terminal of the sixth operational amplifier 162 is coupled to a first terminal of a sliding resistor R, and a second terminal of the sliding resistor R is further coupled to the OUT _ B terminal of the sixth operational amplifier 162 as an Output port Output3 of the current-voltage converter.
The working principle of the current-voltage converter is as follows: in the circuit, R4, R5 and R7 form Y-shaped connection, and can be equivalent to delta-shaped connection formed by an INA end, a GND end and an output end of a fifth operational amplifier 141 in a TLV9062 operational amplifier chip, wherein the resistance connected with the INA end and an OUT _ A end in an equivalent circuit is used as a feedback resistance, the principle is that the ratio of output voltage to the feedback resistance is equal to input current, and the magnitude of the output voltage can be calculated according to the magnitude of the output current and the feedback resistance; the capacitor C5 can reduce the amplification effect of the circuit on high-frequency noise so as to achieve the purpose of noise reduction; c1, C2, C3 and C4 are coupling resistors, so that power supply noise is reduced; the resistor R6, the sliding rheostat and the sixth operational amplifier 142 in the TLV9062 operational amplifier chip form an amplifier circuit, the principle is that the ratio of an input signal (i.e., a current-voltage converter output signal) to the R6 is equal to the ratio of an output signal of the sixth operational amplifier 142 to the resistance value of the sliding rheostat, and the waveform of the output signal can be calculated according to the waveform of the input voltage signal and the resistance values of the resistor R6 and the sliding rheostat.
In an embodiment of the present invention, the analog-to-digital converter is composed of a voltage reference circuit and an analog-to-digital conversion circuit. Referring to fig. 6, the voltage reference circuit includes a first diode D1, an eighth resistor R8, a ninth resistor R9, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a three-terminal adjustable shunt reference voltage source TL431, a sixth capacitor C6, and a seventh capacitor C7; a positive terminal of the first diode D1 is coupled to a +5V power supply terminal of the analog-to-digital conversion circuit, a negative terminal of the first diode D1 is coupled to a first terminal of an eighth resistor R8, a second terminal of the eighth resistor R8 is coupled to a first terminal of a sixth capacitor C6 and a first terminal of a ninth resistor R9, a second terminal of the sixth capacitor C6 is grounded, a second terminal of the ninth resistor R9 is coupled to a first terminal of an eleventh resistor R11, a second terminal of the eleventh resistor R11 is coupled to a reference terminal of a three-terminal adjustable shunt reference voltage source TL431 and a first terminal of a twelfth resistor R12, respectively, a cathode of the three-terminal adjustable shunt reference voltage source TL43 is coupled to a first terminal of the thirteenth resistor R13, a second terminal of the thirteenth resistor R13 is coupled to a first terminal of the seventh capacitor C7, a reference voltage Output port Output4 serving as a voltage reference circuit is coupled to the analog-to-digital conversion circuit, and an anode of the three-terminal adjustable shunt reference voltage source TL431 and a second terminal of the twelfth resistor R12 are both grounded.
Voltage reference circuit theory of operation: d1: the light-emitting diode is used for displaying the working state of the module; r8 is 0 ohm resistance, which is designed for modifying circuit conveniently, and can change the on-off of the branch conveniently without making plate again; c6: a power supply bypass capacitance for decoupling; r9, R11, R12 and TL431 form a typical solution of TL431, and the output voltage (the right end point of R13 is used as an output port) satisfies Vout (R11+ R12) × 2.5/R12; r13 and C7 form a low-pass filter to filter the ripple to a certain extent.
Referring to fig. 7, the analog-to-digital conversion circuit includes an analog-to-digital conversion chip 153, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, an eighth capacitor C8, and a ninth capacitor C9; the VDD terminal of the analog-to-digital conversion chip 153 is coupled to the output terminal of the voltage reference circuit, the GND terminal is connected to ground, the DOUT terminal, the DIN terminal and the ADDR terminal of the analog-to-digital conversion chip 153 are coupled to the data terminal, the clock terminal and the address selection terminal of the second digital circuit, respectively, the ADDR terminal is further coupled to a first terminal of a fourteenth resistor R14, and a second terminal of the fourteenth resistor R14 is coupled to the ADDR terminal of the analog-to-digital conversion chip 153; the DIN terminal of the analog-to-digital conversion chip is also coupled with a first terminal of a fifteenth resistor R15, and a second terminal of the fifteenth resistor R15 is coupled with the DIN terminal of the analog-to-digital conversion chip 153; the terminal DOUT of the analog-to-digital conversion chip is further coupled to one terminal of a sixteenth resistor R16, and a second terminal of the sixteenth resistor R16 is coupled to the terminal DOUT of the analog-to-digital conversion chip 153; the RDY end of the analog-to-digital conversion chip is grounded; the AIN0 terminal of the analog-to-digital conversion chip is coupled with the first terminal of a seventeenth resistor R17, and the AIN0 terminal is further coupled with the second terminal of the seventeenth resistor R17 as a channel 0; the AIN1 terminal of the analog-to-digital conversion chip is coupled with the first terminal of an eighteenth resistor R18, and the AIN1 terminal is also coupled with the second terminal of the eighteenth resistor R18 to serve as a channel 1; the AIN2 terminal of the analog-to-digital conversion chip is coupled with the first terminal of a nineteenth resistor R19, and the AIN0 terminal is also coupled with the second terminal of the nineteenth resistor R19 as a channel 2; the AIN2 terminal of the analog-to-digital conversion chip is coupled with the first terminal of a twentieth resistor R20, and the AIN2 terminal is also coupled with the second terminal of the twentieth resistor R20 as a channel 3; the first end of the nineteenth resistor R19 is further coupled to a first end of an eighth capacitor C8, and a second end of the eighth capacitor C8 is grounded; the first terminal of the twentieth resistor R20 is further coupled to the first terminal of the ninth capacitor C9, and the second terminal of the ninth capacitor C9 is grounded.
The working principle of the analog-to-digital converter circuit is as follows: ADDR: 12C, from the address selection end, the low level is effective, and the resistor R14 plays a role in limiting current; SCLK: the serial clock end is used for external clock input and is externally connected with a digital circuit to provide a clock signal, and R15 is a current-limiting resistor; DOUT: the serial data end is used for serial data input and output, and R16 is a current-limiting resistor; VDD: a power supply terminal; AIN 0-AIN 4 are analog signal input ends and are used for inputting output signals of the memristor units. R17, R18, R19 and R20 are all current limiting resistors, and C8 and C9 filter high-frequency noise in input signals.
In summary, in the above-mentioned scheme of the embodiment of the present invention, the first digital circuit performs binarization processing on the acquired image data to obtain a digital signal carrying binarized image data, and sends the digital signal to the digital-to-analog converter, the digital-to-analog converter steps down the received digital signal and converts the digital signal into a corresponding pulse signal, and outputs the pulse signal to the memristor, the memristor unit converts the pulse signal into a corresponding current signal based on the received pulse signal and sends the current signal to the current-voltage conversion circuit, the current-voltage conversion circuit converts the current signal output by the memristor into a corresponding voltage signal and outputs the voltage signal to the analog-to-digital converter, the analog-to-digital converter converts the voltage signal at the voltage-current conversion circuit side into a corresponding digital signal and sends the digital signal to the second digital circuit, and the second digital circuit performs binarization processing on the digital signal sent by the analog-to-digital converter and the digital signal in the database And matching to obtain a corresponding image recognition result, so that the memristor information can be read.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the foregoing description only for the purpose of illustrating the principles of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the invention as defined by the appended claims, specification, and equivalents thereof.
Claims (6)
1. A memristor read-write circuit applied to digital identification is characterized by comprising a first digital circuit, a digital-to-analog converter, a memristor unit, a current-voltage converter, an analog-to-digital converter and a second digital circuit which are sequentially coupled;
the first digital circuit is suitable for carrying out binarization processing on the acquired image data to obtain a digital signal carrying binarized image data and sending the digital signal to the digital-to-analog converter; the digital-to-analog converter is suitable for reducing the voltage of the received digital signal, converting the digital signal into a corresponding pulse signal and outputting the pulse signal to the memristor unit; the digital-to-analog converter comprises a digital-to-analog conversion module and an operational amplifier module; the digital-to-analog conversion module comprises a digital-to-analog conversion chip, a first resistor, a second resistor and a third resistor; the operational amplifier module comprises a first operational amplifier and a second operational amplifier; the digital-to-analog conversion circuit comprises a digital-to-analog conversion chip, a first resistor, a second resistor, a resistor and a resistor, wherein 8 input ends of the digital-to-analog conversion chip are respectively coupled with eight pins of an 8-pin header, a CS end, a WR end, a GND end, a WR2 end, an XFER end and an Iout2 end of the digital-to-analog conversion chip are all grounded, a VCC end, an ILE end and a Vref end of the digital-to-analog conversion chip are respectively coupled with a +5V direct-current power supply and are used as input ends of the digital-to-analog converter to be coupled with an output end of the first digital circuit, and the Vref end of the digital-to-analog conversion chip is coupled with a first end of the first resistor; an inverting input end of a first operational amplifier of the operational amplifier module is coupled to a first end of the first resistor, a VCC end of the digital-to-analog conversion module and an ILE end, and an output end of the first operational amplifier is coupled to a first end of the second resistor and serves as an output end of the digital-to-analog converter; the positive input end of the first operational amplifier is coupled with a +5V direct-current power supply; the inverting input end of the second operational amplifier is coupled with the Iout1 end of the digital-to-analog conversion module, and the positive input end of the second operational amplifier and the Iout2 end of the digital-to-analog conversion module are both coupled with a +5V direct-current power supply; the output end of the second operational amplifier is coupled with the Rfb end of the digital-to-analog conversion module and the first end of the third resistor; the second end of the first resistor is coupled with the second end of the second resistor and the second end of the third resistor;
the memristor unit is suitable for converting a received pulse signal into a corresponding current signal and sending the current signal to the current-voltage conversion circuit;
the current-voltage conversion circuit is suitable for converting a current signal output by the memristor into a corresponding voltage signal and outputting the voltage signal to the analog-to-digital converter;
the analog-to-digital converter is suitable for converting the voltage signal of the voltage-to-current conversion circuit side into a corresponding digital signal and sending the digital signal to the second digital circuit;
and the second digital circuit is suitable for matching the digital signal sent by the analog-to-digital converter with the digital signal in the database to obtain a corresponding image identification result.
2. The memristor read-write circuit applied to digital identification, according to claim 1, wherein the first digital circuit adopts an FPGA black gold AX150 development board.
3. The memristor read-write circuit applied to digital identification according to claim 1, wherein the digital-to-analog converter is adapted to step down and convert the received digital signal into the corresponding pulse signal by using the following formula:
wherein, VoutIndicating the converted pulse signal, VinRepresenting the received digital signal.
4. The memristor read-write circuit applied to digital recognition, according to claim 3, wherein the memristor cell comprises a four-way memristor;
the input ports of the four memristors are respectively coupled with the output ends of the four digital-to-analog converters which are connected in parallel, and the output ends of the four memristors are mutually coupled to serve as the total output port of the memristors.
5. The memristor read-write circuit applied to digital identification, according to claim 4, wherein the voltage-to-current converter comprises a fifth operational amplifier and a sixth operational amplifier;
the V-end of the fifth operational amplifier is coupled with the third pin of the first four-pin header, the first ends of the first capacitor and the second capacitor, the third pin of the first four-pin header is also coupled with a-5V external direct current power supply, and the second ends of the first capacitor and the second capacitor are both grounded; the-INA end of the fifth operational amplifier is coupled with the fourth pin of the first four-pin header, the first end of a fifth capacitor and the first end of a fourth resistor respectively, the fourth pin of the first four-pin header is further coupled with the output end of the memristor unit, the second end of the fifth capacitor is coupled with the OUT _ A end of the fifth operational amplifier, the first end of a fifth resistor and the first end of a sixth resistor respectively, the second end of the fourth resistor is coupled with the second end of the fifth resistor and the first end of a seventh resistor respectively, and the second end of the seventh resistor is grounded; the + INA end of the fifth operational amplifier is grounded;
the terminal OUT _ B of the sixth operational amplifier is coupled to the second terminal of the sixth resistor; the V + end of the sixth operational amplifier is coupled with the second pin of the first four-pin header, the first end of the third capacitor and the first end of the fourth capacitor respectively; the second pins of the first four-pin header are also respectively coupled with a +5V external direct current power supply, and the second ends of the third capacitor and the fourth capacitor are both grounded; the + INB terminals of the sixth operational amplifier are all grounded, the-INB terminal of the sixth operational amplifier is coupled with the first terminal of the sliding resistor, and the second terminal of the sliding resistor is also coupled with the OUT _ B terminal of the sixth operational amplifier to serve as an output port of the current-voltage converter.
6. The memristor read-write circuit applied to digital identification according to claim 5, wherein the analog-to-digital converter is composed of a voltage reference circuit and an analog-to-digital conversion circuit;
the voltage reference circuit comprises a first diode, an eighth resistor, a ninth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a three-end adjustable shunt reference voltage source, a sixth capacitor and a seventh capacitor; a positive terminal of the first diode is coupled to a VCC terminal of the voltage reference circuit, a negative terminal of the first diode is coupled to a first terminal of an eighth resistor, a second terminal of the eighth resistor is coupled to a first terminal of a sixth capacitor and a first terminal of a ninth resistor, a second terminal of the sixth capacitor is grounded, a second terminal of the ninth resistor is coupled to a first terminal of an eleventh resistor, a second terminal of the eleventh resistor is coupled to a reference electrode of a three-terminal adjustable shunt reference voltage source and a first terminal of a twelfth resistor respectively, a cathode of the three-terminal adjustable shunt reference voltage source is coupled to a first terminal of a thirteenth resistor, a second terminal of the thirteenth resistor is coupled to a first terminal of a seventh capacitor and is coupled to the analog-to-digital conversion circuit as a reference voltage output port of the voltage reference circuit, and a cathode of the three-terminal adjustable shunt reference voltage source and a second terminal of the twelfth resistor R12 are both grounded;
the analog-to-digital conversion circuit comprises an analog-to-digital conversion chip, a fourteenth resistor, a fifteenth resistor, a sixteen resistor R5, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, an eighth capacitor and a ninth capacitor; the VDD end of the analog-to-digital conversion chip is coupled with the output end of the voltage reference circuit, the grounding end of the analog-to-digital conversion chip is grounded, a DOUT end, a DIN end and an ADDR end are respectively coupled with the data end, the clock end and the address selection end of the second digital circuit, the ADDR end is further coupled with a first end of a fourteenth resistor, and a second end of the fourteenth resistor is coupled with the ADDR end; the DIN terminal of the analog-to-digital conversion chip is also coupled with the first terminal of a fifteenth resistor, and the second terminal of the fifteenth resistor is coupled with the DOUT terminal; the DIN terminal of the analog-to-digital conversion chip is also coupled with one end of a sixteenth resistor, and the second end of the sixteenth resistor is coupled with the DIN terminal; the RDY end of the analog-to-digital conversion chip is grounded; the AIN0 terminal of the analog-to-digital conversion chip is coupled with the first terminal of the seventeenth resistor, and the AIN0 terminal is further coupled with the second terminal of the seventeenth resistor to serve as a channel 0; the AIN1 end of the analog-to-digital conversion chip is coupled with the first end of an eighteenth resistor, and the AIN1 end is further coupled with the second end of the eighteenth resistor to serve as a channel 1; the AIN2 terminal of the analog-to-digital conversion chip is coupled with the first terminal of a nineteenth resistor, and the AIN0 terminal is further coupled with the second terminal of the nineteenth resistor to serve as a channel 2; the AIN2 terminal of the analog-to-digital conversion chip is coupled with the first terminal of the twentieth resistor, and the AIN2 terminal is further coupled with the second terminal of the twentieth resistor to serve as a channel 3; the first end of the nineteenth resistor is further coupled to the first end of an eighth capacitor, and the second end of the eighth capacitor is grounded; the first end of the twentieth resistor is further coupled to the first end of the ninth capacitor, and the second end of the ninth capacitor is grounded.
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