CN109508310A - Virtual UART - Google Patents
Virtual UART Download PDFInfo
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- CN109508310A CN109508310A CN201710826989.5A CN201710826989A CN109508310A CN 109508310 A CN109508310 A CN 109508310A CN 201710826989 A CN201710826989 A CN 201710826989A CN 109508310 A CN109508310 A CN 109508310A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
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Abstract
Provide the virtual UART equipment in electronic equipment.Disclosed electronic equipment, have the function of provide by the first link first, the electronic equipment further includes the first UART module and the 2nd UART module, the sending port of first UAR T module is coupled to the receiving port of the 2nd UART module, and the receiving port of the first UART module is coupled to the sending port of the 2nd UART module；First UART module is coupled to the first link to provide the second function of electronic equipment, wherein by the first link, the sending port and the first link of receiving port of the first UART module are accessed；Electronic equipment provides response to the sending port of the 2nd UART module, to realize the second function of electronic equipment from the receiving port acquisition request of the 2nd UART module.
Description
Technical field
This application involves integrated circuit techniques, more particularly to provide virtual UART in integrated circuits, and by virtual
UART is communicated.
Background technique
Universal asynchronous receiving-transmitting transmitter (Universal Asynchronous Receiver/Transmitter) usually quilt
Referred to as U ART is common communication component in electronic equipment.
JTAG is writing a Chinese character in simplified form for the prefix letter of " joint test behavior group (Joint Test Action Group) ", JTA G
It is also a kind of international standard test protocol (IEEE 1149.1 is compatible), is mainly used for chip interior test.
PCIe protocol defines communication between devices mechanism.NVMe agreement is (referring also to " NVM Express Revision
1.2 " (calling NVMe agreement in the following text) the 3rd chapters, on November 3rd, 2014) define the mechanism for accessing non-volatile memory apparatus.PCIe device
It provides storage space (Memory Space).Couple the storage space of the host accessible PCIe device of PCIe device.
Fig. 1 shows the block diagram of the electronic equipment of background technique.Host (host) is coupled to by PCIe PHY module 110
Electronic equipment.Electronic equipment includes PCIe PHY module 110, Data Link Layer Module 120, transport layer module 130, memory
140 and cpu subsystem 160.PCIe PHY module 110 is for handling PCIe underlying protocol (such as physical layer).Transport layer module
130 may have access to memory 140 with 160 subsystem of cpu subsystem.Data Link Layer Module 120 is for handling PCIe data chain
Road layer protocol, transport layer module 130 is for handling PCIe transport layer protocol.Transport layer module 130 is also according to storage space
TLP (transport layer data packet, Transaction Layer Packet) accesses memory 140.And optionally, transport layer module
Memory 140 is written in TLP by 130, and is extracted TLP from memory 140 by cpu subsystem 160 and handled and transport layer module
130 obtain TLP from memory 140, and are sent to host by link layer module 120.Still optionally, transport layer module
TLP is sent to cpu subsystem 160 by 130, is handled by cpu subsystem 160 TLP.
Electronic equipment further includes UART 170, is coupled to the UART 180 of host.Root between UART 170 and UART 180
It is communicated according to specified protocol.UART provides the communication link except PCIe link for host and equipment, for for example to setting
Program etc. is run in standby PCIe system, CPU to be debugged.Debugging software and UAR T driver are run in host.UART drives
UART 180 in dynamic program managing main frame.Debugging software accesses UART 180 by UART driver, to pass through UART
170 are communicated with equipment.
UART 170 and UART 180 is coupled by physical leads, Yao Zhanyong equipment with host interface pin, and
Also the pin for occupying the chip in equipment, increases cost.And equipment is likely located at by the scene of large scale deployment far from people
The area of member workplace, to be led to not due to space/be physically difficult to contact through 170 access equipment of UART.
Summary of the invention
The purpose of the application includes the equipment interface pin for reducing UART and occupying, and provides a user and set by UART access
Standby convenient mechanism.
According to a first aspect of the present application, the first electronic equipment according to the application first aspect is provided, has and passes through
The first function that first link provides, the electronic equipment further includes the first UART module and the 2nd UART module, the first UART
The sending port of module is coupled to the receiving port of the 2nd UART module, and the receiving port of the first UART module is coupled to second
The sending port of UART module；First UART module is coupled to the first link to provide the second function of electronic equipment, wherein logical
The first link is crossed, the sending port and the first link of receiving port of the first UART module are accessed；Electronic equipment is from the 2nd UART
The receiving port acquisition request of module provides response to the sending port of the 2nd UART module, to realize the second of electronic equipment
Function.
According to the first electronic equipment of the application first aspect, provides and set according to the second electronics of the application first aspect
It is standby, wherein the first link is the link that PCIe bus provides.
According to the first or second electronic equipment of the application first aspect, the third according to the application first aspect is provided
The data being written into are supplied to second wherein the first UART module is written into data in response to its sending port by electronic equipment
The receiving port of UART module.
According to one of first of the application first aspect to third electronic equipment, provide according to the application first aspect
4th electronic equipment, wherein there are data in response to the receiving port of the 2nd UART module in the CPU of electronic equipment, from the 2nd UART
The receiving port of module reads data, and the acquisition request from the data of reading collects data according to the instruction of request, generates to asking
The response asked, and by response be written the 2nd UART module sending port.
According to the 4th electronic equipment of the application first aspect, provides and set according to the 5th electronics of the application first aspect
It is standby, wherein the request is debug command to the CPU of electronic equipment and the response is the sound to the debug command
It answers.
According to the 4th or the 5th electronic equipment of the application first aspect, the 6th according to the application first aspect is provided
Electronic equipment also suspends the operation of CPU wherein the CPU of the electronic equipment is in response to the request.
According to one of the first to the 6th electronic equipment of the application first aspect, provide according to the application first aspect
The data being written into are supplied to by the 7th electronic equipment wherein the 2nd UART module is written into data in response to its sending port
The receiving port of first UART.
According to the 7th electronic equipment of the application first aspect, provides and set according to the 8th electronics of the application first aspect
It is standby, wherein the sending port of the first UART module and receiving port are mapped to the address space of the first link, it is coupled to described
The CPU of another electronic equipment of first link may have access to the address space of the first link.
According to the 7th electronic equipment of the application first aspect, provides and set according to the 9th electronics of the application first aspect
It is standby, wherein the sending port of the first UART module is mapped to the address space of the first link, it is coupled to first link
The CPU of another electronic equipment may have access to the address space of the first link；First UART module is written into response to its receiving port
The data being written into are supplied to the memory of another electronic equipment by data.
According to the 9th electronic equipment of the application first aspect, provides and set according to the tenth electronics of the application first aspect
It is standby, wherein the CPU of another electronic equipment obtains the number for being written into the receiving port of the first UART module from its memory
According to.
According to one of the first to the tenth electronic equipment of the application first aspect, provide according to the application first aspect
11st electronic equipment, wherein the first UART module is written into data in response to its receiving port, to being coupled to first chain
Another electronic equipment on road indicates that the receiving port of the first UART is written into data.
According to the 11st electronic equipment of the application first aspect, the 12nd electricity according to the application first aspect is provided
Sub- equipment, wherein another electronic equipment obtains the data for being written into the receiving port of the first UART module, to obtain electronics
The response that the CPU of equipment is provided.
According to one of the first to the 12nd electronic equipment of the application first aspect, provide according to the application first aspect
The 13rd electronic equipment, wherein the sending port in response to the first UART module is written into data, the CPU of the electronic equipment
The data that the sending port of first UART module is written into are supplied to the receiving port of the 2nd UART module.
According to one of the first to the 13rd electronic equipment of the application first aspect, provide according to the application first aspect
The 14th electronic equipment, wherein first function is store function, and second function is debugging function.
According to the 14th electronic equipment of the application first aspect, the 15th electricity according to the application first aspect is provided
Sub- equipment, wherein the electronic equipment passes through first link couples to another electronic equipment, the logic of the electronic equipment
Address space is by the first application program of another electronic equipment by the first link-access to provide the first function；The electricity
First UART module of sub- equipment provides the by the first link-access by the second application program of another electronic equipment
Two functions.
According to the 14th or the 15th electronic equipment of the application first aspect, provide according to the application first aspect
16th electronic equipment, wherein the CPU of the electronic equipment runs debugging server, in response to the reception from the 2nd UART module
Debugging message is collected in the debug command that port obtains, and the response to debug command is supplied to the transmitting terminal of the 2nd UART module
Mouthful.
According to one of the 14th to the 16th electronic equipment of the application first aspect, provide according to the application first party
17th electronic equipment in face is set wherein the CPU of the electronic equipment runs storage service software in response to another electronics
The order of the standby store function using the electronic equipment and collect data and provide response to another electronic equipment.
According to one of the first to the 17th electronic equipment of the application first aspect, provide according to the application first aspect
The 18th electronic equipment, wherein first link is the link of wireless network or cable network.
According to one of the first to the 18th electronic equipment of the application first aspect, provide according to the application first aspect
The 19th electronic equipment, wherein the first UART and the 2nd UART respectively further include the port of instruction state, respectively for instruction
First UART and the 2nd respective sending port of UART whether can be written into data and the first UART and the 2nd UART is respective
Whether receiving port has data to be obtained.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, will be described below to embodiment
Needed in attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description is only some of the application
Embodiment for those of ordinary skill in the art without creative efforts, can also be attached according to these
Figure obtains other attached drawings.
Fig. 1 shows the block diagram of the electronic equipment of background technique；
Fig. 2A is the block diagram according to the electronic equipment of the embodiment of the present application；
Fig. 2 B is the block diagram according to the host of the embodiment of the present application；
Fig. 3 A is the flow chart for sending data to electronic equipment by virtual UART according to the embodiment of the present application host；
Fig. 3 B is the flow chart that host receives the data that electronic equipment provides from virtual UART according to an embodiment of the present application；
Fig. 4 illustrates the flow chart debugged according to control unit of the embodiment of the present application to electronic equipment；
Fig. 5 is the block diagram according to the electronic equipment of the another embodiment of the application；And
Fig. 6 is the block diagram according to the electronic equipment of another embodiment of the application.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description, it is clear that described embodiment is some embodiments of the present application, instead of all the embodiments.Based on this Shen
Please in embodiment, every other implementation obtained by those of ordinary skill in the art without making creative efforts
Example, shall fall in the protection scope of this application.
Fig. 2A is the block diagram according to the electronic equipment of the embodiment of the present application.Host (host) passes through PCIe PHY module 110
It is coupled to electronic equipment.Electronic equipment includes PCIe PHY module 110, Data Link Layer Module 120, transport layer module 230, deposits
Reservoir 140 and cpu subsystem 260.PCIe PHY module 110 is for handling PCIe underlying protocol (such as physical layer).Transport layer
Module 230 and 260 subsystem of cpu subsystem may have access to memory 140.Data Link Layer Module 120 is for handling PCIe number
According to link layer protocol, transport layer module 230 is for handling PCIe transport layer protocol.Transport layer module 230 is also according to TLP (transmission
Layer data packet, Transaction Layer Packet) access storage space and access memory 140.And optionally,
Memory 140 is written in TLP by transport layer module 130, and is extracted TLP from memory 140 by cpu subsystem 260 and handled, and
Transport layer module 230 obtains TLP from memory 140, and is sent to host by link layer module 120.Still optionally, it passes
TLP is sent to cpu subsystem 160 by defeated layer module 130, is handled by cpu subsystem 160 TLP.
Virtual UART module 210 is coupled to transport layer module 230, the UART for accessing for host.Virtual UAR T module
210 provide the function of standard UART equipment with virtual UART module 220.Virtual UART module 210 is coupled to virtual UART module
220.Virtual UART module 210 and virtual UART module 220 respectively include the port of sending port, receiving port, instruction state.
Optionally, virtual UART module 210 and virtual UART module 220 respectively further include interrupting generating unit, with to host/CPU
The instruction of system 260 is interrupted.The sending port of virtual UART module 210 is coupled to the receiving port of virtual UART module 220.Virtually
The sending port of UART module 220 is coupled to the receiving port of virtual UART module 210.The transmitting terminal of virtual UART module 210
Mouth can be accessible to hosts with receiving port.The sending port and receiving port of virtual UART module 220 can be by cpu subsystems 260
Access.Host provides data to the sending port of virtual UART module 210, and host is supplied to its hair by virtual UART module 210
The data of sending end mouth are transferred to the receiving port of virtual UART module 220, and cpu subsystem 260 connects from virtual UART module 220
Receiving end mouth obtains data.Cpu subsystem 260 provides data, virtual UART module to the sending port of virtual UART module 220
220 are transferred to the data that host is supplied to its sending port the receiving port of virtual UART module 210, and host is from virtual UART
The receiving port of module 210 obtains data.The end of virtual UART module 210 and the respective instruction state of virtual UART module 220
Mouthful, indicate whether sending port/receiving port of the virtual UART module 220 of virtual UART module 210/ can be accessed (for example, hair
Sending interface that can be written into data and/or receiving interface has data to be read).Corresponding port is indicated in the port of instruction state
When can not be accessed, even if data are written to the sending port of virtual UART module, the data being written into are not processed yet or lose
It abandons.
As an example, the port of the sending port of virtual UART module 210, receiving port and instruction state is mapped to
The storage space of PCIe device or expanded configuration space (Extended Configuration Space), host passes through visit
Ask storage space/expanded configuration space of PCIe device, sending port, receiving end with realization to virtual UART module 210
The access of the port of mouth and instruction state.Optionally, virtual UART module 210 be when sending port/receiving port can be accessed,
Such as MSI-X is provided to host to interrupt.As another example, virtual UART module 210 is virtual as PCIe device or PCIe
Function (VF, Virtual) is presented to host.
Still as an example, the port of the sending port of virtual UART module 220, receiving port and instruction state is reflected
It is mapped to the addressable space of cpu subsystem 260.Cpu subsystem 260 accesses the sending port of virtual UART module 220, receiving end
Mouthful and instruction state come operate UART module 220 offer UART equipment.Optionally, virtual UART module 220 is in transmitting terminal
When mouth/receiving port can be accessed, interruption is provided to cpu subsystem 260.
According to an embodiment of the present application, storage space of the transport layer module 230 also according to TLP access is mapped to virtually
Data entrained by the TLP in memory write space are supplied to the sending port of UART module 210 by UART module 210；Or for
The TLP for reading storage space obtains data as the response to TLP from the receiving port of UART module 210.With similar side
Formula, host access the port of the instruction state of virtual UART module 210 by TLP, and transport layer module 230 accesses empty according to TLP
The port of the instruction state of quasi- UART module 210.
Optionally, electronic equipment includes multiple pairs of virtual UART modules, a pair of virtual UART module of host accessible
One of, and the cpu subsystem 260 of electronic equipment access this to virtual UART module another, to be set in host and electronics
It is communicated between standby by UART mechanism.
Fig. 2 B is the block diagram according to the host of the embodiment of the present application.Host includes PCIe controller, is assisted as PCIe is met
The main equipment of view is coupled to the PCIe PHY module of electronic equipment, for communicating with electronic equipment.Host also runs and for example debugs
Software, UART driver and/or PCIe driver.PCIe driver drives journey for managing PCIe controller, UART
Sequence is for managing the virtual UART module 210 provided on PCIe device (referring also to Fig. 2A).UART driver is for example to mark
The port of quasi- UART driver, the sending port of standard UART equipment of access, receiving port and instruction state is reflected
It is mapped to storage space or expanded configuration space (Extended that PCIe driver provides, in PCIe device
Configuration Space) in the sending port of virtual UART module 210, receiving port and instruction state port.
Debugging software is the common debugging software that the UART for example managed by UART drive software debugs electronic equipment.It is optional
Ground, in the prior art, the various software for accessing UART can access virtual UART module by standard UART drive software
210.In the software of access UART, virtual UART module 210 is the UART of host, or positioned at the PCIe main equipment of host
UART, and be coupled to as PCIe from the UART (being provided by virtual UART module 220) on the electronic equipment of equipment.
Fig. 3 A is the flow chart communicated by virtual UART according to the embodiment of the present application.In Fig. 3 A, it is logical to illustrate host
Cross the process that virtual UART sends message to electronic equipment.Application program (for example, debugging software of Fig. 2 B) in host uses
UART driver (referring also to Fig. 2 B), the electronics by PCIe driver, by PCIe bus access as PCIe device
Data (310) are written to the sending port of virtual UART module 210 in virtual UART module 210 (referring to Fig. 2A) in equipment.Example
Such as, the sending port of virtual UART module 210 is mapped to the specified address of the storage space of PCIe device, and application program is logical
UART driver and PCIe driver are crossed, is come to the specified address write-in data of the storage space of PCIe device to virtual
Data are written in the sending port of UART module 210.What virtual UART module 210 was sent to that port receives is written into data, mentions
Supply the receiving port (320) of the virtual UART module 220 on PCIe device.The CPU of PCIe device is (for example, CPU of Fig. 2A
System 260) in response to the receiving port of virtual UART module 220 there are data, it is obtained from the receiving port of virtual UART module 220
Access is according to (330).Optionally, there are data in the receiving port in response to virtual UART module 220, and virtual UART module 220 is set
The port of its instruction state is set, to indicate that data occurs in receiving port.Finger of the CPU of PCIe device from virtual UART module 220
The port for showing state knows that data occurs in the receiving port of virtual UART module 220, and from the reception of virtual UART module 220
Port obtains data.Still optionally, there is data, virtual UART module in the receiving port in response to virtual UART module 220
220 issue interrupt requests to CPU, to indicate that data occurs in the receiving port of the virtual UART module 220 of CPU.
Fig. 3 B is the flow chart communicated by virtual UART according to the another embodiment of the application.In Fig. 3 B, master is illustrated
Machine obtains the process of message by virtual UART from electronic equipment.The CPU (for example, cpu subsystem 260 of Fig. 2A) of PCIe device
Data (340) are written to the sending port of the virtual UART module 220 of PCIe device.Virtual UART module 220 is sent to hold
What mouth received is written into data, is supplied to the receiving port (350) of the virtual UART module 210 on PCIe device.Virtual UART
Module 210 is additionally in response to receiving port and receives data, and updates the port of its instruction state to indicate to occur on its receiving port
There are data to be read.UART drive software in host identifies the virtual UART module 210 on PCIe device by PCIe bus
Receiving port there are data (360) to be read.For example, virtual UART module 210 is written into data in response to its receiving port,
It generates and interrupts to host.UART drive software in host in response to PCIe device interruption, from connecing for virtual UART module 210
Receiving end mouth obtains data (370), and is supplied to the application program in host.Application program as another example, in host
Or UART driver poll is located at the port of the instruction state of the virtual UART module 210 of PCIe memory spatially, and
Instruction state port instruction receiving port have data it is to be read when, from receiving port obtain data.
Fig. 4 illustrates the flow chart debugged according to control unit of the embodiment of the present application to electronic equipment.In response to
The debugging operations of user, the debugging software operated on host receive debug command (410) from the user.Debug command is example
Such as suspend CPU operation, setting program breakpoint, obtains memory variable value, obtain software stack information, restore CPU operation.It debugs soft
Part is to debugging command code, the virtual UART mould debug command of coding being sent to by UART driver on PCIe device
The sending port (420) of block 210 (referring to Fig. 2A).According to an embodiment of the present application, it is coupled to the electronics of the PCIe bus of host
Equipment provides two PCIe devices, one is virtual UART equipment, the other is the equipment of the objective function of electronic equipment is provided,
For example, NVMe stores equipment.Virtual UART module 210 is sent to the debug command that port receives, and is supplied in PCIe bus
Virtual UART module 220 receiving port (430).The CPU (for example, cpu subsystem 260 of Fig. 2A) of PCIe device in response to
There is debug command in the receiving port of virtual UART module 220, obtains debug command from the receiving port of virtual UART module 220
(440).Optionally, debug command is made of multiple UART data frames, and more times of the CPU of PCIe device is from virtual UART module 220
Receiving port obtain data, and by the data repeatedly obtained form debug command.Still optionally, in response to virtual UART mould
The receiving port of block 220 receives debug command, and virtual UART module 220 is generated to CPU and interrupted, CPU as the response to interruption,
Save the operation scene of present procedure, and obtain data from the receiving port of virtual UART module 220, optionally, more times of CPU from
The receiving port of virtual UART module 220 obtains data, and the data repeatedly obtained are formed debug command.
The CPU of PCIe device collects the data (450) that be supplied to the debugging software of host operation according to debug command.Example
Such as, debug command is the order for suspending CPU operation, and in response, CPU obtains currently running program address, stops to work as
The operation of preceding program generates instruction CPU information out of service, and it is virtual will to indicate that CPU information out of service is written
The sending port (460) of UART module 220.And optionally, CPU also monitor the receiving port of virtual UART module 220 with etc.
To further debug command.As another example, debug command is for obtaining memory variable value, in response, CPU foundation
The specified memory address of debug command or variable name obtain corresponding value, generate the information of instruction memory variable and its value, and will
220 sending port (460) of virtual UART module is written in information.
What virtual UART module 220 was sent to that port receives is written into data, is supplied to virtual on PCIe device
The receiving port (470) of UART module 210.Virtual UART module 210 is additionally in response to receiving port and receives data, and updates it and refer to
Show the port of state to indicate to occur there are data to be read on its receiving port.UART driver in host is total by PCIe
Line identifies that data (480) to be read occurs in the receiving port of the virtual UART module 210 on PCIe device.Debugging software is from PCIe
The receiving port of virtual UART module 210 in equipment obtains data, and is shown to user (490).
In alternative embodiments, the sending port for the virtual UART module 210 that UART driver is managed is reflected
It is mapped to the storage space of PCIe device, and the receiving port of virtual module 210 is mapped to the designated memory space of host.
Virtual UART module 210 is written into data in response to its receiving port, generates to the CPU of transport layer module 230 or PCIe device
It interrupts.As the response to interruption, the CPU of transport layer module 230 or PCIe device is by the receiving port of virtual UART module 210
Data be sent to the designated memory space of host, and send interrupt requests to host.In host side, as to interruption
Response, debugging software obtain the data for carrying out the receiving port of self-virtualizing UART module 210 from the designated memory space of host, and
Show user.Still optionally, debugging software repeatedly accesses the receiving port of virtual UART module 210, by the data of acquisition
Combination, and show user.
Fig. 5 is the block diagram according to the electronic equipment of the another embodiment of the application.Host (host) passes through PCIe PHY module
110 are coupled to electronic equipment.Electronic equipment includes PCIe PHY module 110, Data Link Layer Module 120, transport layer module
530, memory 540 and cpu subsystem 560.Transport layer module 530 and 560 subsystem of cpu subsystem may have access to memory
540.Transport layer module 250 is for handling PCIe transport layer protocol.Transport layer module 530 also according to TLP (transport layer data packet,
Transaction Layer Packet) access storage space and access memory 540.And optionally, transport layer mould
Memory 540 is written in TLP by block 530, and is extracted TLP from memory 540 by cpu subsystem 560 and handled and transport layer mould
Block 530 obtains TLP from memory 540, and is sent to host by link layer module 120.
According in the embodiment of Fig. 5, the port of the sending port of virtual UART module 510, receiving port and instruction state
It is mapped to the designated memory space of PCIe device.Transport layer module 530 identifies the storage space of TLP access.For writing
Enter to correspond to the TLP of the designated memory space of the sending port of virtual UART module 510, the data that will be written are stored in
Reservoir 540, and send and interrupt to cpu subsystem 560.In response, cpu subsystem 560 obtains write-in virtually from memory 540
The data of the sending port of UART module 510, and write data into the receiving end of the virtual UART module 520 in 540
Mouthful.And another interruption is sent to cpu subsystem 560 (or other CPU).In response, cpu subsystem 560 is from memory 540
The data that the receiving port of virtual UART module 520 is written are obtained, and identify debug command from data.
Cpu subsystem 560 collects the data that be supplied to host according to debug command, and the void in memory 540 is written
The sending port of quasi- UART module 520.And it sends and interrupts to cpu subsystem 560.In response, cpu subsystem 560 is from depositing
Reservoir 540 obtains the data that the sending port of virtual UART module 520 is written, and writes data into connecing for virtual UART module 510
Receiving end mouth.And another interruption is sent to cpu subsystem 560 (or other CPU).Again in response, cpu subsystem 560 (or
Other CPU) it sends and interrupts to host, to indicate that data occurs in the receiving port of virtual UART module 510.
Optionally, the virtual UART module 510 in cpu subsystem poll memory 540 and/or virtual UART module 520
Instruction state port, there are data to obtain in its respective port.
Fig. 6 is the block diagram according to the electronic equipment of another embodiment of the application.Host (host) is coupled to by Ethernet
Electronic equipment.Electronic equipment includes ethernet PHY module 610, TCP/IP module 620 and cpu subsystem 660.CPU subsystem
The virtual UART module 630 of 660 simulation of system and virtual UART module 640.Ethernet PHY module 610 is for handling Ethernet bottom
Agreement (such as physical layer).TCP/IP module 620 handles ICP/IP protocol.Optionally, TCP/IP module 620 also handles such as UDP
Deng other network protocols.As an example, cpu subsystem 660 obtains data from TCP connection.The debugging software and electronics of host
Equipment cpu subsystem 660 is communicated with application layer protocol, and by application layer protocol, the debugging software of host specifies the void to be accessed
Quasi- UART module 630 and its designated port.For example, the debugging software of host is written to the sending port of virtual UART module 630
Data, to indicate debug command.Cpu subsystem 660 identifies the transmitting terminal of virtual UART module 630 by application layer protocol
Mouth is written into data, and the data that the sending port of virtual UART module 630 is written are written to the receiving end of virtual UART module 640
Mouthful.Cpu subsystem 660 (for example, another program) obtains data from the receiving port of virtual UART module 640, and data are identified
For debug command, and Debugging message is collected according to debug command, and the transmission that agreement will be debugged virtual UART module 640 is written
Port.Cpu subsystem 660 is written into data in response to the sending port of virtual UART module 640, writes data into virtual UART
The receiving port of module 630.And the data of the receiving port of virtual UART module 630 are also passed through TCP/ by cpu subsystem 660
IP module 620 is sent to the debugging software of host, shows Debugging message by the debugging software of host operation.
Virtual UART module 630 and/or virtual UART module 640 are provided, are conducive to reuse existing debugging tool.Example
Such as, GDB server (GDB Server) is run by cpu subsystem 660, GDB server passes through the UART equipment in electronic equipment
With the UART equipment communication in host.Due to providing virtual UART module 640, GDB server is accessed in a manner of existing by virtual
The UART equipment that UART module 640 is simulated, and need not accordingly modify.Similarly, the debugging tool run in host is also with existing
Mode accesses the UART equipment simulated by virtual UART module 630, need not also make corresponding modification.To can be used existing more
Kind debugging tool, debugs the electronic equipment according to the embodiment of the present application.And existing a variety of works communicated using UART equipment
Tool, can also use together with the electronic equipment according to the embodiment of the present application.
As another embodiment, virtual UART module 630 is provided in electronic equipment without providing virtual UART module
640.For example, data are written to the sending port of virtual UART module 630 in the debugging software of host, to indicate debug command.CPU
Subsystem 660 identifies that the sending port of virtual UART module 630 is written into data by application layer protocol, will be from virtual
The data that UART module 630 obtains are identified as debug command, and collect Debugging message according to debug command, and will debug agreement
The receiving port of virtual UART module 630 is written.And cpu subsystem 660 is also by the receiving port of virtual UART module 630
Data are sent to the debugging software of host by TCP/IP module 620, show Debugging message by the debugging software of host operation.
Although above as an example with PCIe bus, Ethernet, describing according to the embodiment of the present application with virtual
The electronic equipment of UART, one of ordinary skill in the art are it is to be appreciated that can be used a variety of communications such as JTAG, bluetooth, WIFI, USB
Link is substituted according to the PCIe bus or Ethernet in the embodiment of the present application.The agreements such as bluetooth, WIFI provide physical layer, number
It is described according to link layer, supports the various protocols such as TCP/IP thereon, carried by Transmission Control Protocol according to the virtual of the embodiment of the present application
UART.Usb protocol provides interface for each equipment.According to the virtual UART of the embodiment of the present application as USB device, and will be empty
The port mapping of quasi- UART is operated by accessing the endpoint of USB device according to the embodiment of the present application to the endpoint of USB device
Virtual UART.
According to presently filed embodiment, electronic equipment need not provide the port physics UART, save cost.And it need not
The field adjustable electronic equipment disposed to electronic equipment, and the host that electronic equipment is coupled can be remotely accessed, and pass through
The debugging software run on host collects internal state, the operation scene of electronic equipment by the virtual UART of electronic equipment,
And it is debugged.Electronic equipment can be such as solid state hard disk, vehicle electronic device, graphics card, keyboard, intelligent terminal.
The above, the only specific embodiment of the application, but the protection scope of the application is not limited thereto, it is any
Those familiar with the art within the technical scope of the present application, can easily think of the change or the replacement, and should all contain
Lid is within the scope of protection of this application.Therefore, the protection scope of the application should be subject to the protection scope in claims.
Claims (10)
1. a kind of electronic equipment has the function of provide by the first link first, the electronic equipment further includes the first UART
Module and the 2nd UART module, the sending port of the first UART module are coupled to the receiving port of the 2nd UART module, and first
The receiving port of UART module is coupled to the sending port of the 2nd UART module；
First UART module is coupled to the first link to provide the second function of electronic equipment, wherein by the first link, first
The sending port and the first link of receiving port of UART module are accessed；
Electronic equipment is answered from the receiving port acquisition request of the 2nd UART module to the offer of the sending port of the 2nd UART module
It answers, to realize the second function of electronic equipment.
2. electronic equipment according to claim 1, wherein
First UART module is written into data in response to its sending port, and the data being written into are supplied to the 2nd UART module
Receiving port.
3. electronic equipment according to claim 1 or 2, wherein
There are data in response to the receiving port of the 2nd UART module in the CPU of electronic equipment, from the receiving end of the 2nd UART module
Mouth reads data, and the acquisition request from the data of reading collects data according to the instruction of request, generates the response to request, and
Response is written to the sending port of the 2nd UART module.
4. electronic equipment according to claim 3, wherein
The request is that the debug command and the response to the CPU of electronic equipment are the responses to the debug command.
5. electronic equipment according to claim 3 or 4, wherein
The CPU of the electronic equipment in response to the request, also suspends the operation of CPU.
6. electronic equipment described in one of -5 according to claim 1, wherein
2nd UART module is written into data in response to its sending port, and the data being written into are supplied to the reception of the first UART
Port.
7. electronic equipment according to claim 6, wherein
The sending port and receiving port of first UART module are mapped to the address space of the first link, are coupled to described first
The CPU of another electronic equipment of link may have access to the address space of the first link.
8. electronic equipment according to claim 6, wherein
The sending port of first UART module is mapped to the address space of the first link, is coupled to the another of first link
The CPU of electronic equipment may have access to the address space of the first link；First UART module is written into data in response to its receiving port,
The data being written into are supplied to the memory of another electronic equipment.
9. electronic equipment described in one of -8 according to claim 1, wherein
The electronic equipment passes through first link couples to another electronic equipment, the logical address space of the electronic equipment
By the first application program of another electronic equipment by the first link-access to provide the first function；The electronic equipment
First UART module is by the second application program of another electronic equipment by the first link-access to provide the second function.
10. electronic equipment according to claim 9, wherein
The CPU of the electronic equipment runs debugging server, in response to the debugging obtained from the receiving port of the 2nd UART module
Debugging message is collected in order, and the response to debug command is supplied to the sending port of the 2nd UART module.
From receiving port whether have data to be obtained.
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| CN201710826989.5A CN109508310B (en) | 2017-09-14 | 2017-09-14 | Virtual UART |
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