CN109507934B

CN109507934B - Cascade self-adaptive digital I/O and analog signal acquisition circuit

Info

Publication number: CN109507934B
Application number: CN201811592400.0A
Authority: CN
Inventors: 魏东兴; 王诗涵
Original assignee: Dalian University of Technology
Current assignee: Dalian University of Technology
Priority date: 2018-12-25
Filing date: 2018-12-25
Publication date: 2021-04-09
Anticipated expiration: 2038-12-25
Also published as: CN109507934A

Abstract

The invention provides a cascade self-adaptive digital I/O and analog signal acquisition circuit, which comprises a digital input circuit, an analog signal input circuit, an analog power supply, a digital power supply, an ADC reference voltage circuit, an RS-485 interface circuit and a digital signal output circuit. The circuit of the invention simultaneously collects a plurality of paths of digital input signals and analog input signals, transmits the signals to the MCU module, and can control the output of the digital signals by the MCU module. The circuit supports cascade adaptive adjustment and realizes cascade operation of single or multiple circuits. When the plurality of circuits work in a cascade mode, the circuits communicate with each other through a serial communication interface UART of the MCU, the cascade order is identified in a self-adaptive mode, the inquiry control signals are received, the collected signals are transmitted to the circuit with the highest priority, and the inquiry and control of an upper computer are waited. The technical scheme of the invention solves the problems that the acquisition of multi-path digital input signals and analog input signals in the prior art causes the increase of system complexity and the number of channels of signal I/O cannot be adjusted in a self-adaptive manner.

Description

Cascade self-adaptive digital I/O and analog signal acquisition circuit

Technical Field

The invention relates to the technical field of communication control, in particular to a cascade self-adaptive digital I/O and analog signal acquisition circuit.

Background

In the field of communication control, many real-time data are represented by digital signals and analog signals, so that multiple paths of digital signals and analog signals are often acquired for state query and output control, and the acquisition technology is mature. For the multi-channel signals, the acquisition device with a plurality of channels is mainly used for acquisition, or the multi-channel switch device is used for realizing signal acquisition in a channel switching mode;

conventionally, the following problems exist for the acquisition of digital and analog input signals:

(1) the acquisition of digital input signals and analog input signals is often performed in different circuit modules, increasing system cost and circuit complexity;

(2) the number of channels of the signal I/O has limitations, and the adjustment of the number of channels cannot be flexibly and adaptively realized according to actual requirements.

Disclosure of Invention

According to the technical problems that the acquisition of a plurality of paths of digital input signals and analog input signals leads to the increase of system complexity and the number of channels of signal I/O cannot be adjusted in a self-adaptive mode, the digital I/O and analog signal acquisition circuit with the cascade self-adaptation function is provided. The circuit of the invention simultaneously collects a plurality of paths of digital input signals and analog input signals, transmits the signals to the MCU module, and can control the output of the digital signals by the MCU module. The circuit supports cascade adaptive adjustment and realizes cascade operation of single or multiple circuits. When the plurality of circuits work in a cascade mode, the circuits communicate with each other through a serial communication interface UART of the MCU, the cascade order is identified in a self-adaptive mode, the inquiry control signals are received, the collected signals are transmitted to the circuit with the highest priority, and the inquiry and control of an upper computer are waited.

The technical means adopted by the invention are as follows:

a cascaded, adaptive digital I/O and analog signal acquisition circuit, comprising:

the digital input circuit is used for inputting the digital input signal to the MCU module for processing after the optical coupling isolation;

the analog signal input circuit converts the current signal into a voltage signal through the standard resistor and outputs the voltage signal to an ADC circuit arranged in the MCU module for sampling;

the analog power supply is used for providing power supply voltage for the analog signal input circuit;

a digital power supply for providing a supply voltage to the digital input circuit;

an ADC reference voltage circuit for providing a reference voltage for the ADC circuit;

the RS-485 interface circuit is used for transmitting input signals acquired by all the cascade circuits to the upper computer by adopting a Modbus communication protocol and receiving digital output signals sent by the upper computer;

and a digital signal output circuit;

when the circuit works, the digital input circuit collects a plurality of paths of digital input signals, the analog signal input circuit collects a plurality of paths of analog input signals, the collected signals are transmitted to the MCU module, the MCU module controls the output of the plurality of paths of digital signals, the circuit supports cascade adaptive adjustment, a serial communication interface between circuit boards is reserved, when a plurality of circuits work in a cascade mode, the cascade sequence is automatically identified, the priority is defined, the collected signals are transmitted to the circuit with the highest priority, and the digital output signals are transmitted to the circuit with the low priority; the low-priority circuit communicates with the serial communication interface UART3 of the MCU module of the high-priority circuit through the serial communication interface UART2 of the MCU module, and the circuit with the highest priority communicates with the upper computer through the serial communication interface UART4 of the MCU module through an RS-485 bus to receive state inquiry and control commands of the upper computer.

Further, the MCU module comprises an STM32 microprocessor of an STM32F103VCT6 chip adopting a Cortex-M3 architecture and a peripheral configuration circuit.

Further, the analog signal input circuit further comprises a voltage follower formed by an operational amplifier LM2904 chip.

Further, the digital signal output circuit comprises an ULN2803 transistor array for driving the relay to operate.

Further, the digital power supply comprises a voltage reduction switch type integrated voltage regulation chip LM2576 for outputting 5V power supply voltage in a PWM control mode and a voltage regulator SPX5205M5-L-3-3 chip for converting the 5V power supply voltage into 3.3V power supply voltage.

Further, the analog power supply includes a 5V linear regulator 78M05 chip for converting a 24V supply voltage to a 5V supply voltage and a low noise LDO regulator SPX5205M5-L-3-3 chip for converting a 5V voltage to a 3.3V supply voltage.

Compared with the prior art, the invention has the following advantages:

1. in the invention, a plurality of paths of digital input signals and analog input signals are acquired at the same time, and the output of digital signals (relays) is controlled, so that the system integration is increased, and the system cost and the circuit complexity are reduced;

2. in the invention, the channels can be expanded in a cascade mode among the circuits, the adjustment of the number of I/O channels can be realized flexibly and adaptively according to actual requirements, 8-24 channels of analog input signals are acquired, 40-120 channels of digital input signals are acquired, and 8-24 channels of digital signals are output. Data are transmitted between the cascade circuits every 50ms, and real-time performance can be achieved when the upper computer conducts state query.

In conclusion, the technical scheme of the invention solves the problems that the system complexity is increased and the channel number of signal I/O cannot be adjusted in a self-adaptive manner due to the acquisition of multiple paths of digital input signals and analog input signals in the prior art.

For the above reasons, the present invention can be widely applied to the fields of communication control and the like.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a block diagram of a system according to an embodiment of the present invention.

Fig. 2 is a flowchart of an electrical path procedure provided by the embodiment of the present invention.

Fig. 3 is a flowchart of a communication subroutine of the circuit state 11 according to an embodiment of the present invention.

Fig. 4 is a flowchart of a communication subroutine of the circuit state 10 according to an embodiment of the present invention.

Fig. 5 is a flowchart of a communication subroutine of circuit state 01 according to an embodiment of the present invention.

Fig. 6 is a flowchart of a communication subroutine of circuit state 00 according to an embodiment of the present invention.

Detailed Description

It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.

The relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description. Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. Any specific values in all examples shown and discussed herein are to be construed as exemplary only and not as limiting. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

As shown in fig. 1, the present invention provides a cascade adaptive digital I/O and analog signal acquisition circuit, comprising: the digital input circuit is used for inputting the digital input signal to the MCU module for processing after the optical coupling isolation; the analog signal input circuit converts the current signal into a voltage signal through the standard resistor and outputs the voltage signal to an ADC circuit arranged in the MCU module for sampling; the analog power supply is used for providing power supply voltage for the analog signal input circuit; a digital power supply for providing a supply voltage to the digital input circuit; an ADC reference voltage circuit for providing a reference voltage for the ADC circuit; the RS-485 interface circuit is used for transmitting input signals acquired by all the cascade circuits to the upper computer by adopting a Modbus communication protocol and receiving digital output signals sent by the upper computer; and a digital signal output circuit;

As a preferred embodiment of the invention, a 5V linear voltage regulator 78M05 chip is adopted for the analog power supply to convert 24V power supply voltage into 5V power supply voltage; converting 5V voltage into 3.3V power supply voltage by adopting a low-noise LDO voltage stabilizer SPX5205M5-L-3-3 chip;

as a better embodiment of the invention, the digital power supply adopts a voltage reduction switch type integrated voltage stabilization chip LM2576 in a PWM control mode and outputs 5V power supply voltage; the voltage regulator SPX5205M5-L-3-3 chip converts the 5V power supply voltage into 3.3V power supply voltage;

as a better embodiment of the invention, the ADC reference voltage circuit adopts a precise, micro-power consumption and low-voltage reference voltage source REF192 chip to generate 2.5V as the reference voltage of the ADC circuit;

as a better implementation mode of the invention, the 4-20mA analog signal input circuit converts a current signal into a voltage signal through a standard resistor, and the voltage signal is output to the MCU built-in ADC for sampling processing through a voltage follower formed by an operational amplifier LM2904 chip;

as a preferred embodiment of the invention, the MCU module is an STM32 microprocessor and its peripheral configuration circuit, and the MCU chip adopts an STM32F103VCT6 chip of Cortex-M3 architecture;

as a preferred embodiment of the present invention, the digital signal input circuit adopts a TLP281-4 transistor to output the photoelectric coupler, and inputs the digital input signal to the MCU for processing after the photoelectric coupling isolation; the digital signal output circuit adopts an ULN2803 transistor array to drive the relay to work;

as a better implementation mode of the invention, the RS-485 interface circuit adopts a MAX3485 chip to complete input and drive, and the circuit with the highest priority transmits input signals acquired by all the cascade circuits to the upper computer and receives digital output signals sent by the upper computer.

Example 1

As shown in fig. 2, the present invention further provides a circuit program diagram of a cascade adaptive digital I/O and analog signal acquisition circuit, wherein the process includes the following steps:

s1: initializing a system clock, a GPIO (general purpose input/output), a timer, a UART (universal asynchronous receiver/transmitter) and the like;

s2: identifying the number of cascaded circuit boards, judging according to two GPIO port lines Master and Slave (both in a pull-up input mode) of the MCU, if the circuit has a first-stage input, setting the Master to be a low level, and if the circuit has a next-stage output, setting the Slave to be a low level, wherein the Master is a high level;

s3: the state of the cascade circuit board is determined, and the specific state is as follows:

state 11: there is only one circuit in the system;

state 10: two or three circuits are cascaded in the system, and the circuit with the lowest priority (namely the circuit No. 2/2 or No. 3/3);

state 01: two or three circuits are cascaded in the system, and the circuit is the highest priority circuit (namely, the circuit No. 1/2 or the circuit No. 1/3);

state 00: there are three circuits in the system cascaded, which is circuit No. 2/3.

S4: collecting digital input signals and collecting analog input signals;

s5: executing the corresponding communication subprogram according to the cascade state;

s6: the digital signal output program is executed.

Example 2

On the basis of embodiment 1, the present invention further provides a communication subprogram flow chart executed in different cascade states of the circuit, and the communication subprogram flow chart is divided into the following four states:

as shown in fig. 3, the flow of the communication subroutine for the cascaded circuit board state 11 is as follows:

s301: starting a UART4 interrupt;

s302: judging whether the UART4 receives data, and if not, exiting the subprogram; if the data is received, entering an interrupt processing function, and receiving Modbus communication protocol data sent by an upper computer;

s303: judging whether the UART4 data is received completely, if so, executing the step S304, otherwise, exiting the subprogram;

s304: and processing the data received by the UART4 and transmitting back the function data requested by the upper computer.

As shown in fig. 4, the communication subroutine flow for the cascaded circuit board state 10 is as follows:

s301: starting a UART2 interrupt;

s302: judging whether the timing time is up, if so, executing step S303; otherwise, executing step S304;

s303: transmitting the collected input signal to an upper-stage circuit through a UART 2;

s304: judging whether the UART2 receives data, and if not, exiting the subprogram; if receiving data, entering an interrupt processing function, and receiving a digital output signal sent by a previous-stage circuit;

s305: judging whether the UART2 data is received completely, if so, executing step S306; otherwise, the subroutine is exited.

S306: processes data received by UART 2.

As shown in fig. 5, the flow of the communication subroutine for cascaded circuit board state 01 is as follows:

s301: starting UART3 and UART4 interrupts;

s302: determining whether the UART4 receives data, if not, performing step S307; if the data is received, entering an interrupt processing function, and receiving Modbus communication protocol data sent by an upper computer;

s303: judging whether the UART4 data is received completely, if so, executing step S304, otherwise, executing step S305;

s304: processing data received by the UART4, and returning functional data requested by the upper computer;

s305: judging whether the timing time is up, if so, executing step S306; otherwise, executing step S307;

s306: transmitting the digital output signal to a next stage circuit through a UART 3;

s307: judging whether the UART3 receives data, and if not, exiting the subprogram; if receiving data, entering an interrupt processing function, and receiving an input signal sent by a next-stage circuit;

s308: judging whether the UART3 data is received completely, if so, executing the step S309, otherwise, exiting the subprogram;

s309: processes data received by UART 3.

As shown in fig. 6, the flow of the communication subroutine for cascaded circuit board state 00 is as follows:

s301: starting UART2 and UART3 interrupts;

s303: the collected input signals are transmitted to the upper-stage circuit through the UART2, and digital output signals are transmitted to the lower-stage circuit through the UART 3;

s304: determining whether the UART2 receives data, if not, performing step S307; if receiving data, entering an interrupt processing function, and receiving a digital output signal sent by a previous-stage circuit;

s305: judging whether the UART2 data is received completely, if so, executing step S306; otherwise, executing step S307;

s306: processing data received by the UART 2;

s309: processes data received by UART 3.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A cascaded, adaptive digital I/O and analog signal acquisition circuit, comprising:

the analog signal input circuit converts the current signal into a voltage signal through the standard resistor and inputs the voltage signal to an ADC circuit arranged in the MCU module for sampling;

and a digital signal output circuit;

2. The cascaded adaptive digital I/O and analog signal acquisition circuit of claim 1, wherein the MCU module comprises an STM32 microprocessor and peripheral configuration circuitry of an STM32F103VCT6 chip employing a Cortex-M3 architecture.

3. The cascaded adaptive digital I/O and analog signal acquisition circuit of claim 1, wherein the analog signal input circuit further comprises a voltage follower comprised of an operational amplifier LM2904 chip.

4. The cascaded adaptive digital I/O and analog signal acquisition circuit of claim 1, wherein the digital signal output circuit comprises an ULN2803 array of transistors for driving relay operation.

5. The cascaded adaptive digital I/O and analog signal acquisition circuit according to claim 1, wherein the digital power supply comprises a buck switch type integrated voltage regulation chip LM2576 outputting a 5V supply voltage in a PWM control manner and a voltage regulator SPX5205M5-L-3-3 chip for converting the 5V supply voltage into a 3.3V supply voltage.

6. The cascaded adaptive digital I/O and analog signal acquisition circuit of claim 1, wherein the analog power supply comprises a 5V linear regulator 78M05 chip for converting a 24V supply voltage to a 5V supply voltage and a low noise LDO regulator SPX5205M5-L-3-3 chip for converting a 5V voltage to a 3.3V supply voltage.