CN109507627A - A kind of DC electronic transformer emulation mode - Google Patents
A kind of DC electronic transformer emulation mode Download PDFInfo
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- CN109507627A CN109507627A CN201910008737.0A CN201910008737A CN109507627A CN 109507627 A CN109507627 A CN 109507627A CN 201910008737 A CN201910008737 A CN 201910008737A CN 109507627 A CN109507627 A CN 109507627A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
- G01R35/02—Testing or calibrating of apparatus covered by the other groups of this subclass of auxiliary devices, e.g. of instrument transformers according to prescribed transformation ratio, phase angle, or wattage rating
Abstract
This application provides a kind of DC electronic transformer emulation modes, comprising: obtains initial samples data and sampled signal simulation configurations parameter that host computer issues；According to the output sampling rate in sampled signal configuration parameter, interpolation processing is fitted to initial samples data, obtains transition sampled data；According to the exceptionization parameter in sampled signal configuration parameter, data exception processing is carried out to transition sample data, obtains analog sampled data；Signal is controlled according to the transmission timing issued by FPGA circuitry, exports analog sampled data.The application is handled by carrying out further data exceptionization to the sampled data of acquisition; the output error code of DC electronic transformer digitized sampling, transmission frame losing and time-delay characteristics, solve the weak technical problem of the abnormal data special project detectability of existing joint debugging test method when more accurately simulating live joint debugging test.
Description
Technical field
This application involves testing equipment field more particularly to a kind of DC electronic transformer emulation modes.
Background technique
Direct current instrument transformer is primary equipment important in DC transmission system construction and operational process, is direct current control and protection system
Accurate reliable metrical information is provided, operational reliability and measurement accuracy are directly related to the safety of DC transmission system
Stable operation.In conjunction with the equipment development situation of current DC transmission system and the practical construction situation of Domestic Direct Current Transmission engineering,
Before converter station scene is put into operation, it is necessary to carry out systemic joint debugging to relevant device by testing tools such as DC electronic transformers and survey
Examination.
And traditional joint debugging test method mainly has Digital Simulation test method, passes through RTDS software simulation testing platform pair
Direct current system carries out whole station modeling, simulates the sampled data generated under all kinds of different operating conditions and all kinds of unusual service conditions, leads to
It crosses interface sub-module and is converted to the output of direct current sampling protocol, protect whole system to complete closed loop test as test object using control.But
It is to be led due to lacking the emulation for exporting error code, transmitting frame losing and time-delay characteristics to DC electronic transformer digitized sampling
The technical problem for having caused the abnormal data special project detectability of existing joint debugging test method weak.
Summary of the invention
This application provides a kind of DC electronic transformer emulation modes, for solving due to lacking to DC electronic
The output error code of mutual inductor digitized sampling, the emulation for transmitting frame losing and time-delay characteristics, result in existing joint debugging test method
The weak technical problem of abnormal data special project detectability.
This application provides a kind of DC electronic transformer emulation modes, comprising:
Obtain initial samples data and sampled signal simulation configurations parameter that host computer issues；
According to the output sampling rate in the sampled signal configuration parameter, interpolation is fitted to the initial samples data
Processing, obtains transition sampled data；
According to the exceptionization parameter in the sampled signal configuration parameter, data exception is carried out to the transition sample data
Change processing, obtains analog sampled data；
Signal is controlled according to the transmission timing that FPGA circuitry issues, exports the analog sampled data.
Preferably, the exceptionization parameter according in the sampled signal configuration parameter, to the transition sample data
Data exception processing is carried out, analog sampled data is obtained and specifically includes:
According to the exceptionization parameter in the sampled signal configuration parameter, extracted from the exceptionization parameter preset
Blocking rate, and the sampled point sending time of the transition sample data is adjusted according to the blocking rate, obtain analogue delay obstruction
Analog sampled data.
Preferably, the exceptionization parameter according in the sampled signal configuration parameter, to the transition sample data
Data exception processing is carried out, analog sampled data is obtained and specifically includes:
According to the exceptionization parameter in the sampled signal configuration parameter, extracted from the exceptionization parameter preset
Sampling interval rate, and sent and appointed according to the sampled point that the sampling interval rate skips corresponding number in the transition sample data
Business obtains analog sampling and loses analog sampled data a little.
Preferably, the exceptionization parameter according in the sampled signal configuration parameter, to the transition sample data
Data exception processing is carried out, analog sampled data is obtained and specifically includes:
According to the exceptionization parameter in the sampled signal configuration parameter, data are extracted from the exceptionization parameter and are set
Position parameter, and modified according to the dataset parameter to byte data specific in the transition sample data, it obtains
Simulate the analog sampled data of abnormality mark.
Preferably, before the output analog sampled data further include:
According to preset coding protocol, the analog sampled data is recompiled, is obtained corresponding with preset agreement
Analog sampled data.
Preferably, the fitting processing specifically:
In formula, Vn' it is conversion post-sampling value, VnFor original sample value, n is sampling sequence number, and R is crude sampling rate, and R ' is to turn
Change post-sampling rate.
Preferably, the triggering of the transmission timing control signal controls formula are as follows:
In formula, CntI is the cycle rate counter that output is interrupted, and CntS is the cycle rate counter of whole second, and n is to interrupt serial number, N
For interruption pulse number per second.
A kind of DC electronic transformer simulator provided by the present application, comprising: host computer, main processor circuit,
FPGA circuitry, clock synchronization circuit and signal output apparatus；
First communication ends of the main processor circuit and the host computer communicate to connect, wherein the primary processor electricity
Road is used to the initial samples data that the host computer received is sent being fitted processing and data exceptionization is processed, output
Analog sampled data；
Second communication ends of the main processor circuit and the first communication ends of the FPGA circuitry communicate to connect；
Second communication ends of the FPGA module and the clock synchronization circuit communicate to connect；
The third communication end of the signal input part of the signal output apparatus and the FPGA module communicates to connect, and being used for will
The coded sample data received are sent to equipment to be tested.
Preferably, the signal output apparatus specifically includes at least output interface all the way.
Preferably, the main processor circuit is specially MPC8247 embedded microprocessor.
Preferably, host computer is specially portable PC machine.
Preferably, the output interface is specially fiber optic data communication interface.
Preferably, the output interface is specially the serial optical fiber interface of HFBR 1414.
As can be seen from the above technical solutions, the application has the following advantages:
This application provides a kind of DC electronic transformer emulation modes, comprising: obtains initially adopting for host computer sending
Sample data and sampled signal simulation configurations parameter；According to the output sampling rate in the sampled signal configuration parameter, to described first
Beginning sampled data is fitted interpolation processing, obtains transition sampled data；According to the exception in the sampled signal configuration parameter
Change parameter, data exception processing is carried out to the transition sample data, obtains analog sampled data；It is sent out according to by FPGA circuitry
Transmission timing out controls signal, exports the analog sampled data.
The application is handled by carrying out further data exceptionization to the sampled data of acquisition, and more accurately simulation occurs
The output error code of DC electronic transformer digitized sampling, transmission frame losing and time-delay characteristics when joint debugging test, solve by
In the emulation for lacking the output error code to DC electronic transformer digitized sampling, transmitting frame losing and time-delay characteristics, result in
The weak technical problem of the abnormal data special project detectability of existing joint debugging test method.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of application without any creative labor, may be used also for those of ordinary skill in the art
To obtain other attached drawings according to these attached drawings.
Fig. 1 is a kind of structural representation of one embodiment of DC electronic transformer simulator provided by the present application
Figure；
Fig. 2 is a kind of process signal of one embodiment of DC electronic transformer emulation mode provided by the present application
Figure.
Specific embodiment
The embodiment of the present application provides a kind of direct current instrument transformer emulation mode, for solving due to lacking to DC electronic
The output error code of mutual inductor digitized sampling, the emulation for transmitting frame losing and time-delay characteristics, result in existing joint debugging test method
The weak technical problem of abnormal data special project detectability.
To enable present invention purpose, feature, advantage more obvious and understandable, below in conjunction with the application
Attached drawing in embodiment, the technical scheme in the embodiment of the application is clearly and completely described, it is clear that disclosed below
Embodiment be only some embodiments of the present application, and not all embodiment.Based on the embodiment in the application, this field
Those of ordinary skill's all other embodiment obtained without making creative work belongs to the application protection
Range.
Referring to Fig. 1, a kind of DC electronic transformer simulator provided by the present application, comprising: host computer 1, main place
Manage device circuit 2, FPGA circuitry 3, clock synchronization circuit 4 and signal output apparatus 5；
The first communication ends and host computer 1 of main processor circuit 2 communicate to connect, wherein main processor circuit 2 will be for that will connect
The initial samples data that the host computer 1 received is sent are fitted processing and data exceptionization processing, export analog sampled data；
Second communication ends of main processor circuit 2 and the first communication ends of FPGA circuitry 3 communicate to connect；
The second communication ends and clock synchronization circuit 4 of FPGA module communicate to connect；
The signal input part of signal output apparatus 5 and the third communication end of FPGA module communicate to connect, for that will receive
Coded sample data be sent to equipment to be tested.
It should be noted that the DC electronic transformer simulator of the present embodiment, synchronizes electricity by host computer 1, clock
Road 4, main processor circuit 2, FPGA circuitry 3, signal output apparatus 5 form.Host computer 1 realizes the sampling to DC transmission system
Value emulation and electronic mutual inductor simulated behavior export the digital quantity initial samples data based on DC electronic transformer, main
Processor circuit 2 is fitted interpolation and data exceptionization processing scheduling algorithm processing and application layer protocol group packet to test data,
Finally by FPGA module driving signal output circuit 5, simulation of the output for the analog DC electronic mutual inductor of joint debugging test
Sampled data.Wherein, clock of the clock synchronization circuit 4 for simulator is synchronous and internal interrupt controls.
More specifically, host computer 1 can select portable PC machine, by being based on LabView applied software development, pass through electricity
Ethernet interacts sampling test packet with simulator, realizes the simulation output function of direct current instrument transformer sampled data.
Sampling test data can be generated based on the electric system simulation module of matlab/simulink, by defeated to direct current
Electric system modeling and simulating obtains under normal operation or malfunction, and the sampling of sampling node emulates data in system.Host computer 1
Data file is emulated by importing sampled value and is converted to the sampling output of corresponding DC electronic transformer, realizes that direct current control is protected
The temporary system emulation testing of system.
Host computer 1 can configure the direct current amplitude of electronic mutual inductor output, harmonic frequency content phase；Configure transient process
Each sequence design parameter；The frame loss rate of arrangement abnormalities state, the displacement of mistake mark, the bit error rate；Configure output protocol type and sample rate
Deng, it is sampled and is exported by the transient state of stable state sampling output or status switch mode, the sampling biography of analog DC electronic mutual inductor
Become characteristic.
The clock synchronization circuit 4 of the present embodiment uses CPLD-XC95288XL uniprocessor, mainly completes 1PPS, IRIG-B
Code message adaptive reception and processing, and can accurately control 1PPS second pulse signal and IRIG-B code synchronizable optical, electric pulse letter
Number output.Its clock signal is provided by High Accuracy Constant Temperature crystal oscillator OCXO50.OCXO50 constant-temperature crystal oscillator operating temperature is -40 to 85
Degree, the temperature drift characteristic less than 1ppb, the low phase noise of -160dBc/1KHz, the low aging of maximum 10ppb/year ensure that
The accuracy of module timing control and the stability of long-term work.
The main processor circuit 2 of the present embodiment is embedded in using PowerPC as core using the MPC8247 of Freescale company
Microsever, the processor belong to PowerQUICC II series, the kernel comprising one based on PowerPC MPC603e, and
One communication process kernel CPM.Double-core design has powerful processing capacity and higher integrated level, reduces the composition of system
Expense simplifies the design of circuit board, reduces power consumption.The real-time transmission of transient state step data controls and back production is all by master control
CPU is completed.
PowerPC complete system initialization communicated with self-test, host computer 1, data prediction, frame data tissue, when going out
Sequence calculates and the work such as Refresh Data.Primary processor receives the test configurations parameter that host computer 1 issues, according to transient state/stable state
Type and data sampling frequency obtain real time data by calculating or sampling, and cooperate frame losing, error code, mistake mark, send association
The export control policies such as view, analog DC electronic mutual inductor export sampled data.
The FPGA processor of the present embodiment uses the Spartan3 series of products XC3S1500 of Xilinx, includes 1,500,000
A system door, 32 special multipliers, 4 digital dock management modules, logical resource is abundant, and the speed of service is fast.PFPGA is in height
Under the control of accuracy clock module, when completing the coding-control output of DC electronic transformer digitized sampling agreement and sending
Sequence control, cooperation main control module realizes the simulation of the anomalous modes such as frame losing, the displacement of mistake mark, error code, and driving signal output circuit 5 is defeated
Sampled optical signals out
The signal output apparatus 5 of the present embodiment is multiplex roles parallel output, can output multi-channel direct current instrument transformer emulation simultaneously
Data.Specifically, HFBR1414 serial optical fiber sending device of the signal output apparatus 5 of the present embodiment using Avago company, tool
The optical signal transmission ability of standby high speed, the serial data that can meet under most baud rates send demand.
The above are a kind of detailed description of one embodiment of DC electronic transformer simulator provided by the present application,
It is below a kind of detailed description of the embodiment of DC electronic transformer emulation mode provided by the present application.
Referring to Fig. 2, this application provides a kind of DC electronic transformer emulation modes, comprising:
201, initial samples data and sampled signal simulation configurations parameter that host computer 1 issues are obtained.
It should be noted that establishing DC transmission system and DC electronic transformer by host computer 1 before on-test
Simulation model obtains the direct current system sampling emulation data of DC electronic transformer output, prepares subsequent output.
The SIMULINK module that MATLAB software can be used builds DC transmission system and DC electronic transformer emulates
Model, simulation step length 2us, the real-time sampling Value Data of exportable high sampling rate.Emulation sampling node is placed in converter station
The practical measuring point of DC current transformer can distinguish simulation output stable state and sample or exchange system with DC line under malfunction
The sample information of system.
202, according to the output sampling rate in sampled signal configuration parameter, initial samples data are fitted at interpolation
Reason, obtains transition sampled data.
It should be noted that the sampled signal configuration parameter that steps for importing 201 obtains, reads in sampled signal configuration parameter
Configuration information in simulated mutual inductor sampling channel real output value.
According to the reality output sample rate of simulated direct current instrument transformer, interpolation calculation is fitted to initial samples data,
And mutual inductor normal delay parameter is compensated, the transition sample data for meeting actual samples link transmission requirements are obtained, are adopted
With following fitting formula:
In formula, Vn' it is conversion post-sampling value, VnFor original sample value, n is sampling sequence number, and R is crude sampling rate, and R ' is to turn
Change post-sampling rate.
203, according to the exceptionization parameter in sampled signal configuration parameter, transition sample data are carried out at data exception
Reason, obtains analog sampled data.
It should be noted that being carried out according to the way of output of direct current instrument transformer digitized sampling value to process sampling data
Different normalizing treatment, including delay obstructive root canal, sampling lose control and abnormality mark control.
Postpone the practical sending time that obstructive root canal obtains message, by preconfigured blocking rate, adjusts specified sampling
The sending instant of point, when simulation based on digital sampling is sent, sampling caused by postponing due to interrupt schedule sends adhesion.
Or
Sampling loses control and stops paying out space-number according to the sampled data of setting, skips specified sampled point and sends interruption, mould
The situation stopped paying out is sampled when quasi- processor severe resource consumption.
Or
Abnormality mark control changes the status flag of direct current instrument transformer output protocol, according to the offset for sampling message
Specified bytes data are modified, it may be verified that the sampling exception handling being devices under in location.
204, according to preset coding protocol, analog sampled data is recompiled, is obtained corresponding with preset agreement
Analog sampled data.
It should be noted that believing in hardware driving bottom sampling by the sample code requirement of simulated direct current instrument transformer
Breath is encoded.DC electronic transformer is mainly encoded using graceful code, and simulator is treated according to different coding baud rates
The sample data frames of transmission are converted by turn by byte, and until a frame sampling data are all sent, then lasting output is idle
Position coding, until the transmission interruption of new frame sampling data starts.
Specifically, all sampled points are arranged in order, according to protocol type dynamic regulation data set length and sampled value
Channel map, agreement output while additional starting character, sample counter and cyclic redundancy check, guarantee the stabilization of high speed data transfer
Property.Data transmission procedure and CRC check concurrent process are handled, can be based on the Pipeline control mode of FPGA, at sacrifice
The concurrent working that device resource realizes multimode is managed, module is mutually indepedent when running with intermodule, occupies internal hardware resources parallel.
After all sampling data transmittings, the synchronous CRC check for realizing transmission data is calculated, the end as the frame sampling data
Byte.
The superior coded treatment performance of FPGA circuitry 3 is utilized simultaneously, is recoded by turn by sampled value, is realized to different numbers
Mechanism is uniformly processed in word sampling protocol, and the intercommunication for improving agreement between test equipment and test system is compatible, can be compatible with
The DC electronic transformer of converter station scene mainstream samples output protocol at present.Reduce the uncertainty of field adjustable.
205, signal is controlled according to the transmission timing that FPGA circuitry 3 issues, exports analog sampled data.
It should be noted that DC electronic transformer exports digitized sampled value, output accuracy by message when
Domain discretization error determines that therefore, it is necessary to accurately control the data output time in each group sampled value channel in simulator.
The high precision clock pulse for cooperating clock synchronization circuit 4 to export by fpga chip, it is real to each signal output apparatus 5
The control of row hardware level.By the actual sample rate of mutual inductor, each whole time second is divided into N number of output interruption pulse, effective
Error range in the cycle rate counter of interruption pulse is divided into several gears, by actual sampling interval duration to each defeated
The cycle rate counter interrupted out is adjusted, and guarantees that the period distances of adjacent interruption are accurate and will not jump, it is as follows to adjust formula:
Wherein: CntI is the cycle rate counter that output is interrupted, and CntS is the cycle rate counter of whole second, and n is to interrupt serial number, N
For interruption pulse number per second.
The application is handled by carrying out further data exceptionization to the sampled data of acquisition, and more accurately simulation occurs
The output error code of DC electronic transformer digitized sampling, transmission frame losing and time-delay characteristics when joint debugging test, solve by
In the emulation for lacking the output error code to DC electronic transformer digitized sampling, transmitting frame losing and time-delay characteristics, result in
The weak technical problem of the abnormal data special project detectability of existing joint debugging test method.
More than, above embodiments are only to illustrate the technical solution of the application, rather than its limitations；Although referring to aforementioned reality
Example is applied the application is described in detail, those skilled in the art should understand that: it still can be to aforementioned each
Technical solution documented by embodiment is modified or equivalent replacement of some of the technical features；And these are modified
Or replacement, the spirit and scope of each embodiment technical solution of the application that it does not separate the essence of the corresponding technical solution.
Claims (7)
1. a kind of DC electronic transformer emulation mode characterized by comprising
Obtain initial samples data and sampled signal simulation configurations parameter that host computer issues；
According to the output sampling rate in the sampled signal configuration parameter, the initial samples data are fitted at interpolation
Reason, obtains transition sampled data；
According to the exceptionization parameter in the sampled signal configuration parameter, the transition sample data are carried out at data exception
Reason, obtains analog sampled data；
Signal is controlled according to the transmission timing issued by FPGA circuitry, exports the analog sampled data.
2. the method according to claim 1, wherein the exception according in the sampled signal configuration parameter
Change parameter, data exception processing carried out to the transition sample data, analog sampled data is obtained and specifically includes:
According to the exceptionization parameter in the sampled signal configuration parameter, preset obstruction is extracted from the exceptionization parameter
Rate, and the sampled point sending time of the transition sample data is adjusted according to the blocking rate, obtain the mould of analogue delay obstruction
Quasi- sampled data.
3. the method according to claim 1, wherein the exception according in the sampled signal configuration parameter
Change parameter, data exception processing carried out to the transition sample data, analog sampled data is obtained and specifically includes:
According to the exceptionization parameter in the sampled signal configuration parameter, preset sampling is extracted from the exceptionization parameter
Interval rate, and task is sent according to the sampled point that the sampling interval rate skips corresponding number in the transition sample data, it obtains
Analog sampled data a little is lost to analog sampling.
4. the method according to claim 1, wherein the exception according in the sampled signal configuration parameter
Change parameter, data exception processing carried out to the transition sample data, analog sampled data is obtained and specifically includes:
According to the exceptionization parameter in the sampled signal configuration parameter, dataset ginseng is extracted from the exceptionization parameter
Number, and specific byte data is modified in the transition sample data according to the dataset parameter, obtains simulating different
The analog sampled data often indicated.
5. the method according to claim 1, wherein before the output analog sampled data further include:
According to preset coding protocol, the analog sampled data is recompiled, obtains mould corresponding with preset agreement
Quasi- sampled data.
6. the method according to claim 1, wherein the fitting is handled specifically:
In formula, Vn' it is conversion post-sampling value, VnFor original sample value, n is sampling sequence number, and R is crude sampling rate, and R ' is after converting
Sample rate.
7. the method according to claim 1, wherein the triggering of transmission timing control signal controls formula
Are as follows:
In formula, CntI is the cycle rate counter that output is interrupted, and CntS is the cycle rate counter of whole second, and n is to interrupt serial number, and N is every
The interruption pulse number of second.
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| CN111337781A (en) * | 2020-03-31 | 2020-06-26 | 国网安徽省电力有限公司电力科学研究院 | Sampling abnormity control decoupling direct current protection field test system and method |
| CN111983379A (en) * | 2020-07-30 | 2020-11-24 | 国网安徽省电力有限公司电力科学研究院 | Direct-current line traveling wave protection field test method and system |
| CN114089907A (en) * | 2021-11-09 | 2022-02-25 | 国网江西省电力有限公司电力科学研究院 | Centralized direct-current sampling value data conversion method and device |
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| CN109507627B (en) | 2021-03-12 |
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