CN109507624B - Capacitor simulator and method for simulating capacitor - Google Patents
Capacitor simulator and method for simulating capacitor Download PDFInfo
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- CN109507624B CN109507624B CN201811318954.1A CN201811318954A CN109507624B CN 109507624 B CN109507624 B CN 109507624B CN 201811318954 A CN201811318954 A CN 201811318954A CN 109507624 B CN109507624 B CN 109507624B
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- G01R35/005—Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references
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Abstract
The invention relates to a capacitance simulator and a method for simulating a capacitor, which are characterized in that: the circuit comprises a standard capacitor Cref, an amplifier circuit, a D/A converter, a follower A1, an inverter A4 and a controller. The scheme of the invention realizes that the continuously adjustable output capacitor can be realized only by using a limited number of standard capacitors, and can be programmed, the output precision is determined according to the precision of the selected D/A converter, and the higher the digit of the converter is, the higher the precision of the output capacitor is. The program-controlled table look-up algorithm provided by the text is beneficial to CPU calculation operation and flexibly realizes user setting.
Description
Technical Field
The invention belongs to electronic components, and particularly relates to a capacitance simulator and a method for simulating a capacitor.
Background
In engineering technology, the application of the capacitor is very wide, the capacitor standard is an important standard in an alternating current impedance value transmission system, common capacitor standards are single-value capacitor standards, the size is large, the value range is narrow, and the continuous adjustability of the capacitor standard is basically unrealistic if the capacitor standard is supposed to be achieved through the capacitor standards. The problem of the current situation is prominent in the metering process, the metering efficiency is greatly influenced, and the current metering requirement can not be met. The capacitance standard is a parameter in the multifunctional calibration source, and due to the numerous parameters of the equipment, the circuit of the capacitance standard part needs to be small in size, simple to control and easy to integrate.
Disclosure of Invention
In view of the above circumstances, the present invention provides a capacitor simulator capable of solving the above problems, wherein when a voltage is applied to the two plates of a capacitor, equal amounts of positive and negative charges are respectively accumulated on the two plates to generate a current. The invention designs the analog core circuit to realize the output capacitor with wide range and continuous adjustment based on the relation between the capacitive reactance of the output capacitor and the current and voltage in unit time. The invention mainly provides two capacitance conversion modes of amplification and reduction, and the two modes can be selected through a program control switch. And the coarse adjustment and the fine adjustment are carried out for two-stage adjustment, so that the adjustment of the amplification factor of the circuit is realized. The method can realize the use of the least common standard capacitor, output the widest range of continuously adjustable output capacitive reactance, reduce the circuit volume and be conveniently integrated in a metering standard source or a common circuit. Specifically, the invention provides a capacitance simulator, which is characterized in that two capacitance conversion modes can be selected, and a circuit comprises: the circuit comprises a standard capacitor Cref, an amplifier circuit, a D/A converter, a follower A1, an inverter A4 and a controller.
Further, it is characterized in that: the number of the standard capacitors Cref is multiple.
Further, it is characterized in that: the standard capacitor Cref is an external standard capacitor.
Further, it is characterized in that: the follower A1 realizes the buffer isolation function for the follower, the input end is connected with the non-grounding end of the output capacitor Cout, the output end of the follower A1 is connected with the amplifying circuit, the output of the amplifier circuit is connected with the D/A converter, and the output of the D/A converter is connected with the standard capacitor Cref.
Further, it is characterized in that: the amplifier circuit has two modes, and can be selected through a switch K1, wherein one mode is a capacitance amplification mode; one path is a reduced capacitance mode.
Further, it is characterized in that: and the standard capacitor Cref is connected with the positive input end of the follower.
Further, it is characterized in that: an inverter is arranged between the output of the D/a converter and the reference capacitance Cref and it is selectable by means of a second switch K2 whether the inverter is switched into the circuit or not.
Further, it is characterized in that: there is also a third switch responsible for selecting a plurality of standard capacitances.
The invention also provides a method for simulating the capacitor, which is characterized by comprising the following steps: the method is realized by adopting the capacitance simulator of any one of the above.
Further, it is characterized in that: the controller is an FPGA controller and is responsible for analyzing and calculating the control coefficient of the D/A controller and the connection mode of the first switch K1, the second switch K2 and the third switch K3.
The invention realizes continuous adjustable output capacitance by two-stage adjustment, realizes coarse adjustment by two conversion modes, and realizes fine adjustment by controlling the D/A converter. Finally, the output capacitor can be continuously adjusted only by using a limited number of standard capacitors and can be controlled in a program mode, the output precision is determined according to the precision of the selected D/A converter, and the higher the digit of the converter is, the higher the precision of the output capacitor is. The program-controlled table look-up algorithm provided by the text is beneficial to CPU calculation operation and flexibly realizes user setting.
Drawings
FIG. 1 is a schematic diagram of an analog capacitance simulator of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, the following detailed description of the invention is provided in conjunction with the accompanying drawings and its implementation method.
As shown in fig. 1, the capacitance simulator of the present invention includes: a standard capacitor Cref, an amplifier circuit, a D/A converter, a follower A1, an inverter A4 and an embedded controller.
The follower a1 realizes a buffer isolation function for the follower, an input terminal of the follower a1 is connected to the non-ground terminal of the output capacitor Cout, and an output terminal of the follower a1 is connected to the amplifying circuit. The amplifying circuit has two circuits representing two modes, namely a capacitance amplification mode and a capacitance reduction mode, and different modes are selected through a single-pole double-throw switch K1, specifically, the first circuit comprises an amplifier A2, a voltage division resistor R1 and a voltage division resistor R2, wherein the connection point of R1 and R2 is connected to the negative input end of the amplifier A2, and the output end of the amplifier A2 is connected to the other end of the R2. The first circuit comprises an amplifier A3, a voltage-dividing resistor R3 and a voltage-dividing resistor R4, wherein the connection point of R3 and R4 is connected to the negative input end of the amplifier A3, and the output end of the amplifier A3 is connected with the other end of the R4. The single-pole double-throw switch K1 can be selectively connected with the output end of A2 or A3. The other end of the knife double-throw switch K1 is connected with a D/A converter, the output of the D/A converter is divided into two paths to be connected with a standard capacitor Cref, one path is connected with an inverter A4, and the two paths are selected through a second switch K2. The standard capacitor Cref is two or more than one Cref1-Crefn, can be selected through a third switch K3, and is connected with the positive input end of the follower.
In the invention the reduced mode gain of amplifier A3 was-0.99 and the reduced amplification mode gain of amplifier A2 was-10. Its output signal is output to the reference input of a D/a converter which, under system control, converts the output voltage required. The second switch K2 is used to select whether to connect the inverter, not connecting the inverter when the gain circuit is in the reduction mode, and connecting the inverter when the gain circuit is in the amplification mode. Cref (1) -Cref (n) are n kinds of selectable standard capacitors, different capacitance values are selected through control of a switch K3, different measuring ranges are selected according to the different capacitance values, and for example, 10nF, 10 muF, 10mF and the like can be selected as the standard capacitors.
The voltage at two ends of the output capacitor is Uo, and the current at two ends is Io. The voltage across the standard capacitor is Uc and the current across the capacitor is Io.
The principle of the inventive solution is explained below with reference to the drawings:
1) derivation of output capacitance calculation formula
The element characteristics of the capacitive element are an algebraic relationship between the circuit physical quantity charge q and the voltage u.
q＝C*u；…………………(1)
The scheme is constant current charging, and the relationship between charge and current is as follows:
the charging start time is t1, and the cutoff time is t 2. The formula (2) can be used for obtaining:
q＝i*ΔT；…………………(3)
wherein, the delta T is (T2-T1), and the formula (3) is substituted into the formula (1) to obtain the formula:
in the above formula, q is the physical charge amount of the circuit, C is the capacitance value, u is the voltage of the capacitor, i is the current of the capacitor, T1 is the charge start time, T2 is the charge stop time, and Δ T is (T2-T1).
2) Derivation of output capacitance conversion formula in the circuit
Cout is the output capacitance, Uo is the voltage across the capacitance, Io is the current across the capacitance. From equation (4) derived above, one can derive:
cref is the standard capacitance, Uc is the voltage across the capacitance, Io is the current across the capacitance.
(7) V (8), obtaining:
Cout/Cref＝Uc/Uo；…………………(7)
3) gain control circuit
The gain control circuit is divided into two paths, one path is a capacitance amplification mode, and the other path is a capacitance reduction mode. The system control switch selects different amplification circuits. In the figure, R1, R2, R3 and R4 are voltage dividing resistors respectively, control the amplification factor of the output circuit, and f1 is the amplification factor of the amplification circuit. The formula in the amplification pattern is as follows:
f1＝‐R1/R2；
in the reduced capacitance mode, the formula is as follows:
f1＝‐R3/R4；
in the present invention, the f1 reduction factor was-0.99 and the amplification factor was-10. The fine adjustment of the output capacitance is completed by a D/A converter, and the fine adjustment coefficient f2 is D/2NWherein N is the data bit number of the D/A converter, and the output range is (0-1).
The output capacitance conversion formula is as follows:
Ui＝f1×f2×Uo；…………………(8)
Uc＝Uo‐Ui＝Uo–f1×f2×Uo＝Uo*(1‐f1×f2)；…………………(9)
substituting (9) into (8) can obtain the output capacitance conversion formula:
Cout＝(1‐f1×f2)×Cref；…………………(10)
4) control algorithm of analog capacitor
The controller in the invention preferably adopts FPGA as the controller, and the control coefficient of the D/A controller and the connection mode of the K1, K2 and K3 switches are analyzed and calculated according to the required capacitance value input by a user. Preferably, the FPGA controller implements the control algorithm by means of a table lookup.
For example, if the output capacitance value input by the user is 1nF, the specific steps are as follows:
from a table lookup, the 1nF output capacitance can select the standard capacitance 10nF capacitance conversion mode to the reduced mode, so the K1 switch selects the reduced mode and the K3 switch selects the capacitance 10 nF.
The conversion value of the D/a converter is calculated according to equation (10), where Cout is 1nF, f is-0.99, Cref is 10, and N is 16. D is 59604 obtained through calculation, and the control bus is set to be 59604 through the FPGA.
5) Analog capacitance coverage analysis
The gain reduction coefficient of the invention is-0.99, when the gain reduction circuit is selected to be closed, because the D/A is selected to be a 16-bit reverse output device, the K2 switch is selected not to be connected with an inverter, and the formula (10) is simplified as follows:
Cout＝(1‐0.99×f2)×Cref；
wherein f is more than or equal to 0 and less than or equal to 1, so that Cout can cover the range from (0.01-1) xCref;
the gain amplification coefficient of the invention is-10, when the amplification gain selection circuit is closed, the K2 switch is selectively connected with the inverter, and because the D/A is selected to be a 16-bit reverse output device, the formula (10) is simplified as follows:
Cout＝(1+10×f2)×Cref；
wherein f is more than or equal to 0 and less than or equal to 1, so that Cout can cover the range from (1-11) multiplied by Cref;
based on the above calculations, the standard capacitance and coverage range selected in the present invention are as follows:
as can be seen from the above table, only three standard capacitors are selected to cover the output capacitance range from 0.1nF to 110 mF.
6) Capacitance standard source error analysis
The output error of the standard source part of the capacitor is mainly determined by the error introduced by the standard capacitor and the distribution parameters of the circuit, and the error introduced by other parts in the circuit can be ignored relative to the first two errors.
By purchasing the vacuum packaging capacitor subjected to long-time aging examination, the annual change rate of the standard capacitor can be ensured to be less than 0.1%, errors introduced by distribution parameters can be controlled within 0.1% through careful circuit board layout and wiring design, and therefore the output error of the standard source part of the capacitor can be controlled to be about 0.2%.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention. Furthermore, although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.
Claims (3)
1. A capacitance simulator, characterized by: the circuit comprises a standard capacitor Cref, an amplifier circuit, a D/A converter, a follower A1, an inverter A4 and a controller;
the number of the standard capacitors Cref is multiple; the standard capacitor Cref is an external standard capacitor; the follower A1 realizes the buffer isolation effect, the input end of the follower A1 is connected with the non-grounding end of the output capacitor Cout, the output end of the follower A1 is connected with the amplifier circuit, the output of the amplifier circuit is connected with the D/A converter, and the output of the D/A converter is connected with the standard capacitor Cref; the two amplifier circuits can be selected through a single-pole double-throw switch K1, one of the two amplifier circuits is in a capacitance amplification mode and comprises an amplifier A2, a voltage division resistor R1 and a voltage division resistor R2, wherein the connection point of the voltage division resistor R1 and the voltage division resistor R2 is connected to the negative input end of an amplifier A2, and the output end of the amplifier A2 is connected to the other end of the voltage division resistor R2; the other is in a capacitance reduction mode and comprises an amplifier A3, a voltage-dividing resistor R3 and a voltage-dividing resistor R4, wherein the connection point of the voltage-dividing resistor R3 and the voltage-dividing resistor R4 is connected to the negative input end of the amplifier A3, and the output end of the amplifier A3 is connected to the other end of the voltage-dividing resistor R4; the single-pole double-throw switch K1 can be selectively connected with the output end of the amplifier A2 or the output end of the amplifier A3, and the other end of the single-pole double-throw switch K1 is connected with the D/A converter;
the output of the D/A converter is divided into two paths to be connected with the standard capacitor Cref, one path is connected with the inverter A4, the two paths are selected through the second switch K2, when the amplifying circuit is in a capacitance reduction mode, the output of the D/A converter is not connected with the inverter A4, and when the amplifying circuit is in a capacitance amplification mode, the output of the D/A converter is connected with the inverter A4.
2. The capacitance simulator of claim 1, wherein: the reference capacitor Cref is connected to the positive input of the follower a 1.
3. A method of simulating a capacitor, comprising: this is achieved with a capacitance simulator as claimed in claim 1 or 2.
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| CN201811318954.1A CN109507624B (en) | 2018-11-07 | 2018-11-07 | Capacitor simulator and method for simulating capacitor |
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| CN113050016B (en) * | 2021-06-01 | 2021-08-27 | 中国测试技术研究院电子研究所 | Four-terminal method compensation capacitance simulator |
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| CN202026282U (en) * | 2011-03-30 | 2011-11-02 | 大连交通大学 | Numerical control gain direct current amplifier |
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| CN105115535B (en) * | 2015-09-25 | 2017-06-09 | 成都华太测控技术有限公司 | The analogue means of capacitance sensor |
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