CN109495418A - Ofdm signal synchronous method, device and computer readable storage medium - Google Patents
Ofdm signal synchronous method, device and computer readable storage medium Download PDFInfo
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- CN109495418A CN109495418A CN201811608287.0A CN201811608287A CN109495418A CN 109495418 A CN109495418 A CN 109495418A CN 201811608287 A CN201811608287 A CN 201811608287A CN 109495418 A CN109495418 A CN 109495418A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
- H04L27/2657—Carrier synchronisation
Abstract
The invention discloses a kind of ofdm signal synchronous method, device and computer readable storage mediums, belong to field of communication technology.This method comprises: carrying out frequency-domain transform to signal is received, obtain receiving signal sequence；Docking receives signal sequence and carries out delay relevant treatment, obtains the first sequence of correlation values；Delay relevant treatment is carried out to the first sequence of correlation values, obtains the second sequence of correlation values；It carries out signal based on the second sequence of correlation values just to synchronize, to determine just sync bit；Based on the reception signal sequence after local synchronization sequence and the just sync bit, timing synchronization position is determined.This method can improve the synchronous accuracy of signal with the influence of DC-offset correction and carrier wave frequency deviation, and the synchronous success rate of the signal under Low SNR can be improved.
Description
Technical field
The present invention relates to field of communication technology, in particular to a kind of OFDM (Orthogonal Frequency Division
Multiplexing, orthogonal frequency division multiplexing) signal synchronizing method, device and computer readable storage medium.
Background technique
In the wireless communication system based on OFDM system, the data progress that can be difficult without accurately synchronization to transmission can
It is replied by ground, therefore, ofdm signal is synchronous to be played a crucial role in system design.
Currently, common ofdm signal synchronous method includes: to carry out a cross-correlation using the collection of letters number of local synchronization sequence docking
Processing receives signal autocorrelation processing, and search peak is in correlated results to determine sync bit.It receives signal and receives load
Wave frequency partially and direct current biasing influence, cause the accuracy of ofdm signal Timing Synchronization and success rate lower.
Summary of the invention
It, can be with the embodiment of the invention provides a kind of ofdm signal synchronous method, device and computer readable storage medium
Improve the accuracy and success rate of ofdm signal Timing Synchronization.The technical solution is as follows:
On the one hand, the embodiment of the invention provides a kind of ofdm signal synchronous method, which comprises
Frequency-domain transform is carried out to signal is received, obtains receiving signal sequence；
Delay relevant treatment is carried out to the reception signal sequence, obtains the first sequence of correlation values；
Delay relevant treatment is carried out to first sequence of correlation values, obtains the second sequence of correlation values；
It carries out signal based on second sequence of correlation values just to synchronize, to determine just sync bit；
Based on the reception signal after local synchronization sequence and the just sync bit, timing synchronization position is determined.
In an implementation of the embodiment of the present invention, same at the beginning of the progress signal based on second sequence of correlation values
Step, to determine just sync bit, comprising:
As unit of setting length, the corresponding correlation window function of second sequence of correlation values of multiple units is calculated separately
Rate and delay correlation window power；
It is related to the delay according to the corresponding correlation window power of second sequence of correlation values of each unit
Window power determines just sync bit.
Further, the corresponding correlation window power of second sequence of correlation values according to each unit and
The delay correlation window power determines just sync bit, comprising:
By the corresponding delay correlation window power of second sequence of correlation values of each unit and the associated window
The ratio of mouth power is compared with predetermined threshold value；
If the corresponding ratio of second sequence of correlation values of continuous N number of unit is all larger than predetermined threshold value, by continuous N
The end position of corresponding second sequence of correlation values of n-th ratio in a ratio is determined as just sync bit.
In an implementation of the embodiment of the present invention, described based on local synchronization sequence and described just after sync bit
The reception signal, determine timing synchronization position, comprising:
The direct current biasing of the reception signal after eliminating the just sync bit；
To going the reception signal after removing DC bias to carry out delay correlation, third sequence of correlation values is obtained；
The third sequence of correlation values is quantified, quantized result is obtained；
Matched filtering is carried out to the quantized result using the local synchronization sequence, obtains matched filtering result；
Peak value searching is carried out to the matched filtering result, to determine timing synchronization position.
Optionally, the method also includes:
Binary phase shift keying BPSK modulation is carried out to random sequence, obtains modulation sequence；
Up-sampling interpolation processing is carried out to the modulation sequence, obtains interpolating sequence；
Time domain transformation is carried out to interpolating sequence, obtains local synchronization sequence.
On the other hand, the embodiment of the invention also provides a kind of ofdm signal synchronizing device, described device includes:
Frequency-domain transform module, for obtaining receiving signal sequence to signal progress frequency-domain transform is received；
Correlation module obtains the first sequence of correlation values for carrying out delay relevant treatment to the reception signal sequence；And
Delay relevant treatment is carried out to first sequence of correlation values, obtains the second sequence of correlation values；
First synchronization module is just synchronized for carrying out signal based on second sequence of correlation values, to determine just sync bit；
SNR detection module, for based on local synchronization sequence and the just reception signal after sync bit, really
Determine timing synchronization position.
In an implementation of the embodiment of the present invention, the just synchronization module, comprising:
Power calculation submodule, for as unit of setting length, calculating separately second correlation of multiple units
The corresponding correlation window power of sequence and delay correlation window power；
Just synchronous submodule, for the corresponding correlation window function of second sequence of correlation values according to each unit
Rate and the delay correlation window power determine just sync bit.
In an implementation of the embodiment of the present invention, the SNR detection module, comprising:
Direct current biasing eliminates submodule, for eliminating the direct current biasing for receiving signal；
Relevant sub-module, for obtaining third phase to going the reception signal after removing DC bias to carry out delay correlation
Close value sequence；
Quantify submodule and obtains quantized result for quantifying to the third sequence of correlation values；
Submodule is filtered, for carrying out matched filtering to the quantized result using the local synchronization sequence, is obtained
With filter result；
Peak value searching submodule carries out peak value searching to the matched filtering result, to determine timing synchronization position.
Optionally, described device further include:
Synchronizing sequence generation module obtains modulation sequence for carrying out binary phase shift keying BPSK modulation to random sequence
Column；Up-sampling interpolation processing is carried out to the modulation sequence, obtains interpolating sequence；Time domain transformation is carried out to interpolating sequence, is obtained
Local synchronization sequence.
On the other hand, the embodiment of the invention also provides a kind of ofdm signal synchronizing device, described device includes: processing
Device；Memory for storage processor executable instruction；Wherein, the processor is configured to being stored in for execution described
Executable instruction in processor, to realize foregoing ofdm signal synchronous method.
On the other hand, the embodiment of the invention also provides a kind of computer readable storage mediums, when described computer-readable
When instruction in storage medium is executed by the processor of ofdm signal synchronizing device, enable the ofdm signal synchronizing device
Execute foregoing ofdm signal synchronous method.
Technical solution provided in an embodiment of the present invention has the benefit that
Frequency domain conversion is carried out with the influence of DC-offset correction, then to the reception letter in frequency domain by will first receive signal
It is related that number sequence carries out delay, so as to eliminate the influence of carrier wave frequency deviation, and then synchronous accurate of ofdm signal can be improved
Degree, and the synchronous success rate of the signal under Low SNR can be improved.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is application scenarios schematic diagram provided in an embodiment of the present invention；
Fig. 2 is a kind of flow chart of ofdm signal synchronous method provided in an embodiment of the present invention；
Fig. 3 is a kind of flow chart of ofdm signal synchronous method provided in an embodiment of the present invention；
Fig. 4 is a kind of structural schematic diagram of ofdm signal synchronizing device provided in an embodiment of the present invention；
Fig. 5 shows the structural block diagram of the ofdm signal synchronizing device of an illustrative embodiment of the invention offer.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
Fig. 1 is application scenarios schematic diagram provided in an embodiment of the present invention.Referring to Fig. 1, which includes transmitting terminal 10
With receiving end 20.Transmitting terminal 10 is connected with receiving end 20 by the wireless communication technique based on OFDM.Transmitting terminal 10 and receiving end
20 can be mobile terminal, such as mobile phone, laptop etc..
Transmitting terminal 10 and the communication process of receiving end 20 can be such that the synchronous sequence of the addition in sending signal of transmitting terminal 10
Column, are then sent to receiving end 20, which can be used as auxiliary sequencel and carry in sending signal.In general, the auxiliary
Sequence is sent before data-signal (carrying the signal of valid data), that is, auxiliary sequencel is first sent when sending signal then again
Send data-signal.After receiving end 20 receives signal, it is same that signal is first carried out using the signal that local synchronization sequence docking receives
Then step handle such as channel estimation, encoding and decoding to valid data again to determine the starting position of valid data.
Fig. 2 is a kind of flow chart of ofdm signal synchronous method provided in an embodiment of the present invention.The ofdm signal side of synchronization
Method can be executed by the receiving end 20 in Fig. 1.Referring to fig. 2, which includes:
Step 101: carrying out frequency-domain transform to signal is received, obtain receiving signal sequence.
Wherein, frequency-domain transform can be FFT (Fast Fourier Transformation, Fast Fourier Transform (FFT)).
Step 102: docking receives signal sequence and carries out delay relevant treatment, obtains the first sequence of correlation values.
Step 103: delay relevant treatment being carried out to the first sequence of correlation values, obtains the second sequence of correlation values.
Step 104: signal being carried out based on the second sequence of correlation values and is just synchronized, to determine just sync bit.
Step 105: based on the reception signal sequence after local synchronization sequence and first sync bit, determining Timing Synchronization position
It sets.
In embodiments of the present invention, frequency domain conversion is carried out with the influence of DC-offset correction, so by will first receive signal
Delay correlation is carried out to the reception signal sequence in frequency domain afterwards, so as to eliminate the influence of carrier wave frequency deviation, and then can be improved
The synchronous accuracy of ofdm signal, and the synchronous success rate of the signal under Low SNR can be improved.
Fig. 3 is a kind of flow chart of ofdm signal synchronous method provided in an embodiment of the present invention.Believe referring to Fig. 3, the OFDM
Number synchronous method can be executed by the receiving end 20 in Fig. 1, which includes:
Step 201: generating and save local synchronization sequence.
The step 201 may include:
The first step carries out BPSK modulation to random sequence, obtains modulation sequence；
Wherein, random sequence can be generated by matlab.Random sequence is made of 0 and 1, and the length of random sequence can root
According to needing to be arranged, illustratively, can be 64 random sequences, i.e., length be 64bit random sequence.
Further, BPSK modulation is carried out to random sequence and refers to that indicate 0 use -1,1 use+1 indicates.
Second step carries out up-sampling interpolation processing to modulation sequence, obtains interpolating sequence.
Illustratively, the multiple for up-sampling interpolation processing can be 16, carry out 16 times of up-samplings to 64 random sequences
After interpolation processing, 1024 point interpolation sequences are obtained.
Wherein, it up-samples interpolation processing for N times, refers to and be inserted into N-1 after each point of the sequence obtained after BPSK is modulated
A 0.Illustratively, 16 times of up-sampling interpolation processings refer to and are inserted into 15 after each point of the sequence obtained after BPSK is modulated
A 0.Wherein, up-sampling interpolation is gap periods etc. in order to equally spaced be inserted into random sequence on the carrier wave of OFDM symbol
In up-sampling multiple, such as when 16 times of up-samplings, gap periods are 16, and the subcarrier upper value for not being inserted into random sequence is 0.
Third step carries out time domain transformation to interpolating sequence, to obtain local synchronization sequence.
Wherein, frequency-domain transform can be IFFT (Inverse Fast Fourier Transform, inverse Fourier transform).
After carrying out frequency-domain transform to 1024 point interpolation sequences, obtained local synchronization sequence includes the short sequence being repeated 16 times, each short
The length of sequence is 64bit.
The synchronizing sequence generated using preceding method is with preferable autocorrelation and has lower peak-to-average force ratio.
It should be noted that the step 201 can be optional step, it, can be with if local synchronization sequence has been stored in advance
Without executing step 201.
202, it to signal progress frequency domain processing is received, obtains receiving signal sequence.
In the present embodiment, frequency domain processing is that FFT is handled.
It in the present embodiment, can be able to be setting by a group progress, every group of length to receiving signal to carry out frequency-domain transform
Value, the setting value can be 2 integral number power, such as 64, i.e., 64 point FFT operations are carried out to receiving signal.Here, docking is collected mail
Number sequence carries out FFT processing can be with the influence of DC-offset correction.
Here, receiving signal is time-domain signal, can be and is converted to digital baseband by the radiofrequency signal that receiving end receives
Then signal samples obtained sampled data, receiving signal includes multiple sampled datas.Reception signal sequence is frequency-region signal.
203, docking receives signal sequence and carries out delay relevant treatment, obtains the first sequence of correlation values.
The step 203 may include: that signal sequence progress delay process is received in docking；Calculate the conjugate complex for receiving signal sequence
Number；Reception signal sequence after delay process is multiplied with the conjugate complex number for receiving signal sequence.
In the present embodiment, it can dock and receive 1024 bat delay of signal sequence progress, then carry out subsequent step.For example, will
The 1st data r of acquisition received in signal sequence1, delay 1024 clap and then with receive signal sequence in the 1025th
Data r1025Conjugate complex number be multiplied；By the 2nd data r of acquisition received in signal sequence2Delay 1024 clap and then with
Receive the 1026th data r in signal sequence1026Conjugate complex number be multiplied, and so on.
Specifically the first sequence of correlation values can be obtained using following formula (1):
Wherein, CnFor the nth data in the first sequence of correlation values, rnIt indicates to receive the nth data in signal sequence,
r* n+1024Indicate to receive the conjugate complex number of the (n+1)th 024 data in signal sequence.
Delay relevant treatment in the step 203, can eliminate the influence of carrier wave frequency deviation.
204, delay relevant treatment is carried out to the first sequence of correlation values, obtains the second sequence of correlation values.
The step 204 may include: to carry out delay process to the first sequence of correlation values；Calculate being total to for the first sequence of correlation values
Yoke plural number；The first sequence of correlation values after delay process is multiplied with the conjugate complex number of the first sequence of correlation values.
In the step 204,512 can be carried out to the first sequence of correlation values and clap delay, then carry out subsequent step.
205, as unit of setting length, the corresponding correlation window function of the second sequence of correlation values of multiple units is calculated separately
Rate and delay correlation window power.
Wherein, setting length can be the equal length organized in step 202, for example, 512 points.Second sequence of correlation values
In, adjacent continuous multiple data form a unit, and continuous multiple data after the unit form next unit.
For the second sequence of correlation values of a unit, correlation window power can be calculated using formula (2), using formula
(3) computation delay correlation window power.
Wherein, PnFor with Cn+512C* n+512The corresponding correlation window power of the second sequence of correlation values to open first unit,
SnFor with CnC* n+512The corresponding delay correlation window power of the second sequence of correlation values to open first unit, CnFor the first correlation
N-th of correlation in value sequence, Cn+kFor the n-th+k correlations in the first sequence of correlation values, C* n+k+512Indicate that first is related
The conjugate complex number of n-th+k+512 correlations in value sequence.
206, according to the corresponding correlation window power of the second sequence of correlation values of each unit and delay correlation window power
Determine just sync bit.
The step 206 may include: by the corresponding delay related power of the second sequence of correlation values of each unit and correlation
The ratio of window power is compared with predetermined threshold value, if the corresponding ratio of continuous N number of second sequence of correlation values is all larger than pre- gating
Limit value then determines just to synchronize and search for successfully, by the knot of corresponding second sequence of correlation values of n-th ratio in continuous N number of ratio
Beam position is determined as just sync bit.Wherein, N is the positive integer greater than 1.N and threshold value can be arranged according to actual needs,
Such as it can be determined by emulation.Illustratively, N=256.Illustratively, which can be 0.125~0.5, preferably
0.25.As N=256 and when threshold value is 0.25, false-alarm and false dismissal probability can be reduced under Low SNR.
When determining just synchronous search for successfully, height just genlocing pulse can be set, first genlocing pulse is used to indicate
It is timed synchronization based on the reception signal after first sync bit, i.e. execution step 207~211.
207, the direct current biasing of the reception signal after eliminating just sync bit.
In response to the first genlocing pulse, reception signal can be cached, in order to inclined to the direct current for receiving signal is eliminated
It sets.For example, 1024 sampled datas can be cached.
The step 207 may include:
1024 points of cumulative averagings are carried out to I, Q two paths of signals received after first sync bit, respectively obtain two-way letter
Number direct current biasing；
Corresponding direct current biasing is individually subtracted in I, Q two paths of signals, to eliminate the direct current biasing for receiving signal.
208, delay correlation is carried out to the reception signal after DC-offset correction, obtains third sequence of correlation values.
In the step 208, first the reception signal after DC-offset correction can be delayed, then will eliminate direct current
Reception signal after biasing and the reception signal after the DC-offset correction of 32 points of delay carry out conjugation auto-correlation, obtain third phase
Close value sequence.
209, third sequence of correlation values is quantified, obtains quantized result.
The step 209 may include:
It is added up as the period to the correlation in third sequence of correlation values using the length set, obtains cumulative sequence；
Cumulative sequence is quantified as { -1,1 }, obtains quantized result.
Illustratively, the length set can promote signal-to-noise ratio as 64 points, by multiple cumulative mean.
Wherein, when quantifying cumulative sequence, it is quantified as 1 greater than 0, is quantified as -1 less than 0.
210, matched filtering is carried out to quantized result using local synchronization sequence, obtains matched filtering result.
In the step 210, matched filtering refer to by the short sequence of local synchronization sequence do delay it is related after again with quantization
As a result delay conjugation cross-correlation calculation is carried out, by the cumulative summation of cross-correlation calculation result, obtains matched filtering result.In the step
In 210, the delay umber of beats of short sequence is equal with the delay umber of beats in step 208, in the present embodiment, for 32 points of delays.
Wherein, matched filtering is the process of a sliding.
211, peak value searching is carried out to matched filtering result, to determine timing synchronization position.
In the step 211, by matched filtering result compared with peak value threshold, it is determined as peak value greater than threshold value.If
All there is not peak value in continuous multiple points (such as 128 points), then the position for determining that upper minor peaks occur is synchronization signal end point,
That is timing synchronization position.
After determining timing synchronization position, high timed synchronization pulse signal can be set and exported periodically same in reception signal
Step set after sampled data.
In embodiments of the present invention, frequency domain conversion is carried out with the influence of DC-offset correction, so by will first receive signal
It is related that delay twice carried out to the reception signal sequence in frequency domain afterwards, so as to eliminate the influence of carrier wave frequency deviation, and then can be with
The synchronous accuracy of ofdm signal is improved, and the synchronous success rate of the signal under Low SNR can be improved, with the present embodiment
Middle example data carries out emulation experiment, the experimental results showed that this method can have 99.99% under conditions of -25dB signal-to-noise ratio
Success rate.
Further, since continuously the corresponding ratio of N number of second sequence of correlation values is all larger than predetermined threshold value as determining just same
The condition that step is set, the corresponding ratio of each second sequence of correlation values, without being carried out by the way of FFT window sliding
Just synchronous, calculation amount is small, is particularly suitable for the limited situation of hardware computation resource.
Fig. 4 is a kind of structural schematic diagram of ofdm signal synchronizing device provided in an embodiment of the present invention.Referring to fig. 4, should
Ofdm signal synchronizing device 400 includes: frequency-domain transform module 410, correlation module 420, first synchronization module 430 and Timing Synchronization mould
Block 440.
Frequency-domain transform module 410 is used to obtain receiving signal sequence to signal progress frequency-domain transform is received；Correlation module
420 carry out delay relevant treatment for docking receipts signal sequence, obtain the first sequence of correlation values, and for the first correlation sequence
Column carry out delay relevant treatment, obtain the second sequence of correlation values；First synchronization module 430 is used to carry out based on the second sequence of correlation values
Signal is just synchronous, to determine just sync bit；SNR detection module 440 is used for based on after local synchronization sequence and first sync bit
Reception signal, determine timing synchronization position.
Optionally, which includes: power calculation submodule and first synchronous submodule.Power calculation submodule is used
In the corresponding correlation window power of the second sequence of correlation values and delay phase that as unit of setting length, calculate separately multiple units
Close window power；Just synchronous submodule is used for the corresponding correlation window power of the second sequence of correlation values according to each unit and prolongs
Shi Xiangguan window power determines just sync bit.
Further, which is used for the corresponding delay associated window of the second sequence of correlation values of each unit
The ratio of mouth power and correlation window power is compared with predetermined threshold value；If the second sequence of correlation values of continuous N number of unit is corresponding
Ratio be all larger than predetermined threshold value, then by the end of corresponding second sequence of correlation values of n-th ratio in continuous N number of ratio
Position is determined as just sync bit.
Optionally, which includes: that direct current biasing eliminates submodule, relevant sub-module, quantization submodule, filter
Marble module and peak value searching submodule.Direct current biasing eliminates submodule and is used to eliminate the direct current biasing for receiving signal；Correlator
Module is used to obtain third sequence of correlation values to going the reception signal after removing DC bias to carry out delay correlation；Quantify submodule
For quantifying to third sequence of correlation values, quantized result is obtained；Submodule is filtered to be used for using local synchronization sequence to amount
Change result and carry out matched filtering, obtains matched filtering result；Peak value searching submodule carries out peak value searching to matched filtering result,
To determine timing synchronization position.
Optionally, the device further include: synchronizing sequence generation module 460, for carrying out binary phase-shift to random sequence
Keying BPSK modulation obtains modulation sequence；Up-sampling interpolation processing is carried out to modulation sequence, obtains interpolating sequence；To interpolation sequence
Column carry out time domain transformation, obtain local synchronization sequence.
Optionally, which further includes data buffer unit, receives signal for caching.
It should be understood that ofdm signal synchronizing device provided by the above embodiment carry out ofdm signal it is synchronous when, only
The example of the division of the above functional modules, in practical application, can according to need and by above-mentioned function distribution by
Different functional modules is completed, i.e., the internal structure of equipment is divided into different functional modules, described above complete to complete
Portion or partial function.In addition, ofdm signal synchronizing device provided by the above embodiment and ofdm signal synchronous method embodiment
Belong to same design, specific implementation process is detailed in embodiment of the method, and which is not described herein again.
Fig. 5 shows the structural block diagram of the ofdm signal synchronizing device 600 of an illustrative embodiment of the invention offer.It should
Device 600 can be terminal device, such as desktop computer, smart phone, tablet computer etc..
Illustratively, device 600 includes: processor 601 and memory 602.
Processor 601 may include one or more processing cores, such as 4 core processors, 8 core processors etc..Place
Reason device 601 can use DSP (Digital Signal Processing, Digital Signal Processing), FPGA (Field-
Programmable Gate Array, field programmable gate array), PLA (Programmable Logic Array, may be programmed
Logic array) at least one of example, in hardware realize.Processor 601 also may include primary processor and coprocessor, master
Processor is the processor for being handled data in the awake state, also referred to as CPU (Central Processing
Unit, central processing unit)；Coprocessor is the low power processor for being handled data in the standby state.?
In some embodiments, processor 601 can be integrated with GPU (Graphics Processing Unit, image processor),
GPU is used to be responsible for the rendering and drafting of content to be shown needed for display screen.In some embodiments, processor 601 can also be wrapped
AI (Artificial Intelligence, artificial intelligence) processor is included, the AI processor is for handling related machine learning
Calculating operation.
Memory 602 may include one or more computer readable storage mediums, which can
To be non-transient.Memory 602 may also include high-speed random access memory and nonvolatile memory, such as one
Or multiple disk storage equipments, flash memory device.In some embodiments, the non-transient computer in memory 602 can
Storage medium is read for storing at least one instruction, at least one instruction performed by processor 601 for realizing this Shen
Please in embodiment of the method provide ofdm signal synchronous method.
In some embodiments, device 600 is also optional includes: peripheral device interface 603 and at least one peripheral equipment.
It can be connected by bus or signal wire between processor 601, memory 602 and peripheral device interface 603.Each peripheral equipment
It can be connected by bus, signal wire or circuit board with peripheral device interface 603.Specifically, peripheral equipment includes: radio circuit
604, at least one of touch display screen 605, camera 606, voicefrequency circuit 607, positioning component 608 and power supply 609.
Peripheral device interface 603 can be used for I/O (Input/Output, input/output) is relevant outside at least one
Peripheral equipment is connected to processor 601 and memory 602.In some embodiments, processor 601, memory 602 and peripheral equipment
Interface 603 is integrated on same chip or circuit board；In some other embodiments, processor 601, memory 602 and outer
Any one or two in peripheral equipment interface 603 can realize on individual chip or circuit board, the present embodiment to this not
It is limited.
Radio circuit 604 is for receiving and emitting RF (Radio Frequency, radio frequency) signal, also referred to as electromagnetic signal.It penetrates
Frequency circuit 604 is communicated by electromagnetic signal with communication network and other communication equipments.Radio circuit 604 turns electric signal
It is changed to electromagnetic signal to be sent, alternatively, the electromagnetic signal received is converted to electric signal.Optionally, radio circuit 604 wraps
It includes: antenna system, RF transceiver, one or more amplifiers, tuner, oscillator, digital signal processor, codec chip
Group, user identity module card etc..Radio circuit 604 can be carried out by least one wireless communication protocol with other terminals
Communication.The wireless communication protocol includes but is not limited to: Metropolitan Area Network (MAN), each third generation mobile communication network (2G, 3G, 4G and 4G), wireless office
Domain net and/or WiFi (Wireless Fidelity, Wireless Fidelity) network.In some embodiments, radio circuit 604 may be used also
To include the related circuit of NFC (Near Field Communication, wireless near field communication), the application is not subject to this
It limits.
Display screen 605 is for showing UI (UserInterface, user interface).The UI may include figure, text, figure
Mark, video and its their any combination.When display screen 605 is touch display screen, display screen 605 also there is acquisition to show
The ability of the touch signal on the surface or surface of screen 605.The touch signal can be used as control signal and be input to processor
601 are handled.At this point, display screen 605 can be also used for providing virtual push button and/or dummy keyboard, also referred to as soft button and/or
Soft keyboard.In some embodiments, display screen 605 can be one, and the front panel of device 600 is arranged；In other embodiments
In, display screen 605 can be at least two, be separately positioned on the different surfaces of device 600 or in foldover design；In still other reality
It applies in example, display screen 605 can be flexible display screen, be arranged on the curved surface of device 600 or on fold plane.Even, it shows
Display screen 605 can also be arranged to non-rectangle irregular figure, namely abnormity screen.Display screen 605 can use LCD (Liquid
Crystal Display, liquid crystal display), OLED (Organic Light-Emitting Diode, Organic Light Emitting Diode)
Etc. materials preparation.
CCD camera assembly 606 is for acquiring image or video.Optionally, CCD camera assembly 606 include front camera and
Rear camera.In general, the front panel of terminal is arranged in front camera, the back side of terminal is arranged in rear camera.One
In a little embodiments, rear camera at least two is main camera, depth of field camera, wide-angle camera, focal length camera shooting respectively
Any one in head, to realize that main camera and the fusion of depth of field camera realize background blurring function, main camera and wide-angle
Camera fusion realizes that pan-shot and VR (Virtual Reality, virtual reality) shooting function or other fusions are clapped
Camera shooting function.
Voicefrequency circuit 607 may include microphone and loudspeaker.Microphone is used to acquire the sound wave of user and environment, and will
Sound wave, which is converted to electric signal and is input to processor 601, to be handled, or is input to radio circuit 604 to realize voice communication.
For stereo acquisition or the purpose of noise reduction, microphone can be separately positioned on the different parts of device 600 to be multiple.Mike
Wind can also be array microphone or omnidirectional's acquisition type microphone.Loudspeaker is then used to that processor 601 or radio circuit will to be come from
604 electric signal is converted to sound wave.Loudspeaker can be traditional wafer speaker, be also possible to piezoelectric ceramic loudspeaker.When
When loudspeaker is piezoelectric ceramic loudspeaker, the audible sound wave of the mankind can be not only converted electrical signals to, it can also be by telecommunications
Number the sound wave that the mankind do not hear is converted to carry out the purposes such as ranging.In some embodiments, voicefrequency circuit 607 can also include
Earphone jack.
Positioning component 608 is used for the current geographic position of positioning device 600, to realize navigation or LBS (Location
Based Service, location based service).Positioning component 608 can be the GPS (Global based on the U.S.
Positioning System, global positioning system), the dipper system of China, Russia Gray receive this system or European Union
The positioning component of Galileo system.
Power supply 609 is used to be powered for the various components in device 600.Power supply 609 can be alternating current, direct current,
Disposable battery or rechargeable battery.When power supply 609 includes rechargeable battery, which can support wired charging
Or wireless charging.The rechargeable battery can be also used for supporting fast charge technology.
In some embodiments, device 600 further includes having one or more sensors 610.The one or more sensors
610 include but is not limited to: acceleration transducer 611, gyro sensor 612, pressure sensor 613, fingerprint sensor 614,
Optical sensor 614 and proximity sensor 616.
It will be understood by those skilled in the art that the restriction of the not structure twin installation 600 of structure shown in Fig. 5, can wrap
It includes than illustrating more or fewer components, perhaps combine certain components or is arranged using different components.
The embodiment of the present disclosure additionally provides a kind of non-transitorycomputer readable storage medium, when in the storage medium
When instruction is executed by the processor of computing system, so that computing system is able to carry out the OFDM of Fig. 2 and Fig. 3 any offer
Signal synchronizing method.
A kind of computer program product comprising instruction, when run on a computer, so that computer executes progress
The instruction of ofdm signal synchronous method provided by Fig. 2 and Fig. 3 is any.
Those of ordinary skill in the art will appreciate that realizing that all or part of the steps of above-described embodiment can pass through hardware
It completes, relevant hardware can also be instructed to complete by program, the program can store in a kind of computer-readable
In storage medium, storage medium mentioned above can be read-only memory, disk or CD etc..
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of ofdm signal synchronous method, which is characterized in that the described method includes:
Frequency-domain transform is carried out to signal is received, obtains receiving signal sequence；
Delay relevant treatment is carried out to the reception signal sequence, obtains the first sequence of correlation values；
Delay relevant treatment is carried out to first sequence of correlation values, obtains the second sequence of correlation values；
It carries out signal based on second sequence of correlation values just to synchronize, to determine just sync bit；
Based on the reception signal after local synchronization sequence and the just sync bit, timing synchronization position is determined.
2. the method according to claim 1, wherein at the beginning of the progress signal based on second sequence of correlation values
It is synchronous, to determine just sync bit, comprising:
As unit of setting length, calculate separately multiple units the corresponding correlation window power of second sequence of correlation values and
Be delayed correlation window power；
According to the corresponding correlation window power of second sequence of correlation values of each unit and the delay correlation window
Power determines just sync bit.
3. according to the method described in claim 2, it is characterized in that, second sequence of correlation values according to each unit
The corresponding correlation window power and the delay correlation window power determine just sync bit, comprising:
By the corresponding delay correlation window power of second sequence of correlation values of each unit and the correlation window function
The ratio of rate is compared with predetermined threshold value；
It, will continuous N number of ratio if the corresponding ratio of second sequence of correlation values of continuous N number of unit is all larger than predetermined threshold value
The end position of corresponding second sequence of correlation values of n-th ratio in value is determined as just sync bit.
4. the method according to claim 1, wherein described be based on local synchronization sequence and the just sync bit
The reception signal afterwards, determines timing synchronization position, comprising:
The direct current biasing of the reception signal after eliminating the just sync bit；
To going the reception signal after removing DC bias to carry out delay correlation, third sequence of correlation values is obtained；
The third sequence of correlation values is quantified, quantized result is obtained；
Matched filtering is carried out to the quantized result using the local synchronization sequence, obtains matched filtering result；
Peak value searching is carried out to the matched filtering result, to determine timing synchronization position.
5. method according to any one of claims 1 to 4, which is characterized in that the method also includes:
Binary phase shift keying BPSK modulation is carried out to random sequence, obtains modulation sequence；
Up-sampling interpolation processing is carried out to the modulation sequence, obtains interpolating sequence；
Time domain transformation is carried out to interpolating sequence, obtains local synchronization sequence.
6. a kind of ofdm signal synchronizing device, which is characterized in that described device includes:
Frequency-domain transform module, for obtaining receiving signal sequence to signal progress frequency-domain transform is received；
Correlation module obtains the first sequence of correlation values for carrying out delay relevant treatment to the reception signal sequence；And to institute
It states the first sequence of correlation values and carries out delay relevant treatment, obtain the second sequence of correlation values；
First synchronization module is just synchronized for carrying out signal based on second sequence of correlation values, to determine just sync bit；
SNR detection module, for based on the reception signal after local synchronization sequence and the just sync bit, it to be fixed to determine
When sync bit.
7. device according to claim 6, which is characterized in that the just synchronization module, comprising:
Power calculation submodule, for as unit of setting length, calculating separately second sequence of correlation values of multiple units
Corresponding correlation window power and delay correlation window power；
Just synchronous submodule, for according to each unit the corresponding correlation window power of second sequence of correlation values and
The delay correlation window power determines just sync bit.
8. device according to claim 6, which is characterized in that the SNR detection module, comprising:
Direct current biasing eliminates submodule, for eliminating the direct current biasing for receiving signal；
Relevant sub-module, for obtaining third correlation to going the reception signal after removing DC bias to carry out delay correlation
Sequence；
Quantify submodule and obtains quantized result for quantifying to the third sequence of correlation values；
Submodule is filtered, for carrying out matched filtering to the quantized result using the local synchronization sequence, obtains matching filter
Wave result；
Peak value searching submodule carries out peak value searching to the matched filtering result, to determine timing synchronization position.
9. a kind of ofdm signal synchronizing device, which is characterized in that described device includes: processor；It can be held for storage processor
The memory of row instruction；Wherein, the processor is configured to for executing the executable instruction being stored in the processor,
To realize such as ofdm signal synchronous method described in any one of claim 1 to 5.
10. a kind of computer readable storage medium, which is characterized in that when the instruction in the computer readable storage medium is by counting
When the processor of calculation system executes, so that the computing system is able to carry out ofdm signal described in any one of claim 1 to 5
Synchronous method.
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