CN109494159A - A kind of thin film transistor and its manufacturing method, array substrate and preparation method thereof, display device - Google Patents
A kind of thin film transistor and its manufacturing method, array substrate and preparation method thereof, display device Download PDFInfo
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- CN109494159A CN109494159A CN201811354863.3A CN201811354863A CN109494159A CN 109494159 A CN109494159 A CN 109494159A CN 201811354863 A CN201811354863 A CN 201811354863A CN 109494159 A CN109494159 A CN 109494159A
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- 239000000758 substrate Substances 0.000 title claims abstract description 141
- 239000010409 thin film Substances 0.000 title claims abstract description 108
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 76
- 238000002360 preparation method Methods 0.000 title abstract 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 85
- 239000000463 material Substances 0.000 claims abstract description 71
- 229920005591 polysilicon Polymers 0.000 claims abstract description 64
- 238000000034 method Methods 0.000 claims description 82
- 238000001312 dry etching Methods 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 26
- 229910052751 metal Inorganic materials 0.000 claims description 26
- 239000002210 silicon-based material Substances 0.000 claims description 21
- 238000012545 processing Methods 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 273
- 238000001039 wet etching Methods 0.000 description 19
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 238000002347 injection Methods 0.000 description 10
- 239000007924 injection Substances 0.000 description 10
- 230000009286 beneficial effect Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 8
- 229920000620 organic polymer Polymers 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- 238000013461 design Methods 0.000 description 5
- 239000002344 surface layer Substances 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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Abstract
The present invention discloses a kind of thin film transistor and its manufacturing method, array substrate and preparation method thereof, display device, is related to field of display technology, with the leakage current of pixel where reducing thin film transistor (TFT).The production method of the thin film transistor (TFT) includes: to form polysilicon material layer on the surface of underlay substrate, the first mask layer is formed in the top of polysilicon material layer, and polysilicon material layer is handled, form doped drain region, the second mask layer is formed in the top in doped drain region and the top of the first mask layer, the region not covered by the second mask plate to doped drain region carries out hole doping.The thin film transistor (TFT) is made using the production method of above-mentioned thin film transistor (TFT).Thin film transistor and its manufacturing method provided by the invention, array substrate and preparation method thereof, display device are for reducing leakage current.
Description
Technical Field
The invention relates to the technical field of display, in particular to a thin film transistor, a manufacturing method of the thin film transistor, an array substrate and a display device.
Background
A liquid crystal display device is a flat display device having a high display resolution, has a good display effect, and is currently the mainstream display device in the market.
In the manufacturing process of a thin film transistor used in an existing low-temperature polysilicon liquid crystal display device, a wet etching process is used to form a gate on the surface of a polysilicon material layer, at this time, on the premise that a photoresist covered on the surface of the gate is not removed, the photoresist on the surface of the gate is used as a mask to inject a hole into the polysilicon material layer to form a hole doping portion, then the photoresist on the surface of the gate is removed, and then a Lightly Doped Drain (LDD) process is performed on the polysilicon material layer to form a Lightly Doped Drain (i.e., LDD structure). The inventor finds that the linear length of the LDD structure of the thin film transistor used in the conventional low temperature polysilicon liquid crystal display device is short, so that the leakage current of the pixel where the thin film transistor is positioned is large, and the production yield of the low temperature polysilicon liquid crystal display device is reduced.
Disclosure of Invention
The invention aims to provide a thin film transistor and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display device, so as to reduce the leakage current of a pixel where the thin film transistor is located.
In order to achieve the above object, the present invention provides a method for manufacturing a thin film transistor, including:
forming a polycrystalline silicon material layer on the surface of the substrate base plate;
forming a first mask layer above the polycrystalline silicon material layer, so that the orthographic projection of the first mask layer on the polycrystalline silicon material layer covers a partial area of the polycrystalline silicon material layer;
processing the polycrystalline silicon material layer under the mask of the first mask layer to form a doped drain region;
forming a second mask layer above the doped drain region far from the substrate and above the first mask layer far from the substrate, so that the orthographic projection of the second mask plate in the doped drain region covers a partial region of the doped drain region, and the line width direction of the second mask layer is the same as the line length direction of the doped drain region;
and carrying out hole doping on the region of the doped drain region which is not covered by the orthographic projection of the second mask plate in the doped drain region under the mask of the second mask layer, so that a hole doped part and a doped drain part are formed in the doped drain region.
Compared with the prior art, in the manufacturing method of the thin film transistor, the second mask layer is formed above the doped drain region far from the substrate and above the first mask layer far from the substrate, so that the second mask covers part of the doped drain region in the orthographic projection of the doped drain region, and then the hole doping is performed on the region of the doped drain region which is not covered by the orthographic projection of the second mask in the doped drain region under the mask of the second mask layer, so that the doped drain region is finally formed in the region of the doped drain region which is covered by the orthographic projection of the second mask in the doped drain region, and the hole doping portion is finally formed in the region of the doped drain region which is not covered by the orthographic projection of the second mask in the doped drain region. And because the line width direction of the second mask layer is the same as the line length direction of the doped drain region, the line width of the second mask layer determines the line length of the doped drain region, and before the second mask layer is formed above the doped drain region far away from the substrate and above the first mask layer far away from the substrate, the polysilicon material layer is processed under the mask of the first mask layer to form the doped drain region.
The invention also provides a manufacturing method of the array substrate, which comprises the following steps:
manufacturing a plurality of thin film transistors positioned in a display area on the surface of a substrate base plate; the manufacturing method of one thin film transistor array in the plurality of thin film transistors is the manufacturing method of the thin film transistor.
Compared with the prior art, the manufacturing method of the array substrate provided by the invention has the same beneficial effects as those of the manufacturing method of the thin film transistor, and the details are not repeated herein.
The invention also provides a thin film transistor which is manufactured by adopting the manufacturing method of the thin film transistor.
Compared with the prior art, the beneficial effects of the thin film transistor provided by the invention are the same as those of the manufacturing method of the thin film transistor, and are not repeated herein.
The invention also provides an array substrate which is characterized by comprising a thin film transistor array positioned in a display area, wherein the thin film transistor array comprises at least one thin film transistor.
Compared with the prior art, the beneficial effects of the array substrate provided by the invention are the same as those of the thin film transistor, and are not described herein again.
The invention also provides a display device which comprises the array substrate.
Compared with the prior art, the display device provided by the invention has the same beneficial effects as the array substrate, and the description is omitted here.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a flow chart of a conventional method for fabricating a thin film transistor;
FIG. 2 is a flow chart of a conventional process for fabricating a thin film transistor;
fig. 3 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention;
fig. 4 is a first flowchart of a thin film transistor according to an embodiment of the present invention;
fig. 5 is a first flowchart of a thin film transistor according to an embodiment of the present invention;
fig. 6 is a block diagram illustrating a detailed flow of a thin film transistor according to an embodiment of the present invention;
fig. 7 is a block diagram illustrating a detailed flowchart of a thin film transistor according to an embodiment of the present invention;
fig. 8 is a flowchart of a gate manufacturing method according to an embodiment of the invention;
fig. 9 is a first process flow diagram of a thin film transistor according to an embodiment of the present invention;
fig. 10 is a second process flow diagram of a thin film transistor according to an embodiment of the present invention;
fig. 11 is a third process flow diagram of a thin film transistor according to an embodiment of the present invention;
FIG. 12 is a flow chart of a fabrication process for a gate fan-out structure included in a conventional array substrate;
fig. 13 is a schematic structural diagram of a gate fan-out structure included in the array substrate according to an embodiment of the present invention;
fig. 14 is a flowchart illustrating a manufacturing process of a gate fan-out structure included in the array substrate according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The manufacturing method of the thin film transistor used in the existing low-temperature polysilicon display device is shown in fig. 1 and fig. 2, and specifically comprises the following steps:
step S110: as shown in fig. 2 a, a polysilicon material layer 20 is formed on the surface of the substrate base plate 10.
Step S120: as shown in fig. 2 a, an insulating layer 30 is formed on the surface of the polysilicon material layer 20 away from the base substrate 10.
Step S130: as shown in fig. 2 a, a metal layer 40 is formed on the surface of the insulating layer 30 away from the polysilicon material layer 20;
step S140: as shown in fig. 2 a, a gate mask layer 50 is formed on the surface of the metal layer 40 away from the insulating layer 30;
step S150: as shown in fig. 2B, the metal layer 40 is etched by wet etching under the mask of the gate mask layer 50 to obtain the gate 41, and the surface of the gate 41 away from the insulating layer 30 is still covered with the gate mask layer 50, where the material used for the gate mask layer 50 is generally a photoresist, but may be other materials suitable for forming a mask layer.
Step S160: as shown in fig. 2C, ideally, the region of the metal layer 40 covered by the gate mask layer 50 should not be etched, that is, the orthographic projection of the gate mask layer 50 on the insulating layer 30 is exactly coincident with the orthographic projection of the gate 41 on the insulating layer 30; however, the unilateral CD deviation b1 of the wet etching process is-0.5 μm, so that the orthographic area of the actual gate electrode formed on the insulating layer 30 is smaller than the orthographic area of the target gate electrode on the insulating layer 30 (i.e. the orthographic area of the gate mask layer 50 on the insulating layer 30), and the distance between the orthographic projection edge of the gate mask layer 50 on the insulating layer 30 and the orthographic projection edge of the gate electrode on the insulating layer 30 is 0.5 μm. And after the wet etching, the gate mask layer 50 for assisting the wet etching is not damaged and still remains. Based on this, under the mask of the gate mask layer 50, the hole injection (i.e. ion implantation) is performed on the polysilicon material layer 20, so that the hole doped portion 23 is formed in the region of the polysilicon material layer 20 that is not covered by the gate mask layer 50 in the orthographic projection of the polysilicon material layer 20, and the region of the polysilicon material layer 20 that is covered by the gate mask layer 50 in the orthographic projection of the polysilicon material layer 20 still maintains the original shape.
Step S170: as shown in D in fig. 2, in the process of injecting the hole, the surface layer of the gate mask layer 50 is modified to a certain extent, and the surface of the gate mask layer 50 needs to be etched by using a dry etching process to remove the modified substance, i.e., the modified surface layer, on the surface of the gate mask layer 50, and then the remaining gate mask layer 50 is stripped; when holes are injected, the valence of the injected ions is determined according to the type of the polysilicon material layer, for example: when the polysilicon material layer contains polysilicon material of N-type Low Temperature Polysilicon (LTPS), the implanted ions are generally pentavalent positive ions.
Step S180: as shown in fig. 2E, in view of the unilateral CD deviation b2 of the dry etching being-0.25 μm, the orthographic projection of the gate 41 after the dry etching on the insulating layer 30 is smaller than that of the gate 41 before the dry etching on the insulating layer 30, and the distance between the orthographic projection edge of the gate 41 after the dry etching on the insulating layer 30 and the orthographic projection edge of the gate 41 before the dry etching on the insulating layer 30 is 0.25 μm, so that the original polysilicon material layer 20 is divided into three regions at this time. Wherein the first region is a region covered by the orthographic projection of the gate electrode 41 on the polysilicon material layer 20, and is used for forming a channel when the thin film transistor is conductive, and therefore, the region is defined as a channel forming region 21; the second area is an area covered by the orthographic projection of the blank area formed by the wet etching error and the dry etching error on the polycrystalline silicon material layer 20, and the second area is protected by the grid mask plate when the cavity is injected, so that the original property of the polycrystalline silicon material is still reserved in the second area and no change is generated; the third region is a hole-doped portion 23 formed after hole injection. Based on this, the second region and the third region may be further processed by a lightly doped drain process under the mask of the gate 41, so as to obtain the doped drain portion 22.
It is understood that when the second region and the third region are processed by the lightly doped drain process, although the hole doping portion 23 included in the third region is ion-implanted, the performance of the hole doping portion 23 is not affected. In the process flow chart of the conventional method for manufacturing a thin film transistor shown in fig. 1 and the schematic structural diagram of the thin film transistor shown in fig. 3, the left-right direction in fig. 1 and the left-right direction in fig. 3 are the line width direction of the gate electrode 41, the line length direction of the doped drain portion 22, and the line length direction of the hole doped portion 23. The channel forming region 21, the doped drain portion 22, the hole doped portion 23, and the gate of the conventional thin film transistor are all linear structures, the linear direction of the gate is orthogonal to the linear direction of the channel forming region 21, and the linear direction of the channel forming region 21, the linear direction of the doped drain portion 22, and the linear direction of the hole doped portion 23 are the same.
As can be seen from the above, in the manufacturing process of the conventional thin film transistor, a wet etching process is used to manufacture a gate, and the doped drain portion 22 is formed by using the gate as a mask layer and using a lightly doped drain self-alignment method; moreover, the line length of the doped drain portion 22 included in the conventional thin film transistor is limited by the single-sided CD deviation of the wet etching process and the single-sided CD deviation of the dry etching process, so that the line length of the doped drain portion 22 is restricted. The length of the doped drain portion 22 is limited, so that the resistance of the doped drain portion 22 is also limited, and the leakage current of the pixel in which the conventional thin film transistor is located is relatively large.
It should be noted that the doped drain portion 22 is divided into two portions, and the length of each portion should be equal to the absolute value of the sum of the single-sided CD deviation of the wet etching process and the single-sided CD deviation of the dry etching process. For example: when the single-sided CD deviation b1 of the wet etching process is equal to-0.5 μm and the single-sided CD deviation b2 of the dry etching process is equal to-0.25, the line length b of the two portions included in the doped drain portion 22 is 0.75 μm.
As shown in fig. 4 to fig. 11, an embodiment of the present invention provides a method for manufacturing a thin film transistor, where the method for manufacturing a thin film transistor includes:
step S210: forming a polysilicon material layer 20 on the surface of the substrate 10; the substrate 10 generally includes a glass substrate and a buffer layer formed on the glass substrate, and a polysilicon material may be formed on a surface of the buffer layer facing away from the glass substrate, specifically see a in fig. 9, a in fig. 10, and a in fig. 11.
Step S220: a first mask layer M1 is formed over the polysilicon material layer 20 such that the first mask layer M1 covers a partial region of the polysilicon material layer 20 in an orthographic projection of the polysilicon material layer 20. The region of the polysilicon material layer 20 covered by the orthographic projection of the first mask layer M1 on the polysilicon material layer 20 is used to form a channel under the power-on state of the tft, the region of the polysilicon material layer 20 covered by the orthographic projection of the first mask layer M1 on the polysilicon material layer 20 is defined as a channel forming region 21, and the region of the polysilicon material layer 20 not covered by the orthographic projection of the first mask layer M1 on the polysilicon material layer 20 is defined as a doping forming region, specifically refer to B in fig. 9, a in fig. 10, and a in fig. 11.
Step S230: processing the polysilicon material layer 20 under the mask of the first mask layer M1 to form a doped drain region CZ (i.e., LDD region); since the channel forming region 21 is covered by the orthographic projection of the first mask layer M1 on the polysilicon material layer 20, the processing of the polysilicon material layer 20 under the mask of the first mask layer M1 is substantially a process of processing the doping forming region, specifically, see C in fig. 9, B in fig. 10, and B in fig. 11.
Illustratively, under the mask of the first mask layer M1, the doped drain region CZ may be obtained by performing a light doped drain process on the doped formation region, but at this time, since the hole doped portion 23 is not formed in the doped drain region CZ, the doped drain region CZ is not equal to the doped drain portion 22 (i.e., LDD structure).
Step S240: forming a second mask layer M2 above the doped drain region CZ far away from the substrate base plate 10 and above the first mask layer M1 far away from the substrate base plate 10, so that the orthographic projection of the second mask plate in the doped drain region CZ covers a partial region of the doped drain region CZ, and the line width direction of the second mask layer M2 is the same as the line length direction of the doped drain region CZ. In this process, the region of the doped drain region CZ covered by the orthographic projection of the second mask on the doped drain region CZ is not affected in the subsequent processing, and the characteristics of the lightly doped drain region CZ are still remained, and this region finally forms the doped drain portion 22, specifically see D in fig. 9, C in fig. 10, and C in fig. 11.
Step S250: the hole doping is performed on the region of the doped drain region CZ not covered by the orthographic projection of the second mask on the doped drain region CZ under the mask of the second mask layer M2, which is substantially the process of performing the hole doping on the region of the doped drain region CZ not covered by the orthographic projection of the second mask on the doped drain region CZ to form the hole doped portion 23, so that the doped drain region CZ forms the hole doped portion 23 and the doped drain portion 22, specifically refer to E in fig. 9, D in fig. 10, and D in fig. 11.
Compared with the prior art, in the method for manufacturing the thin film transistor according to the embodiment of the present invention, the second mask layer M2 is formed above the doped drain region CZ away from the substrate 10 and above the first mask layer M1 away from the substrate 10, so that the second mask covers a partial region of the doped drain region CZ in the orthographic projection of the doped drain region CZ, and then the hole doping is performed on the region of the doped drain region CZ not covered by the orthographic projection of the second mask in the doped drain region CZ under the mask of the second mask layer M2, so that the doped drain region 22 is finally formed in the region of the doped drain region CZ covered by the orthographic projection of the second mask in the doped drain region CZ, and the hole doping portion 23 is finally formed in the region of the doped drain region CZ not covered by the orthographic projection of the doped drain region CZ. Since the line width direction of the second mask layer M2 is the same as the line length direction of the doped drain region CZ, the line width of the second mask layer M2 determines the line length of the doped drain region CZ, and before the second mask layer M2 is formed above the doped drain region CZ away from the substrate 10 and above the first mask layer M1 away from the substrate 10, the polysilicon material layer 20 is processed under the mask of the first mask layer M1 to form the doped drain region CZ.
It is understood that, after the step S250, at least the second mask layer M2 needs to be removed, and the material used for the second mask layer M2 is typically an organic polymer such as a photoresist. If the material of the second mask layer M2 is an organic polymer such as photoresist, the surface layer of the second mask layer M2 may be modified during hole doping to form a second modified surface layer with relatively high hardness, and therefore, when removing the second mask layer M2, it is necessary to first ash the second modified surface layer and then strip the remaining portion of the second mask layer M2, specifically refer to F in fig. 9, E in fig. 10, and E in fig. 11.
In some embodiments, as shown in fig. 5 and 6 and fig. 9 and 10, after forming the polysilicon material layer 20 on the surface of the substrate 10, before forming the first mask layer M1 above the polysilicon material layer 20, the method for manufacturing a thin film transistor further includes:
step S215: an insulating layer 30 is formed on the surface of the polysilicon material layer 20 away from the substrate 10, specifically see a in fig. 9 and a in fig. 10.
In one implementation, as shown in fig. 5 and 9, if the first mask layer M1 is a metal material capable of forming the gate 41, forming the first mask layer M1 above the polysilicon material layer 20 includes:
step S221: a gate electrode, which is the first mask layer M1, is formed on the surface of the insulating layer 30 away from the polysilicon material layer 20 by using a patterning process, see specifically B in fig. 9.
At this time, as shown in fig. 5, forming the second mask layer M2 above the doped drain region CZ away from the base substrate 10 and above the first mask layer M1 away from the base substrate 10 includes:
step S241: a second mask layer M2 is formed on the surface of the insulating layer 30 remote from the doped drain region CZ and on the surface of the gate remote from the insulating layer 30, see in particular E in fig. 9.
As can be seen from the above, before the first mask layer M1 is formed above the polysilicon material layer 20, the insulating layer 30 is formed on the surface of the polysilicon material layer 20 away from the substrate 10, so that the material used for controlling the first mask layer M1 is a metal material, and the first mask layer M1 manufactured by using the patterning process can be used as a mask for forming the doped drain region CZ, or after the first mask layer M1 is formed, the first mask layer M1 does not need to be stripped, but the first mask layer M1 is used as a gate after the thin film transistor is manufactured, thereby simplifying the manufacturing process of the thin film transistor. Therefore, in this implementation, the second mask layer M2 is removed in the last step to complete the fabrication of the thin film transistor.
In another implementation, as shown in fig. 6 and 10, the forming of the first mask layer M1 above the polysilicon material layer 20 includes:
step S222: a first mask layer M1 is formed on the surface of the insulating layer 30 away from the polysilicon material, so that the first mask layer M1 covers a partial region of the polysilicon material layer 20 in the orthographic projection of the polysilicon material layer 20, as shown in fig. 10B.
Forming the second mask layer M2 above the doped drain region CZ away from the substrate base plate 10 and above the first mask layer M1 away from the substrate base plate 10 includes:
step S242: a second mask layer M2 is formed on the surface of the doped drain region CZ away from the substrate 10 and the surface of the first mask layer M1 away from the substrate 10, as shown in fig. 10C.
As shown in fig. 6 and 10, after performing hole doping on the doped drain region CZ in the region where the orthographic projection of the doped drain region CZ by the second mask is not covered by the second mask under the mask of the second mask layer M2, the method for manufacturing a thin film transistor further includes:
step S261: removing the first mask layer M1 and the second mask layer M2; considering that the first mask layer M1 and the second mask layer M2 need to be removed at this step, see specifically fig. 10E; therefore, when the material of the first mask layer M1 and the material of the second mask layer M2 are selected, an organic polymer such as photoresist may be selected, and the manner of removing the first mask layer M1 and the second mask layer M2 may refer to the manner of removing the second mask layer M2, which will not be described in detail herein. When the material of the first mask layer M1 and the material of the second mask layer M2 are organic polymers such as photoresist, a photolithography process is generally used to fabricate the first mask layer M1 and the second mask layer M2, the photolithography process has high precision and small deviation, and the distance between the edge of the first mask layer M1 and the edge of the second mask layer M2 can be controlled according to the line length requirement of the doped drain portion 22, so that the line length of the doped drain portion 22 can be controlled.
Step S271: a gate electrode 41 is formed on the surface of the insulating layer 30 away from the substrate base plate 10 by a patterning process, specifically, see F in fig. 10.
In some embodiments, considering that the injected holes or ions do not easily penetrate through the dense insulating layer 30 when performing the above steps S230 and S250, it is necessary to increase the energy of hole injection or ion injection, which easily damages the insulating layer 30; therefore, the fabrication of step S250 can be completed before the insulating layer 30 is formed. Based on this, as shown in fig. 7 and 11, forming the first mask layer M1 above the polysilicon material layer 20 includes:
step S223: a first mask layer M1 is formed on the surface of the polysilicon material layer 20 away from the substrate base plate 10, so that the first mask layer M1 covers a partial area of the polysilicon material layer 20 in the orthographic projection of the polysilicon material layer 20, as shown in fig. 10 a.
As shown in fig. 7 and 11, forming the second mask layer M2 above the doped drain region CZ away from the base substrate 10 and above the first mask layer M1 away from the base substrate 10 includes:
step S243: and forming a second mask layer M2 on the surface of the doped drain region CZ away from the substrate base plate 10 and the surface of the first mask layer M1 away from the substrate base plate 10, specifically referring to C in fig. 10.
As shown in fig. 7 and 11, after performing hole doping on the doped drain region CZ in the region where the orthographic projection of the doped drain region CZ by the second mask is not covered by the second mask under the mask of the second mask layer M2, the method for manufacturing a thin film transistor further includes:
step S262: removing the first mask layer M1 and the second mask layer M2; considering that the first mask layer M1 and the second mask layer M2 need to be removed at this step, see specifically fig. 11E; therefore, when the material of the first mask layer M1 and the material of the second mask layer M2 are selected, an organic polymer such as photoresist may be selected, and the manner of removing the first mask layer M1 and the second mask layer M2 may refer to the manner of removing the second mask layer M2, which will not be described in detail herein. When the material of the first mask layer M1 and the material of the second mask layer M2 are organic polymers such as photoresist, a photolithography process is generally used to fabricate the first mask layer M1 and the second mask layer M2, the photolithography process has high precision and small deviation, and the distance between the edge of the first mask layer M1 and the edge of the second mask layer M2 can be controlled according to the line length requirement of the doped drain portion 22, so that the line length of the doped drain portion 22 can be controlled.
Step S272: an insulating layer 30 is formed on the surface of the hole doping portion 23 away from the substrate base plate 10 and the surface of the doped drain portion 22 away from the substrate base plate 10, so that the insulating layer 30 covers the substrate base plate 10 in the orthographic projection of the substrate base plate 10, specifically, see F in fig. 11.
Step S280: a gate electrode 41 is formed on the surface of the insulating layer 30 away from the substrate 10 by a patterning process, specifically, see G in fig. 11.
As can be seen from the above, doping the polysilicon material layer 20 before forming the insulating layer 30 can make the hole injection and the ion injection not need to pass through the dense insulating layer 30, which not only can reduce the energy of the hole injection and the ion injection, but also can completely avoid the damage of the hole injection and the ion injection to the insulating layer 30.
In some embodiments, as shown in fig. 8, the forming of the gate electrode 41 on the surface of the insulating layer 30 away from the substrate 10 by using the patterning process includes:
step SG 1: forming a metal layer 40 on the surface of the insulating layer 30 far away from the polysilicon material layer 20;
step SG 2: forming a third mask layer M3 on the surface of the metal layer 40 away from the insulating layer 30, so that the orthographic projection of the third mask layer M3 on the metal layer 40 covers a partial area of the metal layer 40;
step SG 3: and etching the metal layer 40 under the mask of the third mask layer M3 to form a gate 41.
Further, considering that the manufacturing process of the existing thin film transistor is manufactured together with the gate fan-out trace in the edge area of the array substrate, when the wet etching process is used to manufacture the gate 41 in the prior art, the deviation ratio of the wet etching process is large, which requires that the frame area of the array substrate is wider for forming the gate fan-out trace. Therefore, the frame of the conventional array substrate is generally wide, which is not favorable for narrowing the frame of the display device. Based on this, the gate electrode 41 can be formed by a dry etching process with a relatively small variation. Specifically, the above-mentioned etching the metal layer 40 under the mask of the first mask layer M1 to form the first mask layer M1 includes:
the metal layer 40 is subjected to dry etching processing under the mask of the third mask layer M3, and a first mask layer M1 is formed.
As shown in fig. 3 and 9, when the metal layer 40 is processed by the dry etching process, compared with the unilateral CD deviation b1(-0.5 μm) of the existing wet etching process, the unilateral CD deviation b2 of the dry etching in the embodiment of the present invention is 0.15 μm, which makes the line width of the gate 41 formed by the dry etching process larger than that formed by the wet etching process. Through testing, the line width of the gate 41 formed by the dry etching process reaches 3.0 μm to 3.5 μm.
In addition, when the gate electrode 41 is manufactured by using the dry etching process with a small deviation ratio, the deviation ratio of the dry etching process is small, the width of a frame reserved for the array substrate can be reduced, and the narrow frame of the display device is facilitated.
In some embodiments, as shown in fig. 3 and 9, the difference between the line width of the first mask layer M1 and the line width of the second mask layer M2 is greater than 1.5 μ M. Further, the doped drain portion 22 includes a first sub-doped drain portion 221 and a second sub-doped drain portion 222, an orthographic projection of the first sub-doped drain portion 221 on the substrate 10 and an orthographic projection of the second sub-doped drain portion 222 on the substrate 10 are located on two sides of an orthographic projection of the gate 41 on the substrate 10, and line lengths of the first sub-doped drain portion 221 and the second sub-doped drain portion 222 are both greater than one half of a difference between a line width of the first mask layer M1 and a line width of the second mask layer M2.
At this time, the line width of the first mask layer M1 and the line width of the second mask layer M2 may be manufactured according to the line length requirement of the first sub-doped drain portion 221 and the line length requirement of the second sub-doped drain portion 222, so that the line length of the first sub-doped drain portion 221 and the line length of the second sub-doped drain portion 222 are not constrained.
When the thin film transistor is manufactured in the manner shown in fig. 9, although the first mask layer M1 is a gate and the line width thereof is affected by the deviation of the dry etching, the second mask layer M2 is required to be manufactured subsequently (the line width of the second mask layer M2 is the same as the line width direction of the gate 41), and at this time, the line width of the second mask layer M2 can be controlled according to actual needs, so that the line length of the first sub-doped drain portion 221 and the second sub-doped drain portion 222 is increased, and the purpose of reducing the leakage current is achieved. For example: when the second mask layer M2 is made of photoresist, a photolithography process may be used to make the second mask layer M2, and the line width of the second mask layer M2 is increased by controlling the exposure amount of photolithography.
As shown in fig. 4 to 11, an embodiment of the present invention further provides a method for manufacturing an array substrate, where the method for manufacturing an array substrate includes:
manufacturing a plurality of thin film transistors positioned in a display area on the surface of a substrate base plate 10; the manufacturing method of one thin film transistor array in the plurality of thin film transistors is the manufacturing method of the thin film transistor.
Compared with the prior art, the manufacturing method of the array substrate provided by the embodiment of the invention has the same beneficial effects as those of the manufacturing method of the thin film transistor, and is not repeated herein.
The conventional array substrate includes not only a thin film transistor array located in a display region, but also a gate fan-out structure located in a frame region. As shown in fig. 12, the gate fan-out structure includes a plurality of gate leads 42, and a gap is formed between two adjacent gate leads 42. In the actual manufacturing process, the grid fan-out structure can be formed together with the thin film transistor array.
Specifically, as shown in fig. 12, in the prior art, when the metal layer 40 is etched by using a wet etching process under the mask of the gate mask layer 50 to form the gate 41, a wider frame needs to be reserved to accommodate the gate fan-out structure because an error of the wet etching process is relatively large. Meanwhile, in order to avoid the gate lead 42 included in the gate fan-out structure being too thin and disconnected, the line width of the plurality of gate leads 42 included in the gate fan-out structure needs to be increased, so that the design width of each unit (such as the blank area between the gate lead 42 and two adjacent gate leads 42 shown in fig. 12) of the gate fan-out structure is 5.5-5.7 um. This further increases the frame width of the array substrate, and is not favorable for narrowing the frame of the display device.
For example: a method for fabricating a conventional gate fan-out structure is shown in fig. 12 and described in detail below with reference to fig. 12.
In the manufacturing process of the conventional thin film transistor, when the insulating layer 30 and the metal layer 40 are formed, the insulating layer 30 and the metal layer 40 are also formed in the frame region of the substrate base plate 10, specifically, see a in fig. 2 and a in fig. 12.
In the conventional manufacturing process of the thin film transistor, when the gate mask layer 50 is formed, the gate mask layer 50 is also formed in the frame region of the substrate 10 as shown in a in fig. 2, and the pattern of the portion of the gate mask layer 50 located in the frame region of the substrate 10 is shown in a in fig. 12. The partial gate mask layer 50 includes a plurality of gate line masks, a line width d11 'of each gate line mask is 3.5 μm, and a distance between two adjacent gate line masks d 12' is 2.0 μm.
In the manufacturing process of the conventional thin film transistor, when the metal layer 40 is etched by using a wet etching process, the metal layer 40 that is also etched is located in the frame region of the substrate 10, because the unilateral CD deviation B1 of the wet etching process is-0.5 μm, the width d21 'of the gate lead 42 formed after the wet etching is 2.5, and the distance d 22' between two adjacent gate leads 42 is 3.0 μm, which is specifically shown as B in fig. 2 and B in fig. 12.
In the manufacturing process of the conventional thin film transistor, when the polysilicon material layer 20 is subjected to hole doping, the surfaces of the plurality of gate line masks of the gate mask layer 50 located in the frame region of the substrate base plate 10 are modified to a certain extent, which is specifically shown in fig. 2C and 12C.
In the manufacturing process of the existing thin film transistor, when the gate mask layer 50 is removed by using a dry etching process and a stripping process, the portion of the gate mask layer 50 located in the frame region of the substrate base plate 10 is also removed. Since the single-sided CD deviation of the dry etching is-0.25 μm, the width W of the gate lead 42 after the dry etching is 2.0 μm, and the gap S between two adjacent gate leads 42 after the dry etching is 3.5 μm, as shown in D in fig. 2 and D in fig. 12.
As can be seen from the above, in the conventional gate fan-out structure, W + S is reserved for each unit to be 2.0 μm +3.5 μm, which is 5.5 μm.
Based on this, in some embodiments, as shown in fig. 14, when the thin film transistor array located in the display region is formed on the surface of the substrate 10, the method for manufacturing the array substrate further includes:
a gate fan-out structure located in the frame region is formed on the surface of the substrate base plate 10.
The gate fan-out structure formed on the surface of the substrate base plate 10 in the frame region is substantially formed together with the gate line included in the thin film transistor.
Specifically, forming a gate fan-out structure located in the frame region on the surface of the substrate 10 includes:
a plurality of gate leads 42 constituting a gate fan-out structure are formed on the surface of the substrate base plate 10. The line width of each gate lead 42 is W, the distance between two adjacent gate leads 42 is S, and W + S is less than 5.5um to 5.7 um.
Illustratively, W + S is 4.2 to 4.5 μm, W is 2.2 to 2.5 μm, and S is 2.0 μm.
The method for manufacturing the gate fan-out lead will be described in detail below, taking the method for manufacturing a thin film transistor shown in fig. 9 as an example.
In the manufacturing process of the thin film transistor shown in fig. 9, when the insulating layer 30 and the metal layer 40 are formed on the surface of the base substrate 10, the insulating layer 30 and the metal layer 40 are formed not only in the display region of the base substrate 10 but also in the frame region of the base substrate 10, specifically, see a in fig. 9 and a in fig. 14.
In the manufacturing process of the thin film transistor shown in a in fig. 9, when the third mask layer M3 is formed, the third mask layer M3 is also formed in the frame region of the base substrate 10, and the pattern of the portion of the third mask layer M3 located in the frame region of the base substrate 10 is as shown in a in fig. 14. The portion of the third mask layer M3 located in the frame region of the substrate base plate 10 includes a plurality of sub-masks, the line width d11 of each sub-mask is 2.3 μ M, and the distance between two adjacent sub-masks d12 is 2.0 μ M.
In the manufacturing process of the thin film transistor shown in fig. 9, when the metal layer 40 is etched by using a dry etching process, the portion of the metal layer 40 located in the frame region of the substrate base plate 10 is also dry etched. Since the single-sided CD deviation B2 of the dry etching is 0.15 μm, the line width W of the formed gate lead 42 is 2.0 μm, and the line widths of two adjacent gate line leads are 2.3 μm, specifically, as shown in fig. 9B, 9C, 13B, and 14C.
In the manufacturing process of the thin film transistor shown in fig. 9, when the second mask layer M2 is formed, the surface of the gate lead 42 away from the base substrate 10 and the surface of the portion of the insulating layer 30 located in the frame region of the base substrate 10 away from the base substrate 10 also form a second mask layer M2, which is specifically shown in fig. 9D and fig. 14D.
In the manufacturing process of the thin film transistor shown in fig. 9, when the hole doping is performed on the region where the doped drain region is not covered by the second mask layer M2, a certain modification may also occur on the surface of the second mask layer M2 located on the frame region of the substrate base plate 10, specifically, see E in fig. 9 and E in fig. 14.
In the manufacturing process of the thin film transistor shown in fig. 9, when the second mask layer M2 is removed, the portion of the second mask layer M2 located in the edge region of the substrate base plate 10 is also removed, specifically, see F in fig. 9 and F in fig. 14.
As can be seen from the above, in the array substrate provided in the embodiment of the present invention, the design width of each unit of the gate fan-out structure is 2.0 μm +2.3 μm, which is 4.3 μm.
Compared with the prior art, in the manufacturing method of the array substrate provided by the embodiment of the invention, the grid 41 is manufactured by adopting the dry etching process, and the etching deviation of the dry etching process is relatively small, so that a wider frame does not need to be reserved for accommodating the grid fan-out structure when the grid fan-out structure is manufactured. For example: the design width of each unit of the existing gate fan-out structure is 5.5um, while the design width of each unit of the gate fan-out structure in the embodiment of the invention is 4.3 μm, which is reduced by 21.82% compared with the design width of each unit of the gate fan-out structure, and is beneficial to the narrow border of the display device.
As shown in fig. 3, an embodiment of the present invention further provides a thin film transistor, where the thin film transistor is manufactured by using the manufacturing method of the thin film transistor.
Compared with the prior art, the beneficial effects of the thin film transistor provided by the embodiment of the invention are the same as those of the thin film transistor, and are not described herein again.
The thin film transistor includes a gate 41, a first sub-doped drain portion and a second sub-doped drain portion, wherein a line width direction of the gate 41, a line length direction of the first sub-doped drain portion 221 and a line length direction of the second sub-doped drain portion 222 are the same (a left-right direction of fig. 3); the orthographic projection of the first sub-doped drain part 221 on the substrate base plate 10 and the orthographic projection of the second sub-doped drain part 222 on the substrate base plate 10 are positioned at two sides of the orthographic projection of the grid 41 on the substrate base plate 10, the line width of the grid 41 is 3.0-3.5 mu m, and the line length of the first sub-doped drain part 221 and the line length of the second sub-doped drain part 222 are both larger than or equal to 0.75 mu m.
As shown in fig. 13, the present invention further provides an array substrate, which includes a thin film transistor array located in a display area, where the thin film transistor array includes at least one thin film transistor.
Compared with the prior art, the beneficial effects of the array substrate provided by the embodiment of the invention are the same as the manufacturing method of the thin film transistor, and are not repeated herein.
As shown in fig. 13, the array substrate further includes a gate fan-out structure in the frame region, the gate fan-out structure includes a plurality of gate leads 42, wherein,
the line width of at least one grid lead 42 is W, the distance between two adjacent grid leads 42 is S, and W + S is less than 5.5 um-5.7 um.
As shown in fig. 3 and 13, a display device according to an embodiment of the present invention includes the array substrate.
Compared with the prior art, the display device provided by the embodiment of the invention has the same beneficial effects as the thin film array substrate, and the details are not repeated herein.
The display device provided in the above embodiments may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, or a navigator.
In the foregoing description of embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (14)
1. A method for manufacturing a thin film transistor includes:
forming a polycrystalline silicon material layer on the surface of the substrate base plate;
forming a first mask layer above the polycrystalline silicon material layer, so that the orthographic projection of the first mask layer on the polycrystalline silicon material layer covers a partial area of the polycrystalline silicon material layer;
processing the polycrystalline silicon material layer under the mask of the first mask layer to form a doped drain region;
forming a second mask layer above the doped drain region far from the substrate and above the first mask layer far from the substrate, so that the orthographic projection of the second mask plate in the doped drain region covers a partial region of the doped drain region, and the line width direction of the second mask layer is the same as the line length direction of the doped drain region;
and carrying out hole doping on the region of the doped drain region which is not covered by the orthographic projection of the second mask plate in the doped drain region under the mask of the second mask layer, so that a hole doped part and a doped drain part are formed in the doped drain region.
2. The method of claim 1, wherein after the forming of the polysilicon layer on the surface of the substrate base plate and before the forming of the first mask layer over the polysilicon layer, the method further comprises:
and forming an insulating layer on the surface of the polycrystalline silicon material layer far away from the substrate base plate.
3. The method of claim 2, wherein the forming a first mask layer over the layer of polysilicon material comprises:
forming a grid electrode on the surface of the insulating layer far away from the substrate base plate by adopting a composition process, wherein the grid electrode is a first mask layer;
the forming of the second mask layer above the doped drain region away from the substrate base plate and above the first mask layer away from the substrate base plate comprises:
and forming a second mask layer on the surface of the insulating layer far away from the doped drain region and the surface of the grid far away from the insulating layer.
4. The method for manufacturing a thin film transistor according to claim 2,
the forming a first mask layer over the layer of polysilicon material comprises:
forming a first mask layer serving as a first mask layer on the surface, far away from the polycrystalline silicon material, of the insulating layer, so that the orthographic projection of the first mask layer on the polycrystalline silicon material layer covers a partial area of the polycrystalline silicon material layer; the forming of the second mask layer above the doped drain region away from the substrate base plate and above the first mask layer away from the substrate base plate comprises:
forming a second mask layer on the surface of the insulating layer far away from the doped drain region and the surface of the first mask layer far away from the insulating layer;
after the hole doping is performed on the region, which is not covered by the orthographic projection of the second mask plate in the doped drain region, of the doped drain region under the mask of the second mask layer, the manufacturing method of the thin film transistor further comprises the following steps:
and removing the first mask layer and the second mask plate, and forming a grid on the surface of the insulating layer far away from the substrate by adopting a composition process.
5. The method of claim 1, wherein the forming a first mask layer over the layer of polysilicon material comprises:
forming a first mask layer on the surface of the polycrystalline silicon material layer, which is far away from the substrate base plate, so that the orthographic projection of the first mask layer on the polycrystalline silicon material layer covers a partial area of the polycrystalline silicon material layer;
processing the polysilicon material layer under the mask of the first mask layer to form a doped drain region comprises:
processing the polycrystalline silicon material layer under the mask of the first mask layer to form a doped drain region;
the forming of the second mask layer above the doped drain region away from the substrate base plate and above the first mask layer away from the substrate base plate comprises:
forming a second mask layer on the surface of the doped drain region far away from the substrate and the surface of the first mask layer far away from the substrate;
after the hole doping is performed on the region, which is not covered by the orthographic projection of the second mask plate in the doped drain region, of the doped drain region under the mask of the second mask layer, the manufacturing method of the thin film transistor further comprises the following steps:
removing the first mask layer and the second mask layer;
forming an insulating layer on the surface of the hole doping part far away from the substrate and the surface of the doping drain part far away from the substrate, so that the insulating layer covers the substrate in the orthographic projection of the substrate;
and forming a gate on the surface of the insulating layer far away from the substrate by adopting a patterning process.
6. The method for manufacturing a thin film transistor according to any one of claims 3 to 5,
the forming of the gate on the surface of the insulating layer away from the substrate by using the patterning process comprises:
forming a metal layer on the surface of the insulating layer far away from the polycrystalline silicon material layer;
forming a third mask layer on the surface of the metal layer, which is far away from the insulating layer, so that the orthographic projection of the third mask layer on the metal layer covers a partial area of the metal layer;
and carrying out dry etching treatment on the metal layer under the mask of the third mask layer to form a grid.
7. The method for manufacturing a thin film transistor according to any one of claims 1 to 5,
the difference between the line width of the first mask layer and the line width of the second mask layer is larger than 1.5 mu m; and/or the presence of a gas in the gas,
the doped drain electrode part comprises a first sub-doped drain electrode part and a second sub-doped drain electrode part, the orthographic projection of the first sub-doped drain electrode part on the substrate and the orthographic projection of the second sub-doped drain electrode part on the substrate are located on two sides of the orthographic projection of the grid electrode on the substrate, and the line length of the first sub-doped drain electrode part and the line length of the second sub-doped drain electrode part are both larger than one half of the difference between the line width of the first mask layer and the line width of the second mask layer.
8. A manufacturing method of an array substrate is characterized by comprising the following steps:
manufacturing a plurality of thin film transistors positioned in a display area on the surface of a substrate base plate; a method of manufacturing a thin film transistor array of a plurality of thin film transistors as claimed in any one of claims 1 to 6.
9. The method for manufacturing the array substrate according to claim 8, wherein when the thin film transistor array is formed on the surface of the substrate, the method further comprises:
forming a plurality of grid leads forming a grid fan-out structure on the surface of the substrate base plate, wherein the grid fan-out structure is positioned in a frame area; wherein,
the line width of each grid lead is W, the distance between two adjacent grid leads is S, and W + S is less than 5.5 um-5.7 um.
10. A thin film transistor, which is manufactured by the method for manufacturing a thin film transistor according to any one of claims 1 to 6.
11. The thin film transistor of claim 10, wherein the thin film transistor comprises a gate electrode, a first sub-doped drain portion and a second sub-doped drain portion, wherein an orthographic projection of the first sub-doped drain portion on the substrate base and an orthographic projection of the second sub-doped drain portion on the substrate base are located on two sides of the orthographic projection of the gate electrode on the substrate base;
the line width direction of the grid electrode, the line length direction of the first doped drain electrode part and the line length direction of the second doped drain electrode part are the same;
the line width of the grid electrode is 3.0-3.5 μm, and the line length of the first doped drain electrode part and the line length of the second doped drain electrode part are both larger than or equal to 0.75 μm.
12. An array substrate comprising a thin film transistor array in a display region, the thin film transistor array comprising at least one thin film transistor according to claim 10 or 11.
13. The array substrate of claim 12, further comprising a gate fan-out structure in a border region, the gate fan-out structure comprising a plurality of gate leads, wherein,
the line width of at least one grid lead is W, and the interval of two adjacent grid leads is S, and W + S is less than 5.5um ~ 5.7 um.
14. A display device comprising the array substrate according to claim 12 or 13.
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