CN109492740B - Voltage converter and radio frequency identification device - Google Patents

Voltage converter and radio frequency identification device Download PDF

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CN109492740B
CN109492740B CN201811332134.8A CN201811332134A CN109492740B CN 109492740 B CN109492740 B CN 109492740B CN 201811332134 A CN201811332134 A CN 201811332134A CN 109492740 B CN109492740 B CN 109492740B
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transistor
pole
signal
voltage
clock signal
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CN109492740A (en
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张盛东
雷腾腾
廖聪维
黄杰
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Peking University Shenzhen Graduate School
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only

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Abstract

The present invention relates to a voltage converter and a radio frequency identification device incorporating such a voltage converter. The voltage converter includes: a first boosting unit configured to generate a first boosted voltage signal at a first output terminal and a second boosted voltage signal at a second output terminal based on the received input signal under the influence of the first clock signal and the second clock signal; a second boost unit configured to generate a third boost signal and a fourth boost signal based on the first boost signal and the second boost signal under the influence of the first clock signal and the second clock signal. The voltage converter further includes an output unit configured to generate an output signal based on the third boost signal and the fourth boost signal. By the technical scheme, threshold voltage loss and on-resistance of the voltage converter can be reduced, and output voltage and driving capability of the voltage converter are improved.

Description

Voltage converter and radio frequency identification device
Technical Field
The invention relates to the field of integrated circuits, in particular to a direct-current voltage conversion circuit and a corresponding RFID tag.
Background
In recent years, Radio Frequency Identification (RFID) technology is increasingly widely used in the Internet of Things (IoT). A complete RFID system generally comprises an RFID tag and a reader/writer, wherein the RFID tag is a data carrier, its sensitivity affects the read/write distance of the RFID, and its cost affects whether the RFID technology can be applied on a larger scale. Conventional RFID tags are implemented using single crystal silicon technology, however, their high manufacturing cost limits the commercial application of RFID technology. For a long time, how to reduce the cost of the RFID tag is a key issue to be solved in the development process of RFID technology.
Disclosure of Invention
One aspect of the present invention provides a voltage converter that can be integrated in an RFID tag, comprising at least two voltage boosting units, wherein: a first boosting unit configured to generate a first boosted voltage signal at a first output terminal and a second boosted voltage signal at a second output terminal based on the received input signal under the influence of the first clock signal and the second clock signal; a second boost unit coupled to the first boost unit and configured to generate a third boost signal and a fourth boost signal based on the first boost signal and the second boost signal under the influence of the first clock signal and the second clock signal, wherein the second boost unit comprises: a first transistor having a first pole coupled to receive the first output, a control pole capacitively receiving the first clock signal, and a second pole capacitively receiving the second clock signal; a second transistor having a first pole coupled to receive the first output, a control pole coupled to the second pole of the first transistor, and a second pole coupled to the control pole of the first transistor. The voltage converter further includes an output unit configured to generate an output signal based on the third boost signal and the fourth boost signal.
In another aspect, the present invention further provides a radio frequency identification device, which includes: a transmitter configured to transmit a radio frequency signal; a processor configured to generate a reply signal based on the radio frequency signal; a voltage converter configured to generate a voltage signal under the influence of the radio frequency signal, wherein the voltage signal powers the processor.
By adopting the technical scheme of the invention, the driving voltage of the driving transistor is improved by adopting the capacitive coupling effect, so that the threshold voltage loss and the on-resistance on the voltage converter can be reduced, and the output voltage and the driving capability of the voltage converter are improved.
Drawings
Preferred embodiments of the present invention will now be described in further detail with reference to the accompanying drawings, in which:
FIG. 1 is a schematic diagram of a conventional two-stage voltage conversion circuit;
FIG. 2 is a schematic diagram of a voltage converting circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a voltage converting circuit according to a first embodiment of the present invention;
FIG. 4a is a timing diagram of a voltage converting circuit according to a first embodiment of the present invention;
FIG. 4b is a diagram showing an output simulation of a conventional second-order voltage conversion circuit and the voltage conversion circuit in the first embodiment;
FIG. 4c is a simulation graph of the output voltage of the conventional second-order voltage conversion circuit and the voltage conversion circuit in the first embodiment as a function of load current;
FIG. 4d is a simulation diagram of the output voltage of the conventional second-order voltage conversion circuit and the voltage conversion circuit in the first embodiment as a function of the threshold voltage;
fig. 4e is a simulation diagram of the energy conversion efficiency of the conventional second-order voltage conversion circuit and the voltage conversion circuit in the first embodiment under different load currents;
FIG. 5 is a diagram illustrating a voltage converting circuit according to a second embodiment of the present invention;
FIG. 6 is a schematic diagram of a voltage converting circuit according to a third embodiment of the present invention;
fig. 7 is an architecture diagram of an rfid device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the following detailed description, reference is made to the accompanying drawings that form a part hereof and in which is shown by way of illustration specific embodiments of the application. In the drawings, like numerals describe substantially similar components throughout the different views. Various specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to practice the teachings of the present application. It is to be understood that other embodiments may be utilized and structural, logical or electrical changes may be made to the embodiments of the present application.
The metal oxide Thin Film Transistor (TFT) technology has the advantages of high field effect mobility, small leakage current, low manufacturing cost, and the like, and may become the first choice for implementing a low-cost RFID tag circuit. Especially, metal oxide devices have high transmittance and can be processed on a flexible substrate, which is beneficial to realizing transparent and flexible RFID labels.
When the transistor is a single-gate transistor, the control electrode of the transistor refers to the gate electrode of the transistor, the first electrode can be the drain electrode or the source electrode of the transistor, and the corresponding second electrode can be the source electrode or the drain electrode of the transistor; when the transistor is a double-gate transistor, the term "first control electrode" in the present invention corresponds to one of a bottom gate or a top gate of the transistor, and "second control electrode" corresponds to the other of the bottom gate or the top gate of the transistor, the first electrode may be a drain or a source of the transistor, and the corresponding second electrode may be a source or a drain of the transistor; when the transistor is a bipolar transistor, the control electrode is the base electrode of the transistor, the first electrode may be the collector or emitter of the transistor, and the corresponding second electrode may be the emitter or collector of the transistor.
For the RFID tag circuit, the analog radio frequency front end module receives a radio frequency signal and generates a stable direct current power supply to provide working voltage for the digital control circuit and the storage circuit. Compared with a circuit prepared by a monocrystalline silicon process, the circuit such as a ring oscillator, an EEPROM and the like realized by adopting an oxide TFT technology requires higher working voltage, for example, the typical value of a high-level voltage source reaches 15V. This requires that the relatively low rf voltage obtained from the RFID antenna be boosted to a higher amplitude operating voltage by a circuit such as a voltage multiplier or charge pump. Because the distance between the RFID reader and the tag is relatively long, and the radio frequency radiation energy is not too high, how to realize the power management circuit with higher energy conversion efficiency by using the TFT becomes a key technology for designing the RFID tag.
The voltage conversion circuit generally comprises a capacitor, a transistor and other devices, and obtains a direct current output voltage with a higher amplitude value by utilizing the voltage coupling effect of the capacitor and matching with a clock signal. Most circuits based on TFT transistors adopt diode-type connection structures to realize unidirectional charge transfer and storage. The energy conversion efficiency of the voltage conversion circuit in the RFID tag has a correlation with the maximum distance over which the RFID tag can normally operate. The factors affecting the energy conversion efficiency of the voltage conversion circuit generally include the following two factors: (1) the on-resistance of the TFT transistor; (2) the TFT transistor threshold voltage is lost.
Fig. 1 is a schematic diagram of a conventional two-stage voltage conversion circuit.
Two branches are included between the input terminal VIN and the output terminal VOUT of the voltage conversion circuit, and each branch includes transistors N1, N3, N5, N7, and transistors N2, N4, N6, and N8. The overdrive voltage across the transistors determines their on-resistance and the voltage drop between the drain and the source. As can be seen from fig. 1, the number of transistors in the critical path between the input terminal VIN and the output terminal VOUT is large, the on-resistance is large, and the voltage drop is large, which results in low energy conversion efficiency and low output voltage.
To reduce the on-resistance, the overdrive voltage of the transistors or the number of transistors in the critical path can be increased on the one hand, and the size of the transistors can be increased on the other hand. However, as the size of the tft increases, the parasitic capacitance between the gate and drain of the tft increases accordingly, which makes the voltage value at which the clock signal CLKA/CLKB can be capacitively coupled to the nodes a1, a2, B1, B2 smaller. In addition, the diode-connected transistors N3, N4, N7, and N8 have threshold voltage loss during voltage transmission, which leads to a decrease in the output voltage of the voltage conversion circuit 100 and a decrease in energy conversion efficiency.
FIG. 2 is a schematic diagram of a voltage conversion circuit according to an embodiment of the invention.
As shown in fig. 2, the voltage converting circuit 200 includes a voltage boosting unit 210 and 220 and an output unit 230, wherein the voltage boosting unit 210 receives the voltage signal VIN to perform a first voltage boosting, and the voltage boosting unit 220 is used to boost the boosted voltage signal again and then output the boosted voltage signal to the output unit 230 to output a voltage signal VOUT which is boosted twice.
It is understood that in other embodiments, the voltage conversion circuit 200 may further include other numbers of boosting units connected in series to boost the received voltage signal VIN step by step.
FIG. 3 is a schematic diagram of a voltage converting circuit according to a first embodiment of the invention.
The voltage conversion circuit 300 includes boosting units 310 and 320 and an output unit 330 connected in series. Specifically, the boosting unit 310 includes symmetrically disposed transistors 311, 312, the boosting unit 320 includes symmetrically disposed transistors 321, 322, and the output unit 330 includes symmetrically disposed transistors 331, 332. The clock signal CLKA is coupled to the output terminal a1 of the voltage boosting unit 310 (i.e., the common node between the transistors 311 and 321) and the output terminal B2 of the voltage boosting unit 320 (i.e., the common node between the transistors 322 and 332) through capacitors C1, C4, respectively, and similarly, the clock signal CLKB is coupled to the output terminal a2 of the voltage boosting unit 310 (i.e., the common node between the transistors 312 and 321) and the output terminal B1 of the voltage boosting unit 320 (i.e., the common node between the transistors 321 and 331) through capacitor C2, respectively. Input terminal V of booster unit 310INFor receiving the voltage signal VDD. The output unit 330 receives a signal from the boosting unit 320, is coupled to the reference potential GND via the resistor R and the capacitor C5, and provides a stable direct voltage at a common node (i.e., an output terminal) of the transistors 331, 332.
As can be seen from fig. 3, the boosting units 310 and 320 in the voltage converting circuit 300 each include two symmetrical transistors and capacitors. By the cascade mode shown in fig. 3, the number of transistors on the critical path from the input terminal to the output terminal can be reduced, and the overdrive voltage of the transistors can be increased by controlling the thin film transistors in the booster cell with high potential. For a transistor operating in the linear region, its on-resistance ronCan be approximately expressed as:
Figure GDA0001935059640000061
where W is the channel width of the transistor, L is the channel length of the transistor, μ is the effective field effect mobility of the transistor, COXIs the capacitance per unit area, V, of the gate dielectric layer of the transistorgsIs the gate-source voltage of the transistor, VthIs the threshold voltage of the transistor. From the formula (1), when the voltage V is overdrivengs-VthWhen the resistance is increased, the on-resistance r of the thin film transistor is increasedonWill decrease accordingly, and therefore, the output voltage of the voltage conversion circuit can be expressed as:
Figure GDA0001935059640000062
wherein N is the order of the DC power conversion circuit, C is the pumping capacitance, Cs is the parasitic capacitance of the key node, ILTo output a current, ROIs an output resistor, wherein the output resistor ROCan be further expressed as:
Figure GDA0001935059640000063
where f is the frequency of the clock and T is the period of the clock. Thus, the output resistance ROClosely related to the clock frequency f and the pump capacitance C. The on resistance of the thin film transistor is reduced, the output resistance is also reduced, and the amplitude range of the output voltage of the voltage conversion circuit is favorably enlarged. In addition, as can be seen from the equation (2), the parasitic capacitance Cs and the threshold voltage loss VthThe maximum value of the output voltage is directly limited.
The voltage conversion circuit provided by the invention overcomes the threshold voltage loss of the transistor in the multi-stage boosting unit, and only the output unit 330 has the threshold voltage loss which is not increased along with the order number, so the output voltage of the voltage conversion circuit can be expressed as:
Figure GDA0001935059640000064
therefore, the voltage conversion circuit provided by the invention can improve the output voltage and the energy conversion efficiency.
FIG. 4a is a timing diagram of a voltage converting circuit according to a first embodiment of the invention. In this embodiment, the voltage VDDThe voltage amplitude of the clock signals CLKA and CLKB is 0V to 5V, and the phase difference is 180 degrees.
When the clock signal CLKA is at the low potential 0V, it is coupled to the node a1 through the capacitor C1, thereby turning off the transistor 312; when the clock signal CLKB is at the high potential of 5V, it is coupled to the node a2 through the capacitor C2, so that the transistor 311 is turned on. In this state, the low potential of the node a1 is initialized to 5V.
When the clock signal CLKA is at the high potential of 5V, it is coupled to the node a1 through the capacitor C1, thereby causing the potential of the node a1 to be pulled up to 10V (2VDD), causing the transistor 312 to be turned on; meanwhile, the clock signal CLKB is at a low level of 0V, coupled to node A2 through capacitor C2, causing transistor 311 to turn off. In this state, the low potential of the node a2 is initialized to 5V.
Therefore, since the booster cells 310 and 320 are connected in series, the output of the booster cell 310 serves as the input of the booster cell 320, and charges the nodes B1 and B2.
When the clock signal CLKA is at the low potential of 0V, it is coupled to the node B2 through the capacitor C4, so that the transistor 321 is turned off; meanwhile, the clock signal CLKB is at a high potential of 5V, coupled to the node B1 through the capacitor C3, and controls the transistor 322 to be turned on. In this state, the high potential 10V (2VDD) of the node a2 charges the node B2 through the transistor 322, so that the low potential of the node B2 is initialized to 10V (2 VDD).
When the clock signal CLKA is at the high potential of 5V, it is coupled to the node B2 through the capacitor C4, and the control transistor 321 is turned on; meanwhile, the clock signal CLKB is at a low level of 0V, coupled to node B1 through capacitor C3, causing transistor 322 to turn off. In this state, the high potential of the node a1, 10V, charges the node B1, initializing the low potential of the node B1 to 10V (2 VDD).
Through the above process, the voltage conversion circuit 300 is initialized so that the low potential of the nodes a1, a2 is 5V and the low potential of the nodes B1, B2 is 10V. In the subsequent working period, the potentials of the nodes A1 and A2 can be bootstrapped due to the capacitive coupling effect of the clock signal and change along with the change of the clock signal between 5V and 10V, and similarly, the potentials of the nodes B1 and B2 change along with the change of the clock signal between 10V and 15V.
The output unit 330 receives the signals output by the nodes B1 and B2, and alternately charges and outputs the signals through the capacitor C5.
The inventors also simulated the voltage conversion circuits 100, 300 and provided the following simulation comparison. The simulation conditions here are all load resistance of 100k Ω, and the transistor size and capacitance are the same, the threshold voltage of the TFT used for the simulation is 2.5V,
fig. 4b is a diagram showing an output simulation of the conventional second-order voltage conversion circuit and the voltage conversion circuit in the first embodiment. In the figure, a curve S1 is an output curve of the voltage conversion circuit 300, and a curve S2 is an output curve of the voltage conversion circuit 100. As can be seen from comparison of the curves S1 and S2, the output voltage of the voltage converting circuit 300 is significantly higher than the output voltage of the voltage converting circuit 100.
Fig. 4c is a simulation diagram of the output voltage of the conventional second-order voltage conversion circuit and the voltage conversion circuit in the first embodiment as a function of the load current. In the figure, a curve S3 corresponds to the voltage conversion circuit 300, and a curve S4 corresponds to the voltage conversion circuit 100. As can be seen from the figure, as the load current increases, the output voltage of the voltage conversion circuit 100 significantly decreases, and the voltage conversion circuit 300 can still output a voltage of about 18.5V when the load current is about 400 μ a, which is sufficient to drive the memory circuit EEPROM and the like in the RFID tag. Therefore, the voltage conversion circuit 300 has stronger driving capability.
Fig. 4d is a simulation diagram of the output voltage of the conventional second-order voltage conversion circuit and the voltage conversion circuit in the first embodiment as a function of the threshold voltage. In the figure, a curve S5 corresponds to the voltage conversion circuit 300, and a curve S6 corresponds to the voltage conversion circuit 100. As can be seen from the figure, the output voltage of the voltage conversion circuit 100 significantly decreases when the amount of threshold voltage shift is positive, whereas the output voltage of the voltage conversion circuit 300 does not significantly decrease when the amount of threshold voltage shift is-6 to + 2V. As described above, the threshold voltage of the TFT used in the simulation is 2.5V, and when the threshold voltage shifts by +2V, the threshold voltage of the transistor is significantly biased, and the output voltage drop caused by the loss of the threshold voltage is dominant, so that the transistor connected in the form of a diode in the voltage conversion circuit 100 causes the output voltage to drop significantly. In contrast, the voltage conversion circuit 300 has a loss of the threshold voltage only in the output unit, and the influence of the threshold voltage on the output voltage is greatly improved.
Fig. 4e is a simulation diagram of the energy conversion efficiency of the conventional second-order voltage conversion circuit and the voltage conversion circuit in the first embodiment under different load currents. In the figure, a curve S7 corresponds to the voltage conversion circuit 300, and a curve S8 corresponds to the voltage conversion circuit 100. As can be seen, the intersection of the curve S7 and the curve S8 corresponds to a load current of 315 microamps. When the load current is less than 315 microampere, the energy conversion efficiency of the voltage conversion circuit 100 is slightly higher than that of the voltage conversion circuit 300, and when the load current is greater than 315 microampere, the opposite is true. For example, when the driving current of the voltage conversion circuit 300 is 400 microamperes, the output voltage is 18.5V, and the energy conversion efficiency reaches 45%. In addition, when the load current is too large or too small, the energy conversion efficiency of the voltage conversion circuit 100 is decreased, and the energy conversion efficiency of the voltage conversion circuit 300 is increased, so that the voltage conversion circuit 300 has strong driving capability and higher energy utilization rate.
FIG. 5 is a diagram illustrating a voltage converting circuit according to a second embodiment of the present invention.
Compared to the first embodiment, an isolation unit 540 is also connected in series between the two boosting units 510 and 520 of the present embodiment. As shown, the boosting unit 510 includes symmetrically disposed transistors 511, 512, the boosting unit 520 includes symmetrically disposed transistors 521, 522, the output unit 530 includes symmetrically disposed transistors 531, 532, and the isolation unit 540 includes symmetrically disposed transistors 541, 542.
Specifically, a first pole of transistor 541 is coupled between the second pole of transistor 511 and a first pole of transistor 521, a first pole of transistor 542 is coupled between the second pole of transistor 512 and a first pole of transistor 522, the second poles of transistors 541 and 542 are connected, and the control poles of transistors 541 and 542 are coupled to the control poles of transistors 521 and 522, respectively.
When the clock signal CLKA is at the low potential 0V, the node a1 is at the low potential, so that the transistor 512 is turned off; meanwhile, the clock signal CLKB is high at 5V, so that the node a2 is high, and the transistor 511 is controlled to be turned on. In this state, the low potential of the node a1 is initialized to 5V.
When the clock signal CLKA is at the high potential of 5V, the potential of the node a1 is bootstrapped to the high potential of 10V, controlling the transistor 512 to turn on; meanwhile, the clock signal CLKB is at the low potential of 0V, and the transistor 511 is turned off. In this state, the power supply VDD charges the node a2, and the low potential of a2 is initialized to 5V.
The low potential of the output terminals B1, B2 of the boosting unit 520 is initialized by the isolation unit 540 of the node a1 or a 2:
when the clock signal CLKA is at the low potential of 0V, the node B2 is at the low potential, so that the transistors 521 and 541 are turned off; meanwhile, the clock signal CLKB is high at 5V, and the node B1 is high, so that the transistors 522 and 545 are turned on. In this state, the node a2 charges the node B2, and the low potential of the node B2 is initialized to 10V.
When the clock signal CLKA is at a high voltage level of 5V, the voltage level at the node B2 is 15V, so that the transistors 521 and 541 are turned on; meanwhile, the clock signal CLKB is at the low level 0V, and the node B1 is at the low level, so that the transistors 522 and 542 are turned off. In this state, the node a1 charges the node B1, and the low potential of B1 is initialized to 10V.
Through the above process, the voltage conversion circuit 400 is initialized so that the low potential of the nodes a1, a2 is 5V and the low potential of the nodes B1, B2 is 10V. In the subsequent working period, the potentials of the nodes A1 and A2 change with the change of the clock signal between 5V and 10V, and the potentials of the nodes B1 and B2 change with the change of the clock signal between 10V and 15V.
Please continue to refer to fig. 5. When CLKA is high, the potentials of the nodes B1 and B2 are 10V and 15V, respectively, and at this time, the transistor 541 is turned on, so that the first electrode of the transistor 522 is 10V and the second electrode is 15V, and is in an off state. Thus, node B2 can only leak in the reverse direction by the leakage current of the transistor 522 that is turned off, and for transistors with negative threshold voltages, the reverse leakage current IleakThe size is as follows:
Figure GDA0001935059640000101
where μ is the channel surface mobility, Cox is the gate oxide capacitance per unit area, W is the effective channel width, and L is the effective channel length. Therefore, with the above arrangement, the transistor 522 can be made to be in the off state, and the reverse leakage current I discharging the node B2 can be made to occurleakLess than the leakage current of transistor 522 in saturation, thereby reducing the leakage current I due to reverseleakThe resulting voltage drop increases the range of output voltages.
As can be seen from the above, the isolation unit 540 can reduce the reverse leakage of the two transistors of the voltage boost unit 520, and reduce the voltage ripple output by the output unit 530.
FIG. 6 is a schematic diagram of a voltage converting circuit according to a third embodiment of the invention.
Compared to the first embodiment, the transistors in the voltage converting circuit 600 in this embodiment are dual-gate transistors. Specifically, the boosting unit 610 includes two symmetrical transistors 611, 612, and Bottom Gates (BG) of the two transistors are cross-connected to output terminals a2, a1 of the boosting unit 610, respectively, and Top Gates (TG) are connected to an input terminal VIN (i.e., power supply VDD), respectively. The clock signals CLKA, CLKB are coupled to nodes a1, a2 via capacitors C1, C2, respectively.
Similarly, the bottom gates of transistors 621, 622 in the boost unit 620 are cross-coupled to the output terminals B2, B1 of the boost unit, and the top gates are coupled to clock signals CLKA, CLKB, respectively. The clock signal CLKA is coupled to the node B2 through a capacitor C4 and the clock signal CLKB is coupled to the node B1 through a capacitor C3.
The output unit 630 includes symmetrically arranged transistors 631, 632 having bottom gates coupled to nodes B1, B2, respectively, and top gates coupled to clock signals CLKB, CLKA, respectively.
Similar to the first embodiment, the low potential of the nodes a1 and a2 is initialized to 5V, and since the top gate potentials of the transistors 611 and 612 are VDD, the threshold voltages of the transistors 611 and 612 can be adjusted to be negative, so that the transistors can be completely turned on and the power voltage VDD can be transmitted to the node a1 or a2 without loss.
Also similar to the first embodiment, the low potential of both the nodes B1, B2 is initialized to 10V. In the initialization process, when the clock signal CLKA is at the low potential of 0V, the transistor 621 is turned off, and the clock signal CLKA makes the top gate of the transistor 621 be at the low potential, so as to adjust the threshold voltage of the transistor 621 to be floating, which is beneficial to turning off the transistor 621. Meanwhile, the clock signal CLKB is at a high potential of 5V, the node B1 is at a high potential, the transistor 622 is turned on, and the top gate of the transistor 622 controlled by the clock signal CLKB is at a high potential, so that the threshold voltage of the transistor 622 is floated negatively, which is beneficial to turning on the transistor 622.
Similarly, when the clock signal CLKA is at a high potential of 5V, the top gate of the transistor 621 is at a high potential, so that the transistor 621 is floated negatively, which is favorable for turning on the transistor 621. The clock signal CLKB causes the top gate of the transistor 622 to be at a low potential, which causes the threshold voltage of the transistor 622 to be floating, facilitating the turn-off of the transistor 622.
From the above, the clock signal is coupled to the top gate of the transistor, so that the threshold voltage of the transistor can be adjusted, the transistor can be completely turned on and off when the threshold voltage is biased positive and biased negative, the problems of charge reverse distribution and threshold voltage loss in the voltage conversion circuit are avoided, and the output voltage is increased.
It is understood that the double-gate transistors 611 and 612 in the voltage boosting unit 610 can also be replaced by single-gate thin film transistors, thereby avoiding the problem of reverse leakage that may be caused by the negative threshold voltage of the transistors, and meanwhile, there is no loss of threshold voltage.
In another embodiment, the top gates of the dual-gate transistors 611, 612 in the voltage boosting unit 610 are coupled to the clock signals CLKB, CLKA, respectively, so that the transistors in the voltage boosting units 610, 620 can use the same dynamic voltage regulation manner, thereby turning on and off the dual-gate transistors 611, 612 more fully.
Similar to voltage converting circuit 500, voltage converting circuit 600 may also include an isolation cell (not shown), and accordingly, the top gates of the symmetrically disposed transistors in the isolation cell are capacitively coupled to their own first poles, respectively, i.e., receive clock signals CLKA, CLKB, respectively. It can be understood that in practical application, the top gate and the bottom gate as two control electrodes of the transistor can be replaced with each other as required without affecting the circuit function.
According to various embodiments, the voltage conversion circuit of the present application may include two or more boosting units according to boosting requirements.
The voltage conversion circuit provided by the invention utilizes the voltage bootstrap effect to control whether the transmission transistor is opened or not, thereby avoiding the loss of threshold voltage in the traditional voltage conversion circuit and increasing the output voltage.
The invention also provides a radio frequency identification device comprising the voltage conversion circuit. Fig. 7 is an architecture diagram of an rfid device according to an embodiment of the present invention.
As shown, the RFID device 700 includes a transmitter 710 for receiving the RFID signal, a processor 720 for generating a reply signal based on the RFID signal, and a voltage converter 730. In particular, the voltage converter 730 generates a voltage signal under the influence of the radio frequency signal to power the processor 720.
In one embodiment, the processor 720 further includes a frequency divider 721 for generating clock signals, such as the first clock signal CLKA and the second clock signal CLKB, required for the operation of the voltage converter 730 based on the rf signal.
The above embodiments are provided only for illustrating the present invention and not for limiting the present invention, and those skilled in the art can make various changes and modifications without departing from the scope of the present invention, and therefore, all equivalent technical solutions should fall within the scope of the present invention.

Claims (9)

1. A voltage converter comprising at least two voltage boosting units, wherein:
a first boost unit (310) configured to generate a first boost signal at a first output and a second boost signal at a second output based on the received input signal under the influence of a first clock signal and a second clock signal;
a second boost unit (320), coupled to the first boost unit (310), configured to generate a third boost signal and a fourth boost signal based on the first boost signal and the second boost signal under the influence of the first clock signal and the second clock signal, wherein the second boost unit comprises:
a first transistor (321) having a first pole coupled to receive the first output, a first control pole capacitively receiving the first clock signal, and a second pole capacitively receiving the second clock signal;
a second transistor (322) having a first pole coupled to receive the second output, a first control pole coupled to the second pole of the first transistor, and a second pole coupled to the first control pole of the first transistor; and
an output unit (330) configured to generate an output signal based on the third boost signal and the fourth boost signal;
an isolation unit coupled between the first boosting unit and the second boosting unit to suppress a reverse leakage current of the second boosting unit, and a first pole of the first transistor and a first pole of the second transistor are coupled to the first output terminal and the second output terminal, respectively, via the isolation unit.
2. The voltage converter of claim 1, wherein the first boost unit comprises:
a third transistor (311) and a fourth transistor (312), wherein a first pole of the third transistor and a first pole of the fourth transistor are configured to receive the input signal, and a second pole of the third transistor is coupled to a first control pole of the fourth transistor and capacitively receives the first clock signal, and a second pole of the fourth transistor is coupled to a first control pole of the third transistor and capacitively receives the second clock signal.
3. The voltage converter of claim 2, wherein the first transistor and the second transistor are bipolar transistors, wherein a second control electrode of the first transistor receives the first clock signal and a second control electrode of the second transistor receives the second clock signal.
4. The voltage converter of claim 3, wherein the third transistor and the fourth transistor are bipolar transistors, wherein a second control electrode of the third transistor and a second control electrode of the fourth transistor are configured to receive the input signal.
5. The voltage converter of claim 1, wherein the output unit comprises:
a fifth transistor (331) having a first pole and a first control pole both coupled to the second pole of the second transistor; and
a sixth transistor (332) having a first pole and a first control pole both coupled to the second pole of the first transistor, and a second pole of the sixth transistor and the second pole of the fifth transistor capacitively coupled to a common potential.
6. The voltage converter of claim 5, wherein the fifth transistor (331) and the sixth transistor (332) are bipolar transistors, a second gate of the fifth transistor receiving the second clock signal and a second gate of the sixth transistor receiving the first clock signal.
7. The voltage converter of claim 1, wherein the isolation unit further comprises:
a seventh transistor (541) having a first pole coupled to the first output, a first control pole coupled to the first control pole of the first transistor, and a second pole coupled to the first pole of the first transistor; and
an eighth transistor (542) having a first pole coupled to the second output, a first control pole coupled to the first control pole of the second transistor, and a second pole coupled to the first pole of the second transistor.
8. The voltage converter of claim 7, wherein the seventh transistor and the eighth transistor are bipolar transistors, a second gate of the seventh transistor receives the first clock signal, and a second gate of the eighth transistor receives the second clock signal.
9. A radio frequency identification device comprising:
a transmitter configured to transmit a radio frequency signal;
a processor configured to generate a reply signal based on the radio frequency signal;
the voltage converter of any one of claims 1 to 8, configured to generate the output signal under the influence of the radio frequency signal, wherein the output signal powers the processor;
the processor further comprises:
a frequency divider configured to generate the first clock signal and the second clock signal based on the radio frequency signal.
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