CN109474554A - A kind of PR-ASK modulator approach and device - Google Patents
A kind of PR-ASK modulator approach and device Download PDFInfo
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Abstract
The present invention provides a kind of PR-ASK modulator approach and device, to realize baseband signal in PR-ASK modulated process can flexible configuration according to demand technical effect.Method includes: that FPGA receives binary initial data code stream that controller is sent；Binary initial data code stream is converted to the first binary code stream of single bit；The CRC code for obtain after CRC calculating for first binary code stream is added in first binary code stream, the second binary code stream is obtained；PIE coding and bipolar coding are carried out to second binary code stream, generate third binary code stream；Molding filtration processing is carried out to the third binary code stream, generates initial baseband signal；Waveform adjustment is carried out to the initial baseband signal, baseband signal is generated and exports.
Description
Technical field
The present invention relates to electronic technology field, in particular to a kind of PR-ASK modulator approach and device.
Background technique
Radio frequency identification (Radio Frequency Identification, RFID) is a kind of wireless communication technique, can be with
Specific objective is identified by radio signals and reads and writes related data, it is mechanical without being established between identifying system and specific objective
Or optical contact.RFID system includes RF tag and RFID reader, makes RF tag in certain distance using electromagnetic wave
It is interior by RFID reader automatic identification.
In the agreement of ISO/IEC 18000-6C, it is mentioned in three kinds of transmitting signal modulations about RFID reader
Hold, is DSB_ASK, SSB_ASK and PR_ASK respectively.Wherein, PR_ASK and DSB_ASK, SSB_ASK modulated RF envelope phase
Than, the pulse width of the modulated RF envelope of PR_ASK is narrow very much, i.e. the low energy transmission time of the modulation system want it is short very much.
Under identical transmission power, PR_ASK preferably can provide carrier energy for label, to make between reader and label
Interaction distance it is farther.
Realize that PR-ASK modulation mainly uses the scheme of CPU+RFID chip in RFID card reader in the prior art,
For CPU according to needing to send RFID instruction to RFID chip, RFID chip carries out coded modulation to instruction.In this scheme,
It is integrated with mature encoding and decoding radio frequency system in RFID chip, can be realized the quick application integration of system, but due to RFID
The encoding and decoding specification and encoding and decoding performance of RFID are had cured in chip, thus are difficult to verify or upgrade novel coding and decoding scheme, nothing
Method meets the application scenarios such as on-line debugging, system upgrade to the adjustment demand of baseband signal.
Summary of the invention
The embodiment of the present invention provides a kind of PR-ASK modulator approach and device, to realize base band in PR-ASK modulated process
Signal can flexible configuration according to demand technical effect.
In a first aspect, the embodiment of the present invention provides a kind of PR-ASK modulator approach, it is applied in FPGA, the method packet
It includes:
Receive binary initial data code stream that controller is sent；
Binary initial data code stream is converted to the first binary code stream of single bit；
The CRC code for obtain after cyclic redundancy check (CRC) calculating for first binary code stream is added to institute
It states in the first binary code stream, obtains the second binary code stream；
Pulsewidth coding PIE coding and bipolar coding are carried out to second binary code stream, generate the three or two into
Code stream processed；
Molding filtration processing is carried out to the third binary code stream, generates initial baseband signal；
Waveform adjustment is carried out to the initial baseband signal, baseband signal is generated and exports.
In the above scheme, PR-ASK modulated process is completely implemented inside FPGA.Since FPGA is a kind of integrated level
Very high novel high-performance programmable chip, internal circuit function are programmable, it may be verified that or the novel encoding and decoding side of upgrading
Case, baseband signal can carry out flexibly encoding configuration according to demand in PR-ASK modulated process, so meet well on-line debugging,
Adjustment demand of the special applications such as system upgrade scene to baseband signal.
Optionally, after carrying out PIE coding to second binary code stream, further includes:
Binary code stream after being encoded according to PIE generates replacement indication signal, to indicate to need in the initial baseband signal
Position where signal to be replaced；
It is described that waveform adjustment is carried out to the initial baseband signal, comprising:
The position where the signal for needing to be replaced in the initial baseband signal is determined according to the replacement indication signal,
And the signal for needing to be replaced in the initial baseband signal is replaced using template signal.
Present embodiment, after the completion of PIE coding, the binary code stream after directly being encoded according to PIE generates replacement instruction
Signal indicates the position for the signal for needing to be replaced in initial baseband signal so that subsequent baseband signal generate after, can directly according to
The signal section for needing to be replaced in initial baseband signal is replaced according to the instruction of replacement indication signal, replacement process does not produce
Raw delay, real-time are high.
Optionally, the position where the signal for needing to be replaced in the initial baseband signal specifically: the just primordium
Position corresponding with the failing edge hopping part of binary code stream after PIE coding in band signal.
The failing edge hopping part of binary code stream after present embodiment is encoded according to PIE determines in initial baseband signal
The position for the signal for needing to be replaced, signal generation delay is small, and real-time is good.
Optionally, the FPGA is configured with the first register and the second register, wherein first register is for depositing
Binary initial data code stream is put, second register is used to indicate CRC calculation；
Before binary initial data code stream is converted to the first binary code stream of single bit, the method
Further include:
When the binary initial data code stream stored in detecting first register changes, from described
Binary initial data code stream after variation is read in one register；
It is described that CRC calculating is carried out to first binary code stream, it specifically includes:
CRC calculating is carried out to first binary code stream according to the CRC calculation of second register instruction.
Present embodiment configures the first register and the second register in FPGA, is respectively used to store binary original number
According to code stream and instruction CRC calculation, so that signal processing is more efficient, strong flexibility.
Optionally, the FPGA is configured with third register, and the third of the length and duty ratio that are used to indicate PIE coding is posted
Storage；
It is described that PIE coding is carried out to second binary code stream, it specifically includes:
Second binary code stream is carried out according to the length of the PIE coding of third register instruction and duty ratio
PIE coding.
Present embodiment, can be real by the third register of configuration instruction PIE is encoded in FPGA length and duty ratio
The length of existing PIE coding and the flexible configuration of duty ratio, the baseband signal programmability for being worth ultimately generating is strong, can be cleverer
Reply on-line debugging demand and application of special occasions demand living.
Second aspect, the embodiment of the present invention provide a kind of PR-ASK modulating device, are applied in FPGA, comprising:
CRC computing module, for receiving binary initial data code stream of controller transmission；By binary original
Beginning data code flow is converted to the first binary code stream of single bit；CRC calculating is carried out to the binary code stream of the list bit, by needle
The CRC code that obtains is added in first binary code stream after carrying out CRC calculating to first binary code stream, obtains the
Two binary code streams；
Coding module, for carrying out PIE coding and bipolar coding to second binary code stream, generate the three or two into
Code stream processed；
Raised cosine roll off filter module carries out molding filtration processing to the third binary code stream, generates initial base band
Signal；
Waveform adjusts module, for carrying out waveform adjustment to the initial baseband signal, generates baseband signal and exports.
Optionally, the coding module is also used to:
Binary code stream after being encoded according to PIE generates replacement indication signal, to indicate to need in the initial baseband signal
Position where signal to be replaced；
The waveform adjustment module is specifically used for: determining that the initial base band is believed according to the instruction of the replacement indication signal
Position where the signal for needing to be replaced in number, and using template signal in the initial baseband signal needing to be replaced
Signal is replaced.
Optionally, the position where the signal for needing to be replaced in the initial baseband signal specifically: the just primordium
Position corresponding with the failing edge hopping part of binary code stream after PIE coding in band signal.
Optionally, the FPGA further includes communication configuration module, is used for:
It is configured to store the first register of the initial data code stream for the CRC computing module, is used to refer to CRC
Second register of calculation；
The CRC computing module is specifically used for: the binary original number stored in detecting first register
When changing according to code stream, binary initial data code stream after reading variation in first register, and will be described
Binary initial data code stream is converted to the first binary code stream of single bit；According to the CRC meter of second register instruction
Calculation mode carries out CRC calculating to first binary code stream, and the CRC code being calculated is added to first binary code
In stream, the second binary code stream is obtained.
Optionally, the communication configuration module is also used to:
The length of instruction PIE coding and the third register of duty ratio are configured to for the coding module；
The coding module is specifically used for: according to the length and duty ratio pair of the PIE coding of third register instruction
Second binary code stream carries out PIE coding.
Optionally, the communication configuration module is also used to: being configured to instruction filter for the raised cosine roll off filter module
4th register of wave device configuration parameter.
Optionally, the communication configuration module is also used to: being adjusted module for the waveform and is configured to storage template signal
The 5th register.
The one or more technical solutions provided in the embodiment of the present invention, have at least the following technical effects or advantages:
PR-ASK modulated process is completely implemented inside FPGA by technical solution of the embodiment of the present invention.Since FPGA is a kind of
The very high novel high-performance programmable chip of integrated level, internal circuit function is programmable, it may be verified that or the novel volume of upgrading
Decoding scheme, baseband signal can carry out flexibly encoding configuration according to demand in PR-ASK modulated process, and then meet well
Adjustment demand of the special applications scenes such as line debugging, system upgrade to baseband signal.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly introduced, it should be apparent that, drawings in the following description are only some embodiments of the invention, for this
For the those of ordinary skill in field, without any creative labor, it can also be obtained according to these attached drawings
His attached drawing.
Fig. 1 is the schematic diagram sent before being realized in the prior art based on CPU+RFID to instruction；
Fig. 2 is the schematic diagram sent before being realized in the prior art based on CPU+DAC to instruction；
Fig. 3 is the flow chart of PR-ASK modulator approach in the embodiment of the present invention；
Fig. 4 is a kind of possible application scenarios schematic diagram of PR-ASK modulator approach in the embodiment of the present invention；
Fig. 5 is the structural schematic diagram of PR-ASK modulating device in the embodiment of the present invention；
Fig. 6 is the structural schematic diagram of PR-ASK modulating device in the embodiment of the present invention；
Fig. 7 is the structural schematic diagram of CRC computing module 21 in the embodiment of the present invention；
Fig. 8 is the structural schematic diagram of coding module 22 in the embodiment of the present invention；
Fig. 9 is the register configuration schematic diagram of PIE coding in the embodiment of the present invention；
Figure 10 is PIE coding schematic diagram in the embodiment of the present invention；
Figure 11 is the waveform diagram of bipolarity conversion front and back in the embodiment of the present invention；
Figure 12 is the schematic diagram of initial baseband signal in the embodiment of the present invention；
Figure 13 is the schematic diagram that replacement indication signal is generated in the embodiment of the present invention；
Figure 14 is the structural schematic diagram of raised cosine roll off filter module 24 in the embodiment of the present invention；
Figure 15 is the structural schematic diagram of FIR filter in the embodiment of the present invention；
Figure 16 is the schematic diagram of initial baseband signal and replacement indication signal in the embodiment of the present invention；
Figure 17 is the schematic diagram for carrying out signal replacement in the embodiment of the present invention to initial baseband signal using template signal；
Preceding and waveform diagram adjusted is adjusted in Figure 18 embodiment of the present invention for baseband signal waveform.
Specific embodiment
Technical solution of the present invention is described in detail below by attached drawing and specific embodiment, it should be understood that the present invention
Specific features in embodiment and embodiment are the detailed description to technical solution of the present invention, rather than to the technology of the present invention
The restriction of scheme, in the absence of conflict, the technical characteristic in the embodiment of the present invention and embodiment can be combined with each other.
It is to be appreciated that in the description of the embodiment of the present invention, the vocabulary such as " first ", " second " are only used for distinguishing and retouch
The purpose stated, is not understood to indicate or imply relative importance, can not be interpreted as indication or suggestion sequence.In the present invention
In the description of embodiment " multiple ", refer to two or more.
Term "and/or" in the embodiment of the present invention, a kind of only incidence relation for describing affiliated partner, expression can be with
There are three kinds of relationships, for example, A and/or B, can indicate: individualism A exists simultaneously A and B, these three feelings of individualism B
Condition.In addition, character "/" herein, typicallys represent the relationship that forward-backward correlation object is a kind of "or".
Currently, to instruction transmission, there are two types of schemes before realizing in RFID card reader: one is based on CPU+RFID chip
Scheme, CPU are transmitted to RFID chip and carry out coding and be directly sent to RFID mark by antenna according to the instruction for needing to send
Label；One is the scheme for being based on CPU+ digital analog converter (Digital to Analog Converter, DAC) chip, CPU is needed
Modulation code stream is generated according to the instruction of transmission, be re-fed into DAC chip, generated RFID signal；Following scheme with before RFID to biography
It is input into row for example:
1) it is based on CPU+RFID chip solution:
Referring to Fig.1, system is based on arm processor S3C2410 (chip model)+AS3991 (model of chip) and realizes superelevation
Frequency RFID card reader.ARM S3C2410 is controlled as master cpu sends RFID instruction, and AS3991 receives CPU communication instruction, adjusts
It is sent after system.
It is integrated with mature encoding and decoding radio frequency system in this scheme, in RFID chip, can be realized the quick of system
Application integration, but due to having cured RFID encoding and decoding specification and encoding and decoding performance in chip, so can not verify or upgrade novel
Coding and decoding scheme faces following certain special applications scenes, can not meet the needs of coding flexible configuration in time.
2) it is based on CPU+DAC chip solution:
Referring to Fig. 2, system is based on X86 system+monolithic system+AD9122 (ADI DAC chip model) and realizes hyperfrequency
To transmission encryption algorithm verification platform before RFID.X86 carries out coded modulation to the RFID instruction that needs are sent as master cpu,
Code stream is formed, then by communication interface, code stream is sent to monolithic system, monolithic system controls DAC chip and carries out digital-to-analogue turn
After changing, it is sent to outer antennas circuit.
It is more demanding to CPU computing capability in this scheme, refer to if can not be issued within the time as defined in standard
It enables, then Communications failure can occur, and the scheme practical application of CPU+DAC chip is fewer, unidirectionally be calculated generally as project's earlier stage
Method verifying uses.
In order to solve the above technical problem of the existing technology, the embodiment of the present invention provides a kind of PR-ASK modulation methods
Method is applied in field programmable gate array (Field-Programmable Gate Array, FPGA), referring to Fig. 3, the party
Method specifically includes:
S101:FPGA receives binary initial data code stream that controller is sent；
Binary initial data code stream is converted to the first binary code stream of single-bit (bit) by S102:FPGA；
S103:FPGA will carry out cyclic redundancy check (Cyclic redundancy for first binary code stream
Check, CRC) calculate after the CRC code that obtains be added in first binary code stream, obtain the second binary code stream；
S104:FPGA carries out pulsewidth coding (Pulse interval to second binary code stream
Encoding, PIE) and bipolar coding, generate third binary code stream；
S105:FPGA carries out molding filtration processing to the third binary code stream, generates initial baseband signal；
S106:FPGA carries out waveform adjustment to the initial baseband signal, generates baseband signal and exports.
Fig. 4 is a kind of possible application scenarios schematic diagram of PR-ASK of embodiment of the present invention modulator approach, controller in Fig. 4
01 for sending binary initial data code stream to FPGA02, and FPGA02 carries out PR-ASK to binary initial data code stream
Modulation generates baseband signal.
In the specific implementation process, controller 01 and FPGA02 can be integrated in a physical entity, be also possible to
It separately designs in two different object entities, the embodiment of the present invention is not particularly limited.Controller 01, which can be, to be had
The arbitrary equipment or device of central processor (Central Processing Unit, CPU) processing function, such as arm processor,
The embodiment of the present invention is not particularly limited.
PR-ASK modulated process is completely implemented inside FPGA by the embodiment of the present invention, since FPGA is a kind of integrated level
Very high novel high-performance programmable chip, internal circuit function are programmable, it may be verified that or the novel encoding and decoding side of upgrading
Case, baseband signal can carry out flexibly encoding configuration according to demand in PR-ASK modulated process, so meet well on-line debugging,
Adjustment demand of the special applications such as system upgrade scene to baseband signal.
Optionally, after carrying out PIE coding to the second binary code stream, further includes:
Binary code stream after being encoded according to PIE generates replacement indication signal, with indicate to need in initial baseband signal by
Position where the signal of replacement；
Waveform adjustment is carried out to initial baseband signal, comprising:
The position where the signal for needing to be replaced in initial baseband signal is determined according to replacement indication signal, and uses mould
Partitioned signal is replaced the signal for needing to be replaced in initial baseband signal.
Present embodiment, after the completion of PIE coding, the binary code stream after directly being encoded according to PIE generates replacement instruction
Signal indicates the position for the signal for needing to be replaced in initial baseband signal so that subsequent baseband signal generate after, can directly according to
The signal section for needing to be replaced in initial baseband signal is replaced according to the instruction of replacement indication signal, replacement process does not produce
Raw delay, real-time are high.
Optionally, the position where the signal for needing to be replaced in initial baseband signal specifically: in initial baseband signal
Position corresponding with the failing edge hopping part of binary code stream after PIE coding.
The failing edge hopping part of binary code stream after present embodiment is encoded according to PIE determines in initial baseband signal
The position for the signal for needing to be replaced, signal generation delay is small, and real-time is good.
Optionally, FPGA is configured with the first register and the second register, wherein the first register is for storing binary system
Initial data code stream, the second register is used to indicate CRC calculation；
Before binary initial data code stream is converted to the first binary code stream of single bit, method further include:
When the binary initial data code stream stored in detecting the first register changes, from the first register
The middle binary initial data code stream read after variation；
CRC calculating is carried out to the first binary code stream, is specifically included:
CRC calculating is carried out to the first binary code stream according to the CRC calculation of the second register instruction.
By configuring the first register and the second register in FPGA, it is respectively used to store binary initial data code stream
With instruction CRC calculation, so that signal processing is more efficient, strong flexibility.
Optionally, FPGA is configured with third register, is used to indicate the third deposit of the length and duty ratio of PIE coding
Device；
PIE coding is carried out to the second binary code stream, is specifically included:
PIE coding is carried out to the second binary code stream according to the length of the PIE coding of third register instruction and duty ratio.
By the third register of configuration instruction PIE is encoded in FPGA length and duty ratio, it can be achieved that PIE was encoded
The flexible configuration of length and duty ratio, the baseband signal programmability for being worth ultimately generating is strong, more flexible can cope with and exist
Line debugs demand and application of special occasions demand.
Based on the same inventive concept, the embodiment of the present invention also provides a kind of PR-ASK modulating device, which is applied to
In FPGA, the partial function module in FPGA specifically can be, be also possible to FPGA itself, the embodiment of the present invention does not do specific limit
System.Referring to Fig. 5, which is specifically included:
CRC computing module 21, for receiving binary initial data code stream of controller transmission；It will be described binary
Initial data code stream is converted to the first binary code stream of single bit；CRC calculating is carried out to the binary code stream of the list bit, it will
The CRC code for obtain after CRC calculating for first binary code stream is added in first binary code stream, obtains
Second binary code stream；
Coding module 22 generates the three or two for carrying out PIE coding and bipolar coding to second binary code stream
System code stream；
Raised cosine roll off filter module 23 carries out molding filtration processing to the third binary code stream, generates just primordium
Band signal；
Waveform adjusts module 24, for carrying out waveform adjustment to the initial baseband signal, generates baseband signal and exports.
Optionally, the coding module 22 is also used to: the binary code stream after being encoded according to PIE generates replacement instruction letter
Number, to indicate the position where the signal for needing to be replaced in the initial baseband signal；
The waveform adjustment module 24 is specifically used for: determining the initial base band according to the instruction of the replacement indication signal
Position where the signal for needing to be replaced in signal, and using template signal to needing to be replaced in the initial baseband signal
Signal be replaced.
Optionally, the position where the signal for needing to be replaced in the initial baseband signal specifically: the just primordium
Position corresponding with the failing edge hopping part of binary code stream after PIE coding in band signal.
Optionally, referring to Fig. 6, described device further includes communication configuration module 25, is used for:
1) it is configured to store the first register of binary initial data code stream for CRC computing module 21, so that CRC
When binary initial data code stream that computing module 21 is stored in detecting the first register changes, from the first deposit
Binary initial data code stream after variation is read in device, and binary initial data code stream after variation is converted into list
The first binary code stream of bit；2) the second register of instruction CRC calculation is configured to for CRC computing module 21, so that
The CRC calculation that CRC computing module 21 is indicated according to the second register carries out CRC calculating to the first binary code stream, and will
The CRC code being calculated is added in first binary code stream, obtains the second binary code stream；3) match for coding module 22
The third register for setting the length and duty ratio that are used to refer to PIE coding, so that coding module 22 is indicated according to third register
PIE coding length and duty ratio to second binary code stream carry out PIE coding；It 4) is raised cosine roll off filter module
23 are configured to the 4th register of instruction filter configuration parameter；5) module 24 is adjusted for waveform be configured to storage template letter
Number the 5th register.
In the specific implementation process, controller is specifically as follows arm processor, which can be by built-in
Lightweight AXI4 bus can be used for realizing that CPU is read from the cpu bus that end (AXI4-Lite Slave) is mounted to arm processor
The register at the end described device programmable logic part (programmable logic, PL) is write, CPU can be according to these registers
It realizes and the end PL is controlled.
In the following, the specific implementation of each functional module of PR-ASK modulating device is described in detail respectively:
1, configuration module 25 is communicated:
The AXI4 protocol code of AXI4-Lite Slave establishing criteria, register read-write interface is drawn in conversion after encapsulation.It is logical
The type for interrogating definition register (register, REG) in configuration module 25 realizes the read-write of register, and address information can be used the
16 are parsed.It is automatically complete by bus arbiter after AXI4-Lite Slave is mounted on the cpu bus of arm processor 11
At the arbitration of address.Communicate configuration module 25 and each Subordinate module (CRC computing module 21, coding module 22, raised cosine roll off
Filter module 23 and waveform adjustment module 24 etc.) data information connection, the content of registers by each Subordinate module is straight
It connects and guides to port, be sent into corresponding Subordinate module.
Communicating 25 configuration register of configuration module includes:
1) it is directed to CRC computing module 21, needs to be arranged register and is used to select CRC algorithm and stores the finger that CPU is issued
Enable (i.e. binary initial data code stream).Specifically, the first register of configuration is used to store binary initial data code stream,
It configures the second register and is used to indicate CRC calculation.In the specific implementation process, the implementation of the first register can be
Individually, it is also possible to multiple, the embodiment of the present invention is not particularly limited.For example, the first register of 3 32bit of setting is enough
Store commonly required command length.
2) it is directed to coding module 22, needs to configure the length and duty ratio of register instruction PIE coding.Specifically, to compile
Code module is configured to the length of instruction PIE coding and the third register of duty ratio.
3) it is directed to raised cosine roll off filter module 23, needs to be arranged register selection filter configuration parameter.Specifically, being
Raised cosine roll off filter module 23 is configured to the 4th register of instruction filter configuration parameter.
4) module 24 is adjusted for waveform, needs to be arranged register storage template signal.Specifically, adjusting module for waveform
24 are configured to the 5th register of storage template signal.
2, CRC computing module 21
Referring to Fig. 7, CRC computing module 21 specifically includes four submodules: instruction serial type transform subblock (Code_to_
Seriel) 211, CRC6 submodule 212, crc selection submodule (Crc_sel) 213 and CRC15 submodule 214.Wherein,
The instruction input triggering that Code_to_seriel submodule 211 is used to receive higher level's module (for example is stored in the first register
Binary initial data code stream changes), it is serially defeated that instruction (i.e. binary initial data code stream) is converted into single bit
Out.CRC6 submodule 212 and CRC15 submodule 214 receive single bit data code flow, and start to calculate CRC code, at data flow end
The CRC code that end addition is calculated, and Crc_sel submodule 213 is used to select CRC algorithm according to the instruction of the second register,
Choose a kind of data flow output.
3, coding module 22
Referring to Fig. 8, the binary code for the addition CRC code that higher level's module, that is, CRC computing module 21 of coding module 22 exports
After stream enters coding module 22, caching enters in first in first out caching (First in first out, fifo) device 221 first,
Built-in state machine (State machine) 226 detects the input of new command, starts to start frame head generation (frame_head_
Gen) device 225 generates frame head, and it is to be sent that the frame head data of generation flows into back segment fifo223 caching etc..Frame head, which generates, to be completed
Afterwards, starting frame data generator (frame_data_gen) 222 generates frame data, caches into rear end fifo223.Rate control
Device (Rate_ctl) 224 detects that there are frame data (binary code streams after encoding) in fifo223, with the reading of preset rate
Data Concurrent is taken to be sent in Subordinate module (i.e. raised cosine FIR filter module 23).Wherein, it is default to read data by Rate_ctl
Rate, those skilled in the art can select according to the actual situation, and the embodiment of the present invention is not particularly limited, for example, with
Rate 6.4M per second reads data.
PIE cataloged procedure: complete PIE code is divided into single high level low level section inside coding module 22, completely
PIE code be spliced by single hop.Single hop code generate when, by communication control configuration module 25 indicate PIE coding length and
The register (i.e. above-mentioned third register) of duty ratio generates the low and high level of programmable lengths, realizes different duty ratio and week
Phase.The length, low and high level length of each of PIE code section can be pre-configured with programming by third register, coding module 22 according to
Coding is generated according to its configuration and data.For example, the code registers of data-0 are configured that high=5, low=5, then production is encoded
Raw is 1111100000, if high=2, low=2, then coding is produced as 1100.The code registers of Data-1 are configured that
High=5, low=1 are then encoded and are produced as 111110.Fig. 9 is the citing that PIE encodes configurable register, and register REG0 is used
In configuring preamble separator length (delimiter), register REG1 is used for configuring preamble data data-0 high level length, posts
Storage REG2 is used for configuring preamble data data-0 low level length, and register REG3 is for configuring card reader to the leading school of label
Quasi- symbol (reader to tag calibration, RTcal) high level, register REG4 are posted for configuring RTcal low level
Storage REG5 is for label allocation to the high electricity of the leading calibration symbol (tag to reader calibration, TRcal) of card reader
Flat, register REG6 is for configuring TRcal low level length, with reference to interval (Type A Reference Interval, Tari)
Also referred to as reference time intervals, the period are the time width of two neighboring pulse falling edge, and PW is low level width
(pulse width)；Figure 10 is REG0=4, REG1=2, REG2=2, REG3=8, REG4=2, REG5=10, REG6=2
Configuration generates PIE lead code, and wherein dotted box portion is indicated according to the leading waveform of RFID caused by above register configuration.
Bipolar coding process: the unipolarity waveform that PIE coding generates needs to be converted to according to ambipolar coding rule
Bipolar waveform.For example, Figure 11 is the waveform diagram of bipolarity conversion front and back.
It can be seen from figure 11 that the waveform after bipolar coding contained at 0 point, so causing to filter by raised cosine roll off
Waveform after device module 23 occurs the too slow or amplitude of amplitude decline near 0 point and improves too slow situation.
2, Figure 12 is the schematic diagram for the initial baseband signal that raised cosine FIR filter module 23 exports, Figure 12 referring to Fig.1
Waveform waveform occur excessively smooth crossing near 0 point, do not meet sinusoidal magnitude value variation.The irregularity of initial baseband signal,
More frequency domain components can be introduced, signal quality is influenced.In consideration of it, the embodiment of the present invention can further to signal regularity portion
Divide and carries out waveform adjustment.
With continued reference to Figure 12, (i.e. amplitude increases the signal section that the part instruction in the dotted line frame in Figure 12 needs to replace
The position reduced with amplitude).And the signal that this part needs to replace, exactly correspond to the failing edge hopping part in PIE code.Therefore
The failing edge skip signal of PIE code can be indicated in PIE coding stage, using the indication signal as replacement indication signal,
The waveform adjusting stage is used to refer to baseband signal and needs position of the signal section replaced in baseband signal.
Figure 13 is to generate the schematic diagram for replacing indication signal, after the first row signal indicates PIE coding from top to bottom in Figure 13
Binary data code stream, the second row signal be indicate PIE coding after binary data code stream in valid data instruction letter
Number, the third line signal is the indication signal that the binary data code stream after indicating PIE coding terminates, and fourth line signal is instruction
The indication signal that binary data code stream after PIE coding starts, fifth line signal are the binary data code stream after PIE coding
Failing edge skip signal, wherein high level (i.e. dotted line frame iris out part) indication signal replacement.
4, raised cosine roll off filter module 23
Referring to Fig.1 4, finite impulse response (FIR) (the Finite impulse of 125 ranks can be used in raised cosine roll off filter module 23
Response, FIR) filter built, and FIR filter is relatively more fixed in FPGA way of realization, can directly adopt limit for length
Unit impulse response filter Logic Core (Finite Impulse Response Intellectual Property, FIR
IP it) realizes, first in first out caching (First Input First Output, fifo) is used for data buffer storage, advanced elder generation in Figure 14
Reading control of the cache controller (fifo control, fifo_ctl) for data buffer storage in fifo out, FIR top layer (fir_
It top) is FIR IP, parameter selector (parameter select, par_sel) is used for FIR filter parameter selection, Tu15Wei
The structural schematic diagram of FIR filter.
The input terminal of raised cosine roll off filter module 23 receives the third binary code stream and replace that coding module 22 exports
Change indication signal；Output is initial baseband signal and replaces indication signal, as shown in figure 16.
5, waveform adjusts module 24
As hereinbefore, initial baseband signal is when generating, since ambipolar PIE coding had 0 point of feelings
Condition, therefore the waveform after raised cosine roll off filter module 23 occur the too slow or amplitude of amplitude decline near 0 point and improved
Slow situation.The irregularity of initial baseband signal, can introduce more frequency domain components, influence signal quality, thus need by
Signal carries out waveform adjustment processing.
Waveform adjustment 24 input end signal of module includes initial baseband signal and replacement indication signal, replacement indication signal point
It Zhi Shi not start to replace failing edge signal, and start to replace rising edge signal, baseband signal is synchronous with template replacement indication signal.
Referring to Fig.1 7, when encountering failing edge instruction, template data inquiry address starts to be incremented by, and gets failing edge template
Data, and be substituted into initial baseband signal.When encountering rising edge instruction, template data inquiry address starts to be incremented by, and obtains
It to rising edge template data, and is substituted into initial baseband signal, the waveform adjustment of entire initial baseband signal is completed with this, it is whole
A process without carry out signal storage judgement, can template be replaced in real time.Figure 18 is before baseband signal waveform adjusts and to adjust
Waveform diagram after whole.
In the specific implementation process, template signal used in replacing can be stored in the random access memory of FPGA
It in (Random Access Memory, RAM), and is configured by the 5th register, by configuring different template signals
Different baseband signals is produced, the demand of various particular applications can be flexibly met.
In the specific implementation process, the present invention implements the above-mentioned apparatus provided, in addition to that can be used to realize before RFID to letter
Number PR-ASK modulation it is outer, can also be extended for realizing the modulation for modulating similar other signals with PR-ASK.For example, can
The waveform of the bipolar coding function, waveform adjustment module closed in coding module adjusts function, and appropriate adjustment the 4th is deposited
Filter configuration parameter in device reaches SSB-ASK modulation or DSB- to realize SSB-ASK modulation or the modulation of DSB-ASK
ASK modulation is completely implemented at the effect inside FPGA.
The one or more technical solutions provided in the embodiment of the present invention, have at least the following technical effects or advantages:
1, changing for baseband signal waveform can be realized by related register configuration in the PR-ASK modulation realized based on FPGA
Become, baseband signal programmability is strong, can more flexible reply on-line debugging demand and application of special occasions demand；
2, PR-ASK modulator approach is completely implemented inside FPGA, and design is simple, and occupancy logical resource is few, hardware spending
It is few；
3, resource occupation is small, without largely being calculated in baseband signal adjustment, only by jumping to PIE code failing edge
Detection can determine the position of the signal for needing to be replaced in baseband signal, use signal correlation meter compared to the prior art
It calculates, calculation amount needed for calculating replacement position is greatly improved, and improves the real-time of waveform adjustment；
4, each module design of FPGA is based on stream treatment criterion, and each module mono signal goes out into mono signal, further reduced
Signal delay；
5, FPGA inner utilization raised cosine FIR filter carries out molding filtration, directly passes through low pass compared with the prior art
Filter shape has the advantages that intersymbol without crosstalk, and the signal quality of generation is higher.
It should be understood by those skilled in the art that, the embodiment of the present invention can provide as method, system or computer program
Product.Therefore, complete hardware embodiment, complete software embodiment or reality combining software and hardware aspects can be used in the present invention
Apply the form of example.Moreover, it wherein includes the computer of computer usable program code that the present invention, which can be used in one or more,
The computer program implemented in usable storage medium (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.) produces
The form of product.
The present invention be referring to according to the method for the embodiment of the present invention, the process of equipment (system) and computer program product
Figure and/or block diagram describe.It should be understood that every one stream in flowchart and/or the block diagram can be realized by computer program instructions
The combination of process and/or box in journey and/or box and flowchart and/or the block diagram.It can provide these computer programs
Instruct the processor of general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce
A raw machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute for real
The device for the function of being specified in present one or more flows of the flowchart and/or one or more blocks of the block diagram.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (10)
1. a kind of phasing back amplitude-shift keying PR-ASK modulator approach, which is characterized in that be applied to field programmable gate array
In FPGA, which comprises
Receive binary initial data code stream that controller is sent；
Binary initial data code stream is converted to the first binary code stream of single-bit bit；
The CRC code that obtains after cyclic redundancy check (CRC) calculating will be carried out for first binary code stream is added to described the
In one binary code stream, the second binary code stream is obtained；
Pulsewidth coding PIE coding and bipolar coding are carried out to second binary code stream, generate third binary code
Stream；
Molding filtration processing is carried out to the third binary code stream, generates initial baseband signal；
Waveform adjustment is carried out to the initial baseband signal, baseband signal is generated and exports.
2. the method as described in claim 1, which is characterized in that after carrying out PIE coding to second binary code stream,
Further include:
Binary code stream after being encoded according to PIE generates replacement indication signal, with indicate to need in the initial baseband signal by
Position where the signal of replacement；
It is described that waveform adjustment is carried out to the initial baseband signal, comprising:
The position where the signal for needing to be replaced in the initial baseband signal is determined according to the replacement indication signal, and is adopted
The signal for needing to be replaced in the initial baseband signal is replaced with template signal.
3. method according to claim 2, which is characterized in where the signal for needing to be replaced in the initial baseband signal
Position specifically: in the initial baseband signal with the PIE coding after binary code stream failing edge hopping part pair
The position answered.
4. the method according to claim 1, which is characterized in that the FPGA is configured with the first register and second
Register, wherein for storing binary initial data code stream, second register is used for first register
Indicate CRC calculation；
Before binary initial data code stream is converted to the first binary code stream of single bit, the method is also wrapped
It includes:
When the binary initial data code stream stored in detecting first register changes, posted from described first
Binary initial data code stream after variation is read in storage；
It is described that CRC calculating is carried out to first binary code stream, it specifically includes:
CRC calculating is carried out to first binary code stream according to the CRC calculation of second register instruction.
5. method as claimed in claim 4, which is characterized in that the FPGA is configured with third register, is used to indicate PIE volume
The length of code and the third register of duty ratio；
It is described that PIE coding is carried out to second binary code stream, it specifically includes:
PIE is carried out to second binary code stream according to the length of the PIE coding of third register instruction and duty ratio
Coding.
6. a kind of PR-ASK modulating device is applied in FPGA characterized by comprising
CRC computing module, for receiving binary initial data code stream of controller transmission；By binary original number
The first binary code stream of single bit is converted to according to code stream；CRC calculating is carried out to the binary code stream of the list bit, institute will be directed to
It states the CRC code that the first binary code stream obtain after CRC calculating to be added in first binary code stream, obtains the two or two
System code stream；
Coding module generates third binary code for carrying out PIE coding and bipolar coding to second binary code stream
Stream；
Raised cosine roll off filter module carries out molding filtration processing to the third binary code stream, generates initial baseband signal；
Waveform adjusts module, for carrying out waveform adjustment to the initial baseband signal, generates baseband signal and exports.
7. device as claimed in claim 6, which is characterized in that the coding module is also used to:
Binary code stream after being encoded according to PIE generates replacement indication signal, with indicate to need in the initial baseband signal by
Position where the signal of replacement；
The waveform adjustment module is specifically used for: being determined in the initial baseband signal according to the instruction of the replacement indication signal
Position where the signal for needing to be replaced, and using template signal to the signal for needing to be replaced in the initial baseband signal
It is replaced.
8. device as claimed in claim 7, which is characterized in where the signal for needing to be replaced in the initial baseband signal
Position specifically: in the initial baseband signal with the PIE coding after binary code stream failing edge hopping part pair
The position answered.
9. such as the described in any item devices of claim 6-8, which is characterized in that the FPGA further includes communication configuration module, is used
In:
It is configured to store the first register of the initial data code stream for the CRC computing module, is used to refer to CRC calculating
Second register of mode；
The CRC computing module is specifically used for: the binary initial data code stored in detecting first register
When stream changes, from first register read variation after binary initial data code stream, and by described two into
The initial data code stream of system is converted to the first binary code stream of single bit；The calculating side CRC indicated according to second register
Formula carries out CRC calculating to first binary code stream, and the CRC code being calculated is added to first binary code stream
In, obtain the second binary code stream.
10. device as claimed in claim 9, which is characterized in that the communication configuration module is also used to:
The length of instruction PIE coding and the third register of duty ratio are configured to for the coding module；
The coding module is specifically used for: according to the length of the PIE coding of third register instruction and duty ratio to described
Second binary code stream carries out PIE coding.
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