CN109474294B - Uplink channel circuit for satellite-borne measurement and control equipment - Google Patents
Uplink channel circuit for satellite-borne measurement and control equipment Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
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- H—ELECTRICITY
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- H04B7/00—Radio transmission systems, i.e. using radiation field
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- H04B7/185—Space-based or airborne stations; Stations for satellite systems
- H04B7/1851—Systems using a satellite or space-based relay
- H04B7/18515—Transmission equipment in satellites or space-based relays
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- H—ELECTRICITY
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- H04B7/00—Radio transmission systems, i.e. using radiation field
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- H04B7/185—Space-based or airborne stations; Stations for satellite systems
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention discloses an uplink channel circuit for a satellite-borne measurement and control device. The up channel circuit comprises a low noise amplifier, a first mixer, an intermediate frequency filter, a second mixer, a baseband filter and an automatic gain controller which are arranged behind the second mixer, and then the up channel circuit is electrically connected with a digital baseband circuit, and the first mixer and the second mixer are mixed by a radio frequency local oscillator signal and an intermediate frequency local oscillator signal which are respectively generated by the same local oscillator circuit. The channel gain of the channel circuit can be adjusted by arranging the matched attenuator and the multistage gain amplifier, and the chip selected by the downlink channel circuit has small volume and low power consumption, the printed circuit board circuit comprises two communicated cavities, and the chip is arranged in the cavities in a compact way, so that the space is saved, and the advantages of miniaturization and good electromagnetic compatibility are realized.
Description
Technical Field
The invention relates to the field of satellite measurement and control, in particular to an uplink channel circuit for satellite-borne measurement and control equipment.
Background
The satellite-borne measurement and control equipment is equipment which is loaded on a satellite and used for completing functions of satellite-to-ground measurement and control, ranging, speed measurement and the like, and plays an important role in the in-orbit flight of the satellite. The device is typically composed of an antenna, a channel circuit, a baseband circuit, a computer, a power supply, etc.
Because of the influence of factors such as satellite load weight, space, energy consumption and the like, the indexes such as the volume, the weight, the power consumption and the like of the satellite-borne measurement and control equipment are expected to meet the design requirements of miniaturization, light weight and low power consumption, and the satellite-borne measurement and control equipment works stably and reliably. For up-channel circuits, design requirements in terms of channel bandwidth, channel gain, etc. are also to be met.
Disclosure of Invention
The invention mainly solves the technical problem of providing an uplink channel circuit for a satellite-borne measurement and control device, and solves the problems of miniaturization, universality, low power consumption and the like of the uplink channel circuit of the satellite-borne measurement and control device in the prior art.
In order to solve the technical problem, the invention adopts a technical scheme that an uplink channel circuit for a satellite-borne measurement and control device is provided, and the uplink channel circuit comprises a low noise amplifier, a first mixer and a second mixer, wherein an intermediate frequency filter is arranged between the first mixer and the second mixer, a baseband filter and an automatic gain controller are arranged behind the second mixer, and the second mixer is electrically connected with a digital baseband circuit; the low noise amplifier receives a radio frequency signal to amplify the radio frequency signal with low noise, then carries out first down conversion through the first mixer to obtain an intermediate frequency signal, filters the intermediate frequency signal through the intermediate frequency filter, carries out second down conversion through the second mixer to obtain a baseband signal, and then carries out filtering through the baseband filter and automatic gain control through the automatic gain controller to output the baseband signal.
In another embodiment of the up channel circuit for the satellite-borne measurement and control device, the first mixer and the second mixer are used for mixing the radio frequency local oscillation signals and the intermediate frequency local oscillation signals respectively generated by the same local oscillation circuit.
In another embodiment of the up channel circuit for the satellite-borne measurement and control equipment, a first stage radio frequency filter is further arranged in front of the low noise amplifier in a cascading manner, a second stage radio frequency filter is further arranged behind the low noise amplifier in a cascading manner, and a second stage radio frequency gain amplifier is further arranged between the second stage radio frequency filter and the first mixer.
In another embodiment of the up channel circuit for the satellite-borne measurement and control device of the present invention, an intermediate frequency amplifier is arranged between the intermediate frequency filter and the second mixer.
In another embodiment of the up channel circuit for the satellite-borne measurement and control device, the radio frequency signal, the intermediate frequency signal, the baseband signal, the radio frequency local oscillation signal and the intermediate frequency local oscillation signal are integer multiples of the fundamental frequency.
In another embodiment of the up-channel circuit for the on-board measurement and control device of the present invention, the low noise amplifier includes a chip TQP M9037, the first mixer includes a chip MAX2681, the second mixer includes a chip AD8347, the first stage radio frequency filter includes a chip CMF43C2031C03A, the second stage radio frequency gain amplifier includes a chip ECG001F-G, the intermediate frequency filter includes a chip TA0424A, and the intermediate frequency amplifier includes a chip ECG001F-G.
In another embodiment of the up channel circuit for the satellite-borne measurement and control equipment, the up channel circuit is arranged in a two-way cavity which is in an inverted U shape, the chip CMF43C2031C03A, the chip QP3M9037, the chip CMF43C2031C03A, the chip ECG001F-G and the chip MAX2681 are arranged in a first cavity, and the chip MAX2681, the chip TA0424A, the chip ECG001F-G and the chip AD8347 are arranged in a second cavity.
In another embodiment of the up channel circuit for a satellite-borne measurement and control device of the present invention, the up channel local oscillation circuit includes a chip S I4133, a clock signal output by a clock generator is input to an XI N end of the chip S I4133, an RFOUT end of the chip S I4133 outputs the radio frequency local oscillation signal, and an I FOUT end of the chip S I4133 outputs the intermediate frequency local oscillation signal.
The beneficial effects of the invention are as follows: the invention discloses an uplink channel circuit for a satellite-borne measurement and control device. The up channel circuit comprises a low noise amplifier, a first mixer, an intermediate frequency filter, a second mixer, a baseband filter and an automatic gain controller which are arranged behind the second mixer, and then the up channel circuit is electrically connected with a digital baseband circuit, and the first mixer and the second mixer are mixed by a radio frequency local oscillator signal and an intermediate frequency local oscillator signal which are respectively generated by the same local oscillator circuit. The channel gain of the channel circuit can be adjusted by arranging the matched attenuator and the multistage gain amplifier, and the chip selected by the downlink channel circuit has small volume and low power consumption, the printed circuit board circuit comprises two communicated cavities, and the chip is arranged in the cavities in a compact way, so that the space is saved, and the advantages of miniaturization and good electromagnetic compatibility are realized.
Drawings
FIG. 1 is a block diagram of one embodiment of an up channel circuit for an on-board measurement and control device in accordance with the present invention;
FIG. 2 is a schematic diagram of a clock circuit in one embodiment of an up channel circuit for an on-board measurement and control device in accordance with the present invention;
FIG. 3 is a diagram of an up channel local oscillator circuit in one embodiment of an up channel circuit for use with a satellite based measurement and control device in accordance with the present invention;
FIG. 4 is a circuit diagram of a first stage RF filter and a low noise amplifier in one embodiment of an up channel circuit for an on-board measurement and control device in accordance with the present invention;
FIG. 5 is a circuit diagram of a second stage RF filter and a second stage RF gain amplifier in one embodiment of an up channel circuit for an on-board measurement and control device in accordance with the present invention;
FIG. 6 is a circuit diagram of a first mixer in an embodiment of an up-channel circuit for an on-board measurement and control device in accordance with the present invention;
FIG. 7 is a circuit diagram of an intermediate frequency filter and intermediate frequency amplifier in one embodiment of an up channel circuit for an on-board measurement and control device in accordance with the present invention;
FIG. 8 is a second mixer circuit diagram in an embodiment of an up channel circuit for an on-board measurement and control device in accordance with the present invention;
FIG. 9 is a circuit diagram of a filter network in one embodiment of an up channel circuit for an on-board measurement and control device in accordance with the present invention;
FIG. 10 is a block diagram of the channel components in one embodiment of an up channel circuit for an on-board measurement and control device in accordance with the present invention;
FIG. 11 is a circuit board layout diagram in an embodiment of an up-channel circuit for an on-board measurement and control device in accordance with the present invention.
Detailed Description
In order that the invention may be readily understood, a more particular description thereof will be rendered by reference to specific embodiments that are illustrated in the appended drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used in this specification includes any and all combinations of one or more of the associated listed items.
FIG. 1 shows a flow chart of one embodiment of the up-channel circuit for an on-board measurement and control device of the present invention. In fig. 1, a low noise amplifier 10, a first mixer 11 and a second mixer 12 are included, and an intermediate frequency filter 13 is provided between the first mixer 11 and the second mixer 12, and a baseband filter 14 and an automatic gain controller 15 are further provided after the second mixer 12, and then input to a digital baseband circuit 16. The low noise amplifier 10 receives the uplink rf signal from the ground to perform low noise amplification, performs first down-conversion through the first mixer 11 to obtain an intermediate frequency signal, filters the intermediate frequency signal through the intermediate frequency filter 13, performs second down-conversion through the second mixer 12 to obtain a baseband signal, and performs filtering through the rf filter 14 and automatic gain control through the automatic gain controller 15 to output the baseband signal.
Preferably, the first mixer 11 and the second mixer 12 mix the radio frequency local oscillation signal and the intermediate frequency local oscillation signal respectively generated by the same uplink channel local oscillation circuit 17.
Preferably, FIG. 2 shows an illustrative graph of the frequency relationship produced by the clock circuit. It can be seen that the 10MHz oscillation signal output by the crystal oscillator signal source 610 generates a square wave signal of 80MHz to the digital baseband circuit after passing through the clock generator 612, and generates two clock signals with the same frequency, the frequency being 4F0, and outputs the two clock signals to the up-channel local oscillation circuit 613 and the down-channel local oscillation circuit 614 respectively, the up-channel local oscillation circuit 613 generates the radio frequency local oscillation signal 133F0 and the intermediate frequency local oscillation signal 87F0 respectively through the phase-locked loop therein, and the down-channel local oscillation circuit 614 generates the first local oscillation signal 13F0 and the second local oscillation signal 225F0 respectively through the phase-locked loop therein. It can be seen that the clock circuit generates local oscillation signals with different frequencies based on the same crystal oscillator signal source 610 after multiple frequency multiplication, and the local oscillation signals use the same fundamental frequency F0 as a reference, and the generated frequency is an integer multiple of the fundamental frequency.
Preferably, fig. 3 shows a circuit diagram of an embodiment of an up channel local oscillator circuit. The channel local oscillator circuit includes a chip S I4133. The chip forms a phase-locked loop local oscillation circuit, the radio frequency output frequency range is 0.9GHz-1.8GHz or 0.75GHz-1.5GHz, the intermediate frequency output frequency range is 62.5MHz-1000MHz, the output power range is-7 dBm-0dBm, the reference frequency is up to 26MHz, the working voltage is 2.7-3.6V, and the working current is 18mA. The input clock signal REF_D is input to the XI N end of the chip through a coupling capacitor C56, the radio frequency local oscillation signal DLO_RF generated by the chip is output by the RFOUT end through an inductor L18 and a capacitor C42 which are connected in series, and the intermediate frequency local oscillation signal DLO_ I F generated by the chip is output by the I FOUT end through an inductor L34 and a capacitor C109 which are connected in series.
In addition, it can be seen that the SDATA terminal and the SCLK terminal of the chip S I4133 are used for inputting frequency control words, and the frequencies output by the RFOUT terminal and the I FOUT terminal can be set respectively.
Preferably, as shown in fig. 4, the low noise amplifier 10 includes a chip TQP M9037 with a noise figure of 0.6, a gain of 19dB, an output 1dB compression point power of 16dBm, a supply of 3.3V, and a current of 44mA at 2 GHz.
Preferably, the chip TQP M9037 is first filtered, and the uplink radio frequency signal from the ground is received by the antenna and then filtered by the dielectric filter CMF43C2031C03A, which is referred to as a first stage radio frequency filter. The chip has only three pins, is small in size, belongs to passive filtering and is low in power consumption. The filter belongs to a blocking filter to filter strong signals of a receiving channel of the transmitter coupled from an antenna, preventing the receiver from being saturated. Then, a matching network composed of capacitors C27 and C116 and an inductor L38 is passed, the matching network is formed by connecting the capacitors C27 and C116 in series, one end of the inductor L38 is connected to the electric connection part of the capacitors C27 and C116, and the other end is grounded. The matching network with the structure can also be replaced by a matching attenuation network consisting of resistors, and the matching attenuation network is used for regulating and controlling the channel gain. The other end of the capacitor C116 is electrically connected to the rf input terminal RFI of the chip TQP M9037 as an output terminal of the matching network, and the rf output terminal RFO of the chip TQP M9037 is electrically connected to the capacitor C117, so that the low noise amplified rf signal is further output from the capacitor C117 to the subsequent stage. In addition, the rf output terminal RFO of the chip TQP M9037 is further connected to +3.3v dc voltage through a power filtering network, the power filtering network includes capacitors C114 and C115 and an inductor L37, the power filtering network is favorable to filtering power fluctuation interference caused by a power supply and other interference signals of crosstalk, electromagnetic compatibility of the channel circuit is improved, the capacitors C114 and C115 and the inductor L37 are connected to +3.3v dc voltage together, the other ends of the capacitors C114 and C115 are grounded, and the other end of the inductor L37 is connected to the rf output terminal RFO of the chip TQP M9037.
Further, as shown in fig. 5, the rf output terminal RFO of the chip TQP M9037 in fig. 4 is electrically connected to the capacitor C117 and then further connected to the input terminal of the U2 dielectric filter CMF43C2031C03A in fig. 5. The filter is called a second stage radio frequency filter, and is mainly used for suppressing the image component and further filtering the signal of the emission leakage. The output end of the filter is electrically connected with a capacitor C148 and is connected to the input IN end of a chip ECG001F-G, and the chip belongs to a gain amplifier for radio frequency signals, namely a second-stage radio frequency gain amplifier is arranged between the second-stage radio frequency filter and the first mixer. The working frequency band of the chip is DC-6 GHz, the gain is 20dB@2GHz, the noise coefficient is 3.4dB, and the output 1dB compression point power is +12.5dBm. +3.4V supply, current 30mA. Therefore, the input signal is amplified by 20dB, the output OUT end of the chip ECG001F-G is electrically connected with the capacitor C23, and meanwhile, the output OUT end also passes through a power supply filter network consisting of the inductors L52, C150 and C151, the power supply filter network is favorable for filtering power supply fluctuation interference and other interference signals of crosstalk caused by a power supply, the electromagnetic compatibility of a channel circuit is improved, the voltage dividing resistor R3 is connected with direct current +5V voltage, and the direct current voltage at the output OUT end is 3.4V.
Further, as shown in fig. 6, the output OUT end of the chip ECG001F-G in fig. 5 is electrically connected to the capacitor C23 and then connected to a matching network composed of the capacitors C37 and C38 and the inductor L14, the capacitors C37 and C38 are connected in series, one end of the inductor L14 is connected to the serial connection between the capacitors C37 and C38, the other end is grounded, and the other end of the capacitor C38 is connected to the radio frequency input end RFIN of the chip MAX 2681. The local oscillator end LO of the chip is connected to the radio frequency local oscillator signal DLO_RF through a coupling capacitor C34. After the radio frequency signal and the radio frequency local oscillation signal are mixed by the chip MAX2681, an intermediate frequency signal is output by an IFOUT end of the chip. It can also be seen that the power supply terminal VCC of the chip MAX2681 is connected to a +3.3v dc power supply through a power supply filter network composed of capacitors C35, C36 and an inductor L27. The power supply filter network is favorable for filtering power supply fluctuation interference caused by a power supply and other interference signals of crosstalk, so that the electromagnetic compatibility of the channel circuit is improved, and the/SHDN end of the chip MAX2681 is electrically connected with the power supply end VCC. The IFOUT terminal of the chip MAX2681 is also electrically connected to the power supply terminal VCC through the inductance L13, and is further connected to the subsequent stage circuit through the capacitance C39. The working frequency of the RFIN end and the LO end of the chip MAX2681 is 400 MHz-2500 MHz, the working frequency of the IFOUT end is 10 MHz-500 MHz, the variable frequency gain is about 8dB, the input third-order cut-off point is 1dBm, the noise coefficient is 12.7dB, the power is supplied by 2.7V-5.5V, and the current is 8.7mA.
Further, as shown in fig. 7, the IFOUT terminal of the chip MAX2681 in fig. 6 is electrically connected to the capacitor C40 in fig. 7 through the capacitor C39, and then connected to the input terminal of the acoustic surface filter chip TA0424A, which is passive filtering for suppressing the spurious generated by the mixer chip MAX2681, which is also called as an intermediate frequency filter. The output end of the chip TA0424A is electrically connected with the input IN end of the amplifier chip ECG001F-G through the coupling capacitor C4, and the chip performs gain amplification on the intermediate frequency signal after the down-conversion, so that an intermediate frequency amplifier is arranged between the intermediate frequency filter and the second mixer. The working frequency band of the chip is DC-6 GHz, the gain is 20dB@2GHz, the noise coefficient is 3.4dB, and the output 1dB compression point power is +12.5dBm. +3.4V supply, current 30mA. Therefore, the input signal is amplified by 20dB, the output OUT end of the chip ECG001F-G is electrically connected with the capacitor C1 and is connected with the subsequent stage circuit, meanwhile, the output OUT end also passes through a power supply filter network consisting of the inductors L1, C32 and C61, the power supply filter network is favorable for filtering power supply fluctuation interference and other interference signals of crosstalk caused by a power supply, the electromagnetic compatibility of a channel circuit is improved, the voltage dividing resistor R2 is connected with direct current +5V voltage, and the direct current voltage at the output OUT end is 3.4V.
Further, as shown in fig. 8, the output OUT terminal of the chip ECG001F-G in fig. 7 is electrically connected to the capacitor C1, then is electrically connected to the resistor R20 and the capacitor C48 in fig. 8, and is coupled to the RFIP terminal of the quadrature demodulator chip AD8347 through the capacitor C48, and the chip AD8347 integrates functions of intermediate frequency mixing, intermediate frequency amplifier, AGC and the like, wherein the bandwidth of the intermediate frequency is 0.8GHz-2.7GHz, the maximum bandwidth of the intermediate frequency can reach 65mhz, 2.7-5.5V is supplied, and the current is 64mA. It can also be seen from fig. 8 that, after the intermediate frequency local oscillation signal dlo_if passes through the filter network formed by the capacitors C63, C64 and the resistor R25, the intermediate frequency local oscillation signal dlo_if is input to the LOIP end and the LOIN end of the chip AD8347, and is used for further performing down-conversion mixing with the intermediate frequency signal input by the RFIP end. The QOPP end and the QOPN end of the chip output two paths of baseband signals IF-OUT and IF+OUT after down-conversion through capacitors C159 and C160 respectively.
In addition, in fig. 8, the VREF terminal of the chip is also electrically connected to the VDT2 terminal through a resistor R17 and to the QAIN terminal, and is connected to one terminal of the peripheral filter network W1 through a capacitor C52 at the QMXO terminal, and the other terminal of the peripheral filter network W1 is connected to the QAIN terminal of the chip and to the VDT1 terminal through a resistor R22. In addition, the VAGC terminal is electrically connected to the resistor R18 and then electrically connected to the VGIN terminal, and this electrical connection mode makes the chip operate in a gain control mode state, and the gain can be changed according to the external control voltage, and VGIN is further electrically connected to the resistor R29 and then receives the external gain control voltage.
Fig. 9 shows a peripheral filter network W1, which comprises 3 sub-networks, wherein the input end of the filter network is also one end of a capacitor C62 electrically connected to the input end of the first sub-network, the capacitor C62 is connected in parallel with an inductor L31, the end of the capacitor C62 is further connected in series with an inductor L19 and then grounded, the other end of the capacitor C62 is connected in series with an inductor L20 and then grounded, and the other end of the capacitor C62 is also connected as the output end of the first sub-network to the input end of the second sub-network.
The input end of the second sub-network is electrically connected to one end of a resistor R67, a resistor R66 is connected in series with the output end of the first network and then grounded, the other end of the resistor R67 is connected in series with a resistor R68 and then grounded, and the other end of the resistor R67 is also connected to the input end of the third sub-network as the output end of the second sub-network.
The input end of the third sub-network is electrically connected with one end of an inductor L21, two ends of the inductor L21 are connected with a capacitor C65 in parallel, one end of the inductor L21 is also connected with a capacitor C66 in series and then grounded, and the other end of the inductor L21 is connected with the capacitor C67 in series and then grounded; the electric connection part of the inductor L21 and the capacitor C67 is also electrically connected with one end of the inductor L22, the inductor L22 is connected with the capacitor C73 in parallel, the other end of the inductor L22 is connected with the capacitor C68 in series and then grounded, the other end of the inductor L22 is also used as the output end of the third sub-network to be connected with the capacitor C69, and the other end of the capacitor C69 is used as the output end of the whole filter network.
The channel gain needs to be considered to meet the requirement on the signal level for the whole uplink channel circuit, and meanwhile, the nonlinear influence of gain amplification on components is considered, so that multistage filtering and multistage amplification are also emphasized on the radio frequency part in the whole uplink channel circuit, and an attenuation network for adjusting the gain of the whole channel is also arranged. Preferably, on the basis of the embodiment shown in fig. 1, as shown in fig. 9, the frequency of the input radio frequency signal is 221F0, the power level of the signal is-105 dBm to-52 dBm, the signal has-1 dB loss after passing through the dielectric filter CMF43C2031C03A, the matched attenuator S1 for regulation can be set according to the requirement, and as shown in fig. 4, the matched attenuator S1 is a matching network composed of capacitors C27, C116 and an inductor L38, and under the condition that the circuit structure is kept unchanged, the capacitors C27, C116 and the inductor L38 can be replaced by resistors, so that the matched attenuation network is formed for regulating the gain of the whole channel. And the capacitors, the inductors and the resistors are replaced by only replacing the capacitors, the inductors and the resistors by adopting the same patch packaging structure, so that the PCB circuit board is not required to be specially structurally, and the flexibility of adjusting the channel gain is enhanced. The low noise amplifier 10 includes a chip TQP3M9037 that provides a gain of 19dB, corresponding to a power level of-88 dBm to-34 dBm of the radio frequency signal.
Further, there is a loss of-1 dB through the RF filter L2, i.e., corresponding to the dielectric filter CMF43C2031C03A in FIG. 4, and then through the RF gain amplifier D1, corresponding to the chip ECG001F-G in FIG. 4, with a RF gain of 20 dB. The matching attenuator S2 for regulation and control can be set according to the need, as can be seen from fig. 5, the matching attenuator S2 is a matching network composed of capacitors C37 and C38 and an inductor L14, and the matching network can also replace the capacitors C37 and C38 and the inductor L14 with resistors under the condition of unchanged circuit structure and also be used for regulating and controlling the gain of the whole channel. The mixer 11 corresponds to a chip MAX2681 with a gain of 5dB, the intermediate frequency filter 13 corresponds to the saw filter chip TA0424A with an attenuation of-5 dB, and then passes through the rf amplifier D2 with a rf gain of 20dB corresponding to the gain amplifier chip ECG001F-G. Thus, the power level of the signal varies by a gain of-1+20+5-5+20=39 dB before entering the second mixer 12, and thus the power level of the corresponding signal ranges from-49 dBm to 5dBm. The second mixer 12 corresponds to a chip AD8347 which integrates the function of AGC and is able to control the input signal level at a constant power value of-5 dBm.
In addition, from the perspective of frequency conversion, the up-channel circuit adopts an integer multiple frequency conversion scheme, that is, the radio frequency signal, the intermediate frequency signal, the baseband signal, and the radio frequency local oscillation signal and the intermediate frequency local oscillation signal are all integer multiples of a fundamental frequency, and the fundamental frequency is denoted by F0. As can be seen from fig. 10, the frequency of the radio frequency signal is 221F0, the local oscillation circuit multiplies the input reference frequency 4F0 and outputs two local oscillation signals, namely, a radio frequency local oscillation signal and an intermediate frequency local oscillation signal, wherein the frequency corresponding to the radio frequency local oscillation signal is 133F0, the frequency corresponding to the intermediate frequency local oscillation signal is 87F0, after first down-conversion by the mixer 11, the frequency of the output signal is 88F0, and then after second down-conversion by the mixer 12, two orthogonal signals are output, the frequencies of the two signals are all F0, and only the carrier phases are orthogonal, which are respectively represented by f0+ and F0-. The actual value of the frequency parameter F0 of the fundamental frequency can be reasonably selected through the integral multiple frequency conversion scheme, so that the universality of the uplink channel circuit is enhanced.
Fig. 11 shows a layout diagram of the printed circuit board of the up-channel circuit, and it can be seen that these circuit components are mainly laid in the inverted U-channel, and the layout diagram shows that U14 corresponds to the chip CMF43C2031C03A, U4 corresponds to the chip QP3M9037, U2 corresponds to the chip CMF43C2031C03A, U33 corresponds to the chip ECG001F-G, U5 corresponds to the chip MAX2681, U6 corresponds to the chip TA0424A, U9 corresponds to the chip ECG001F-G, and U8 corresponds to the chip AD8347. The chips also correspond to the chips in fig. 4 to 8, and the structure shows that the whole channel circuit has the characteristic of miniaturization, and is arranged according to the cascade relation formed by the uplink channel circuits, so that in order to arrange the chips in a limited space, a cavity dividing structure is adopted, and it can be seen that U14, U4, U2, U33 and U5 in the first cavity Q1 mainly finish amplification and filtering of radio frequency, and first down-conversion, U6, U9 and U8 in the second cavity Q2 mainly finish filtering and gain amplification of intermediate frequency, the two cavities have certain independence and simultaneously carry out channel cascade, and meanwhile, reasonable layout in the limited space is also met, and the miniaturization requirement is met.
In addition, from the viewpoint of power consumption estimation, the main chips of the up-channel circuit are: the low-noise amplifier chip QP3M9037 is 3.3V power supply, the current is 45mA, and the single-chip power consumption is 148.5mW; the chip ECG001F-G is 3.3V power supply, the current is 30mA, the single chip power consumption is 99mW, two chips are used, and the power consumption is 198mW; chip MAX2681 is 3.3V power supply, current is 9mA, and single-chip power consumption is 29.7mW; chip AD8347 is 5V power supply, current is 64mA, and single-chip power consumption is 320mW; the upstream PLL chip SI4133 was 3.3V powered, 20mA current, 66mW single chip power consumption. The overall power consumption of the uplink channel is estimated to be 762.2mW, and the uplink channel has the obvious characteristic of low power consumption.
It can be seen that the present invention discloses an up channel circuit for a satellite-borne measurement and control device. The up channel circuit comprises a low noise amplifier, a first mixer, an intermediate frequency filter, a second mixer, a baseband filter and an automatic gain controller which are arranged behind the second mixer, and then the up channel circuit is electrically connected with a digital baseband circuit, and the first mixer and the second mixer are mixed by a radio frequency local oscillator signal and an intermediate frequency local oscillator signal which are respectively generated by the same local oscillator circuit. The channel gain of the channel circuit can be adjusted by arranging the matched attenuator and the multistage gain amplifier, and the chip selected by the downlink channel circuit has small volume and low power consumption, the printed circuit board circuit comprises two communicated cavities, and the chip is arranged in the cavities in a compact way, so that the space is saved, and the advantages of miniaturization and good electromagnetic compatibility are realized.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent structural changes made by the present invention and the accompanying drawings, or direct or indirect application in other related technical fields, are included in the scope of the present invention.
Claims (7)
1. The uplink channel circuit for the satellite-borne measurement and control equipment is characterized by comprising a low-noise amplifier, a first mixer and a second mixer, wherein an intermediate frequency filter is arranged between the first mixer and the second mixer, and a baseband filter and an automatic gain controller are arranged behind the second mixer and then electrically connected with a digital baseband circuit; the low noise amplifier receives a radio frequency signal to amplify the radio frequency signal with low noise, performs first down-conversion through the first mixer to obtain an intermediate frequency signal, filters the intermediate frequency signal through the intermediate frequency filter, performs second down-conversion through the second mixer to obtain a baseband signal, and then performs filtering through the baseband filter and automatic gain control through an automatic gain controller to output the baseband signal;
the first mixer and the second mixer are used for mixing radio frequency local oscillation signals and intermediate frequency local oscillation signals respectively generated by the same uplink channel local oscillation circuit;
the frequencies of the radio frequency local oscillation signal, the intermediate frequency local oscillation signal, the baseband signal, the intermediate frequency signal and the radio frequency signal are integer multiples of the frequency of the fundamental frequency signal by taking the same fundamental frequency as a reference.
2. The up-channel circuit for a satellite-borne measurement and control device according to claim 1, wherein a first stage radio frequency filter is further cascaded before the low noise amplifier, a second stage radio frequency filter is further cascaded after the low noise amplifier, and a second stage radio frequency gain amplifier is further arranged between the second stage radio frequency filter and the first mixer.
3. Up-channel circuit for a satellite borne measurement and control device according to claim 2, characterized in that an intermediate frequency amplifier is arranged between the intermediate frequency filter and the second mixer.
4. A up-channel circuit for a satellite borne measurement and control device according to claim 3, wherein the radio frequency signal, the intermediate frequency signal, the baseband signal, and the radio frequency local oscillator signal and the intermediate frequency local oscillator signal are each integer multiples of a fundamental frequency.
5. The up-channel circuit for an on-board measurement and control device of claim 4, wherein the low noise amplifier comprises a chip TQP M9037, the first mixer comprises a chip MAX2681, the second mixer comprises a chip AD8347, the first stage radio frequency filter comprises a chip CMF43C2031C03A, the second stage radio frequency gain amplifier comprises a chip ECG001F-G, the intermediate frequency filter comprises a chip TA0424A, and the intermediate frequency amplifier comprises a chip ECG001F-G.
6. The up-channel circuit for a satellite borne measurement and control device according to claim 5, wherein the up-channel circuit is arranged in two-way cavities in an inverted U shape, the chip CMF43C2031C03A, the chip QP3M9037, the chip ECG001F-G, the chip MAX2681 are arranged in a first cavity, and the chip MAX2681, the chip TA0424A, the chip ECG001F-G, and the chip AD8347 are arranged in a second cavity.
7. The up channel circuit for a satellite-borne measurement and control device according to claim 1, wherein the up channel local oscillation circuit comprises a chip SI4133, a clock signal output by a clock generator is input to an XIN terminal of the chip SI4133, an RFOUT terminal of the chip SI4133 outputs the radio frequency local oscillation signal, and an IFOUT terminal of the chip SI4133 outputs the intermediate frequency local oscillation signal.
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