CN109473073B - Display device and driving method thereof - Google Patents
Display device and driving method thereof Download PDFInfo
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- CN109473073B CN109473073B CN201811379607.XA CN201811379607A CN109473073B CN 109473073 B CN109473073 B CN 109473073B CN 201811379607 A CN201811379607 A CN 201811379607A CN 109473073 B CN109473073 B CN 109473073B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
Abstract
The invention discloses a display device and a driving method thereof, belonging to the technical field of display, wherein the display device comprises a display panel, a control circuit and a grid driving circuit; the control circuit receives a frame data signal and carries out integrity judgment on the frame data signal, and when the frame data signal is judged to be missing, the control circuit generates a missing detection signal; when the received frame data signal is judged to be a complete signal, the control circuit generates an emptying signal; when detecting that a missing detection signal or a clear signal is generated, the control circuit generates a clear signal and inputs the clear signal into the gate drive circuit, so that the control circuit can clear and reset the gate drive circuit after receiving any frame data signal; the display device and the driving method thereof are used for solving the problem of abnormal display caused by the absence of a certain frame data signal.
Description
Technical Field
The invention belongs to the technical field of display, and particularly relates to a display device and a driving method thereof.
Background
Fig. 1 is a schematic diagram of a display device using GDM (Gate Driver Monolithic) technology, which has various names, such as GIP (Gate In Panel), ASG (organic Silicon Gate), GOA (Gate on Array or Gate Driver on Array), and the like. The original process of the liquid crystal display panel is used to manufacture the grid drive circuit connected with the scanning line on the substrate around the display area, so that the grid drive circuit can replace an external IC to complete the drive of the scanning line. The GDM technology can reduce the binding process of the external IC, thus improving the productivity and reducing the product cost, and the liquid crystal display panel can be more suitable for manufacturing narrow-frame or frameless display products.
As shown in fig. 2, a conventional display device includes a display panel 01, a control circuit including a timing control circuit 02 (TCON), a Level shifter 03 (LVSH), and a gate driver circuit 04 (GDM circuit). As shown in fig. 3, the timing control circuit 02 receives a continuous multi-frame data Signal (Signal), generates signals such as a gate start Signal GSP and a clear Signal CLRI, and inputs the signals to the level conversion circuit 03, the level conversion circuit 03 outputs the signals such as the gate start Signal GSP, the clear Signal CLRO, a plurality of clock signals CLK1, CLK2, CLK3, and CLK4 to the gate drive circuit 04, and the gate drive circuit 04 controls the voltage on each row of scanning lines (gate lines), so that the display device performs normal display.
As shown in fig. 3, after receiving a complete frame of data signal, the timing control circuit 02 generates a clear signal CLRI, i.e., the potential on the clear signal line in the timing control circuit 02 rises from a low potential to a high potential, and then falls to the low potential after maintaining the high potential for a short period of time. The level shifter circuit 03 boosts the clear signal CLRI, and inputs the boosted clear signal CLRO to the gate driver circuit 04. The gate drive circuit 04, upon receiving the clear signal CLRO, performs clear reset and outputs the low-level scan signal Gn. When the next frame data starts, the above operations are sequentially circulated.
As shown in fig. 4, when the data signal of the Fm th frame is missing, the level shifter 03 does not output the clear signal CLRO after receiving the data signal of the Fm th frame, and the gate driver 04 does not perform the clear operation. When the data signal of the Fm +1 th frame is output, the gate driving circuit 04 operates abnormally, and the display of the frame is abnormal. When the output of the data signal of the complete Fm +1 th frame is finished, the level conversion circuit 03 generates a clear signal CLRO and inputs the clear signal CLRO to the gate driving circuit 04, the gate driving circuit 04 is cleared and reset, and the subsequent picture is normally displayed. Therefore, the absence of data signals in a certain frame may cause abnormal display in subsequent frames, and the gate driving circuit 04 is continuously at a high voltage level, which affects the stability of the display.
When the data signal of the Fm th frame is missing, a plurality of adjacent clock signals output from the level shifter 03 are maintained at a high level, and the remaining clock signals are maintained at a low level. Taking the driving timing shown in fig. 4 as an example, CLK2 and CLK3 are maintained at a high potential, and CLK1 and CLK4 are maintained at a low potential. When the timing control circuit 02 does not have an Over Current Protection (OCP) function, a large current is always present in the circuits in the display device before the output of the clear signal CLRI of the next frame, which may damage the gate driving circuit 04. When the timing control circuit 02 has an over-current protection (OCP) function, the duration of the large current is greater than a set value, all outputs of the timing control circuit 02 are in a high impedance (Hi-Z) state, and the display device does not need to display a picture and can normally display the picture after being powered on again.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a display device, wherein a clear signal is formed after performing an or operation on a missing detection signal and a clear signal generated by a timing control circuit, so that the control circuit can perform a clear reset on a gate driving circuit after receiving any frame data signal; the invention also discloses a driving method of the display device.
The technical scheme provided by the invention is as follows:
the invention discloses a display device, comprising: the display panel comprises a display area, wherein scanning lines and data lines which are criss-cross and a plurality of pixel units defined by the intersection of the scanning lines and the data lines are arranged in the display area;
the display device further comprises a control circuit and a gate drive circuit:
the control circuit is used for receiving a frame data signal and carrying out integrity judgment on the frame data signal; and generating a missing detection signal when it is determined that the received frame data signal is missing; when the received frame data signal is judged to be a complete signal, generating an emptying signal; when the missing detection signal or the clearing signal is detected to be generated, generating a zero clearing signal and inputting the zero clearing signal to the grid drive circuit;
and the grid driving circuit comprises a plurality of cascaded grid driving units, each grid driving unit respectively inputs scanning signals to a row of scanning lines, and the grid driving circuit performs zero clearing reset and outputs low-level scanning signals after receiving the zero clearing signals.
Preferably, the control circuit includes a timing control circuit and a level conversion circuit;
the timing control circuit includes:
the integrity judgment module is used for receiving a frame data signal and carrying out integrity judgment on the frame data signal;
the emptying signal generating module is used for generating an emptying signal to be input into the level conversion circuit after the control circuit receives a complete frame of data signal;
the missing detection signal generation module is used for generating a missing detection signal to be input into the level conversion circuit after the control circuit receives a frame data signal with missing;
the level conversion circuit is used for generating a clear signal to be input into the grid drive circuit when receiving a clear signal or a missing detection signal.
Preferably, the level conversion circuit includes:
the OR operation module is used for generating an operation signal when receiving the emptying signal or the missing detection signal;
and the boosting module is used for boosting the operation signal to form a zero clearing signal and inputting the zero clearing signal to the gate drive circuit.
Preferably, the control circuit includes a timing control circuit and a level conversion circuit;
the timing control circuit includes:
the integrity judgment module is used for receiving a frame data signal and carrying out integrity judgment on the frame data signal;
the clearing signal generating module is used for generating a clearing signal after the control circuit receives a complete frame data signal;
the control circuit is used for receiving a frame data signal which has a missing state and generating a missing detection signal;
the OR operation module is used for generating an operation signal to be input into the level conversion circuit when detecting that the clear signal or the missing detection signal is generated;
the level shift circuit includes:
and the boosting module is used for boosting the operation signal to form a zero clearing signal and inputting the zero clearing signal to the gate drive circuit.
Preferably, after the clear signal is input to the gate driving circuit, the level shift circuit controls the clock signal at the high level input to the gate driving circuit to fall to the low level, and the clock signal at the low level maintains the low level.
The present invention also discloses a driving method of a display device, the display device including: the display device comprises a display panel, a control circuit and a grid driving circuit; the display panel comprises a display area, wherein scanning lines and data lines which are criss-cross and a plurality of pixel units defined by the intersection of the scanning lines and the data lines are arranged in the display area; the grid driving circuit comprises a plurality of cascaded grid driving units, and each grid driving unit inputs a scanning signal to a row of scanning lines; the driving method includes the steps of:
the first step is as follows: the control circuit receives a frame data signal and carries out integrity judgment on the frame data signal;
the second step is that: when the frame data signal is complete, the control circuit generates a clearing signal; when the frame data signal is missing, the control circuit generates a missing detection signal;
the third step: when the missing detection signal or the clearing signal is detected to be generated, the control circuit generates a clearing signal and inputs the clearing signal to the grid drive circuit;
the fourth step: the grid drive circuit performs zero clearing reset after receiving the zero clearing signal and outputs a low-level scanning signal.
Preferably, the driving method specifically includes the steps of:
the first step is as follows: the time sequence control circuit receives a frame data signal and carries out integrity judgment on the frame data signal;
the second step is that: when the frame data signal is complete, the time sequence control circuit generates an emptying signal and inputs the emptying signal into the level conversion circuit;
when the frame data signal is missing, the time sequence control circuit generates a missing detection signal and inputs the missing detection signal into the level conversion circuit;
the third step: when receiving a clear signal or a missing detection signal, the level conversion circuit generates a clear signal and inputs the clear signal into the gate drive circuit;
the fourth step: the grid drive circuit performs zero clearing reset after receiving the zero clearing signal and outputs a low-level scanning signal.
Preferably, the third step specifically comprises:
when receiving the clear signal or the missing detection signal, the level conversion circuit generates an operation signal;
the level conversion circuit boosts the operation signal to form a zero clearing signal, and inputs the zero clearing signal to the gate drive circuit.
Preferably, the driving method specifically includes the steps of:
the first step is as follows: the time sequence control circuit receives a frame data signal and carries out integrity judgment on the frame data signal;
the second step is that: when the frame data signal is complete, the time sequence control circuit generates an emptying signal;
when the frame data signal is missing, the time sequence control circuit generates a missing detection signal;
the third step: when detecting that the clear signal or the missing detection signal is generated, the time sequence control circuit generates an operation signal and inputs the operation signal into the level conversion circuit;
the fourth step: the level conversion circuit performs voltage boosting processing on the operation signal to form a zero clearing signal, and the zero clearing signal is input into the gate drive circuit;
the fifth step: the grid drive circuit performs zero clearing reset after receiving the zero clearing signal and outputs a low-level scanning signal.
Preferably, after the clear signal is input to the gate driving circuit, the level shift circuit controls the clock signal at the high level input to the gate driving circuit to fall to the low level, and the clock signal at the low level maintains the low level.
Compared with the prior art, the time sequence control circuit is additionally provided with the missing detection signal generation module, and when a frame of data signal with a missing state is received, the missing detection signal generates a missing detection signal; the missing detection signal compensates for the vacancy of the clear signal after receiving a frame of data signal with missing, and when the missing detection signal or the clear signal is detected to be generated, the control circuit generates a clear signal to be input into the gate drive circuit, so that the control circuit can clear and reset the gate drive circuit after receiving any frame of data signal; when the control circuit judges that the received frame data signal is absent, the level conversion circuit controls the clock signal which is input into the grid drive circuit and is at the high level to be reduced to the low level, and the clock signal at the low level maintains the low level, so that the working stability of the GDM is ensured.
Drawings
The present invention will be further described in the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings.
FIG. 1 is a schematic diagram of a display device using GDM technology;
FIG. 2 is a schematic diagram of a conventional display device;
FIG. 3 is a timing diagram illustrating a normal driving sequence of the display device shown in FIG. 2;
FIG. 4 is a timing diagram illustrating an abnormal driving operation of the display device shown in FIG. 2;
FIG. 5 is a schematic view of a display device according to the present invention;
FIG. 6 is a schematic diagram of a control circuit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a driving timing sequence of the display device according to the present invention;
fig. 8 is a schematic structural diagram of a control circuit of another embodiment of the display device of the invention.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will be made with reference to the accompanying drawings. It is obvious that the drawings in the following description are only some examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be derived from them without inventive effort.
For the sake of simplicity, the drawings only schematically show the parts relevant to the present invention, and they do not represent the actual structure as a product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "one" means not only "only one" but also a case of "more than one".
The structure of the display device of the present invention is shown in fig. 5, and the display device includes: display panel 01, gate driving circuit 04, and control circuit. The display panel 01 includes a display area and a circuit placement area located at a side of the display area, the display area is provided with criss-cross scanning lines and data lines, and a plurality of pixel units defined by the scanning lines and the data lines in a crossed manner, and each pixel unit is provided with a thin film transistor and a pixel electrode. The grid electrode of the thin film transistor is connected with a row of scanning lines, the source electrode of the thin film transistor is connected with a row of data lines, and the drain electrode of the thin film transistor is connected with the pixel electrode.
The gate driving circuit 04 is located in the circuit placement region at the side of the display region, and includes a plurality of cascaded gate driving units, and each gate driving unit inputs a scanning signal to a corresponding row of scanning lines. When the scanning Signal is at a high level, the thin film transistor connected to the scanning line is in a conducting state, and a data Signal (Signal) is transmitted to the pixel electrode through the thin film transistor to control the display of the pixel area.
The control circuit includes a timing control circuit 02 and a level conversion circuit 03. The control circuit receives a data signal, the data signal being divided into a plurality of frames according to a start symbol or an end symbol, including: the Fm-1 frame data signal, the Fm +1 frame data signal … …, and the frame data signal has a missing part when the duration of the frame data signal is shorter than the preset value.
The control circuit receives a frame data signal and carries out integrity judgment on the frame data signal; when the received frame data signal is judged to be a complete signal, an emptying signal CLRI is generated, namely the potential on an emptying signal wire in the control circuit is increased from a low potential to a high potential, and is reduced to the low potential after the high potential is maintained for a short period of time; when it is determined that a frame of received data signal is Missing, a Missing detection signal DM (Date Missing) is generated, i.e., the potential on the Missing detection signal line in the control circuit is raised from a low potential to a high potential, and is lowered to the low potential after the high potential is maintained for a short period of time. When the absence detection signal DM or the clear signal CLRI is detected to be generated, the control circuit generates the clear signal CLRO and inputs the clear signal CLRO to the gate driving circuit 04.
When the absence of a frame of data signal is judged, the control circuit of the display device generates an absence detection signal DM, the absence detection signal DM compensates the absence of a clearing signal CLRI when the absence of the data signal exists, and when the absence detection signal DM or the clearing signal CLRI is detected, the control circuit generates a clear signal CLRO to be input into the gate drive circuit 04 so as to ensure that the control circuit can clear and reset the gate drive circuit 04 after receiving any frame of data signal. The or operation of the missing detection signal DM and the clear signal CLRI can be performed in the timing control circuit 02 or in the level shift circuit 03.
The driving method of the display device of the invention comprises the following steps:
the first step is as follows: the control circuit receives a frame data signal and carries out integrity judgment on the frame data signal;
the second step is that: when the frame data signal is complete, the control circuit generates a clear signal CLRI; when the frame data signal is missing, the control circuit generates a missing detection signal DM;
the third step: when detecting that the clear signal CLRI or the missing detection signal DM is generated, the control circuit generates a clear signal CLRO and inputs the clear signal CLRO to the gate driving circuit 04;
the fourth step: the gate drive circuit 04, upon receiving the clear signal CLRO, performs clear reset and outputs a low-level scan signal.
The technical solution of the present invention is described in detail with specific examples below.
The first embodiment is as follows:
fig. 6 is a schematic structural diagram of a control circuit in an embodiment of a display device according to the present invention, in which the timing control circuit 02 includes: an integrity judgment module 21, a clear signal generation module 22, and a missing detection signal generation module 23.
After the timing control circuit 02 receives a frame of data signal, the integrity judgment module 21 performs integrity judgment on the frame of data signal, and inputs the judgment result into the clear signal generation module 22 and the missing detection signal generation module 23, where the clear signal generation module 22 and the missing detection signal generation module 23 respectively generate a clear signal CLRI and a missing detection signal DM and input the signals to the level conversion circuit 03.
Fig. 7 shows a driving timing diagram of the display device. When the frame data signal is complete, the clear signal generating module 22 generates a clear signal CLRI; when the frame data signal is missing, the clear signal CLRI maintains a low level, and the missing detection signal generating module 23 generates the missing detection signal DM.
The level shift circuit 03 includes an or operation block 31 and a boosting block 32. The OR operation module 31 generates an operation signal OR when receiving the clear signal CLRI OR the missing detection signal DM. That is, the or operation module 31 is electrically connected to the empty signal generation module 22 through the empty signal line, the missing detection signal generation module 23 through the missing detection signal line, and the boosting module 32 through the operation signal line, and when the potential on the empty signal line or the missing detection signal line is high potential, the potential on the operation signal line is high potential; when the potential on the empty signal line and the potential on the missing detection signal line are both low potential, the potential on the operation signal line is low potential. The boosting module 32 receives the operation signal OR, performs boosting processing on the operation signal OR to form a clear signal CLRO, and inputs the clear signal CLRO to the gate driving circuit 04. The high potential of the clear signal CLRO is higher than the high potential of the clear signal CLRI and higher than the high potential of the missing detection signal DM, so as to meet the voltage requirement of the gate driving circuit 04 on the clear signal CLRO.
The level shift circuit 03 inputs the gate start signal GSP, the clock signals CLK1, CLK2, CLK3, and CLK4 to the gate driving circuit 04, and all of the plurality of clock signals are pulse signals with high and low levels staggered when the frame data signal is complete. After the clear signal CLRO is input to the gate driver circuit 04, the level shifter circuit 03 controls the clock signal at the high level to fall to the low level, and controls the clock signal at the low level to maintain the low level. As shown in fig. 7, since the data signal of the Fm th frame is missing, the clock signals CLK2 and CLK3 are not pulled low, and the abnormality is maintained at a high level. At the falling edge of the missing detection signal DM, the level shift circuit 03 controls the clock signals CLK2 and CLK3 at the high level to fall to the low level, and controls the clock signals CLK1 and CLK4 at the low level to maintain the low level, thereby preventing a large current from occurring in the display device and ensuring that the timing of the gate driving circuit 04 is normal.
In this embodiment, the driving method of the display device specifically includes the following steps:
the first step is as follows: the time sequence control circuit 02 receives a frame data signal and carries out integrity judgment on the frame data signal;
the second step is that: when the frame data signal is complete, the timing control circuit 02 outputs a clear signal CLRI; when the frame data signal is missing, the timing control circuit 02 outputs a missing detection signal DM;
thirdly, when receiving the clear signal CLRI or the missing detection signal DM, the level shifter 03 generates the clear signal CLRO and inputs the clear signal CLRO to the gate driving circuit 04;
more specifically, when receiving the clear signal CLRI OR the missing detection signal DM, the level shifter circuit 03 generates an operation signal OR; the level conversion circuit 03 boosts the operation signal OR to form a clear signal CLRO, and inputs the clear signal CLRO to the gate drive circuit 04;
the fourth step: the gate drive circuit 04, upon receiving the clear signal CLRO, performs clear reset and outputs a low-level scan signal.
The driving method of the present embodiment further includes: after the clear signal CLRO is input to the gate driver circuit 04, the level shifter circuit 03 controls the clock signal at the high level input to the gate driver circuit 04 to fall to the low level, and the clock signal at the low level maintains the low level.
Example two:
fig. 8 is a schematic structural diagram of a control circuit in another embodiment of the display device of the present invention, which is different from the first embodiment in that: the or operation module 31 is located in the timing control circuit 02.
The control circuit includes sequential control circuit 02 and level shift circuit 03, and sequential control circuit 02 includes: the integrity judgment module 21, the clear signal generation module 22, the missing detection signal generation module 23 and the or operation module 31.
After the timing control circuit 02 receives a frame of data signal, the integrity judgment module 21 performs integrity judgment on the frame of data signal, and inputs the judgment result to the clear signal generation module 22 and the missing detection signal generation module 23, and the clear signal generation module 22 and the missing detection signal generation module 23 respectively generate a clear signal CLRI and a missing detection signal DM and input the clear signal CLRI and the missing detection signal DM to the or operation module 31.
Fig. 7 shows a driving timing diagram of the display device. When the frame data signal is judged to be complete, the clear signal generating module 22 generates a clear signal CLRI; when it is determined that the frame data signal is missing, the clear signal CLRI maintains a low level, and the missing detection signal generating module 23 generates the missing detection signal DM.
The OR operation module 31 generates an operation signal OR when receiving the clear signal CLRI OR the missing detection signal DM. That is, the or operation module 31 is electrically connected to the empty signal generation module 22 through the empty signal line, the missing detection signal generation module 23 through the missing detection signal line, and the level conversion circuit 03 through the operation signal line, and when the potential on the empty signal line or the missing detection signal line is high potential, the potential on the operation signal line is high potential; when the potential on the empty signal line and the potential on the missing detection signal line are both low potential, the potential on the operation signal line is low potential.
The level shift circuit 03 includes a boosting module 32, and the boosting module 32 receives the operation signal OR, performs a boosting process on the operation signal OR to form a clear signal CLRO, and inputs the clear signal CLRO to the gate drive circuit 04. The high potential of the clear signal CLRO is higher than the high potential of the clear signal CLRI and higher than the high potential of the missing detection signal DM, so as to meet the voltage requirement of the gate driving circuit 04 on the clear signal CLRO. The level shift circuit 03 also receives the gate start signal GSP and the missing detection signal DM output by the timing control circuit 02.
The level shift circuit 03 inputs the gate start signal GSP, the clock signals CLK1, CLK2, CLK3, and CLK4 to the gate driving circuit 04, and all of the plurality of clock signals are pulse signals with high and low levels staggered when the frame data signal is complete. After the clear signal CLRO is input to the gate driving circuit 04, the level shifter circuit 03 controls the clock signal at the high level to fall to the low level according to the missing detection signal DM, and controls the clock signal at the low level to maintain the low level. As shown in fig. 7, since the data signal of the Fm th frame is missing, the clock signals CLK2 and CLK3 are not pulled low, and the abnormality is maintained at a high level. At the falling edge of the missing detection signal DM, the level shift circuit 03 controls the clock signals CLK2 and CLK3 at the high level to fall to the low level, and controls the clock signals CLK1 and CLK4 at the low level to maintain the low level, thereby preventing a large current from occurring in the display device and ensuring that the timing of the gate driving circuit 04 is normal.
In this embodiment, the driving method of the display device includes the steps of:
the first step is as follows: the time sequence control circuit 02 receives a frame data signal and carries out integrity judgment on the frame data signal;
the second step is that: when the frame data signal is complete, the timing control circuit 02 outputs a clear signal CLRI; when the frame data signal is missing, the timing control circuit 02 outputs a missing detection signal DM;
the third step: the OR operation module 31 in the timing control circuit 02 receives the clear signal CLRI and the missing detection signal DM, and when detecting that the clear signal CLRI OR the missing detection signal DM is generated, the timing control circuit 02 generates an operation signal OR to input the operation signal OR to the level conversion circuit 03;
the fourth step: the level conversion circuit 03 receives the operation signal OR, boosts the operation signal OR to form a clear signal CLRO, and inputs the clear signal CLRO to the gate drive circuit 04;
the fifth step: the gate drive circuit 04 performs zero clearing reset and outputs a low-level scan signal after receiving the zero clearing single pulse of the zero clearing signal CLRO.
It should be noted that the above embodiments can be freely combined as necessary. The above description is only a preferred embodiment of the present invention, but the present invention is not limited to the details of the above embodiment, and it should be noted that, for those skilled in the art, it is possible to make various modifications and alterations without departing from the principle of the present invention, and it should be understood that these modifications, alterations and equivalents should be regarded as the protection scope of the present invention.
Claims (8)
1. A display device, comprising: the display panel comprises a display area, wherein scanning lines and data lines which are criss-cross and a plurality of pixel units defined by the intersection of the scanning lines and the data lines are arranged in the display area;
the device is characterized by further comprising a control circuit and a grid driving circuit:
the control circuit is used for receiving a frame data signal and carrying out integrity judgment on the frame data signal; and generating a missing detection signal when it is determined that the received frame data signal is missing; when the received frame data signal is judged to be a complete signal, generating an emptying signal; when the missing detection signal or the clearing signal is detected to be generated, generating a zero clearing signal and inputting the zero clearing signal to the grid drive circuit;
the grid driving circuit comprises a plurality of cascaded grid driving units, each grid driving unit respectively inputs scanning signals to a row of scanning lines, and the grid driving circuit performs zero clearing reset and outputs low-level scanning signals after receiving the zero clearing signals; the control circuit comprises a time sequence control circuit and a level conversion circuit;
the timing control circuit includes:
the integrity judgment module is used for receiving a frame data signal and carrying out integrity judgment on the frame data signal;
the emptying signal generating module is used for generating an emptying signal to be input into the level conversion circuit after the control circuit receives a complete frame of data signal;
the missing detection signal generation module is used for generating a missing detection signal to be input into the level conversion circuit after the control circuit receives a frame data signal with missing;
the level conversion circuit is used for generating a clear signal to be input into the grid drive circuit when receiving a clear signal or a missing detection signal.
2. The display device according to claim 1,
the level shift circuit includes:
the OR operation module is used for generating an operation signal when receiving the emptying signal or the missing detection signal;
and the boosting module is used for boosting the operation signal to form a zero clearing signal and inputting the zero clearing signal to the gate drive circuit.
3. The display device according to claim 1 or 2, wherein:
after the clear signal is input to the gate driving circuit, the level conversion circuit controls the clock signal which is input to the gate driving circuit and is at the high level to be reduced to the low level, and the clock signal which is at the low level maintains the low level.
4. A driving method of a display device, the display device comprising: the display device comprises a display panel, a control circuit and a grid driving circuit; the display panel comprises a display area, wherein scanning lines and data lines which are criss-cross and a plurality of pixel units defined by the intersection of the scanning lines and the data lines are arranged in the display area; the grid driving circuit comprises a plurality of cascaded grid driving units, and each grid driving unit inputs a scanning signal to a row of scanning lines; the driving method is characterized by comprising the following specific steps:
the first step is as follows: the time sequence control circuit receives a frame data signal and carries out integrity judgment on the frame data signal;
the second step is that: when the frame data signal is complete, the time sequence control circuit generates an emptying signal and inputs the emptying signal into the level conversion circuit;
when the frame data signal is missing, the time sequence control circuit generates a missing detection signal and inputs the missing detection signal into the level conversion circuit;
the third step: when receiving a clear signal or a missing detection signal, the level conversion circuit generates a clear signal and inputs the clear signal into the gate drive circuit;
the fourth step: the grid drive circuit performs zero clearing reset after receiving the zero clearing signal and outputs a low-level scanning signal.
5. The method for driving a display device according to claim 4, wherein the third step is specifically:
when receiving the clear signal or the missing detection signal, the level conversion circuit generates an operation signal;
the level conversion circuit boosts the operation signal to form a zero clearing signal, and inputs the zero clearing signal to the gate drive circuit.
6. The method for driving a display device according to claim 4, wherein:
after the clear signal is input to the gate driving circuit, the level conversion circuit controls the clock signal which is input to the gate driving circuit and is at the high level to be reduced to the low level, and the clock signal which is at the low level maintains the low level.
7. A driving method of a display device, the display device comprising: the display device comprises a display panel, a control circuit and a grid driving circuit; the display panel comprises a display area, wherein scanning lines and data lines which are criss-cross and a plurality of pixel units defined by the intersection of the scanning lines and the data lines are arranged in the display area; the grid driving circuit comprises a plurality of cascaded grid driving units, and each grid driving unit inputs a scanning signal to a row of scanning lines; the driving method is characterized by comprising the following specific steps:
the first step is as follows: the time sequence control circuit receives a frame data signal and carries out integrity judgment on the frame data signal;
the second step is that: when the frame data signal is complete, the time sequence control circuit generates an emptying signal;
when the frame data signal is missing, the time sequence control circuit generates a missing detection signal;
the third step: when detecting that the clear signal or the missing detection signal is generated, the time sequence control circuit generates an operation signal and inputs the operation signal into the level conversion circuit;
the fourth step: the level conversion circuit performs voltage boosting processing on the operation signal to form a zero clearing signal, and the zero clearing signal is input into the gate drive circuit;
the fifth step: the grid drive circuit performs zero clearing reset after receiving the zero clearing signal and outputs a low-level scanning signal.
8. The method for driving a display device according to claim 7, wherein:
after the clear signal is input to the gate driving circuit, the level conversion circuit controls the clock signal which is input to the gate driving circuit and is at the high level to be reduced to the low level, and the clock signal which is at the low level maintains the low level.
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