CN109471394A - A kind of multi-channel wide dynamic range high-speed signal acquisition processing unit - Google Patents
A kind of multi-channel wide dynamic range high-speed signal acquisition processing unit Download PDFInfo
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- CN109471394A CN109471394A CN201811465362.2A CN201811465362A CN109471394A CN 109471394 A CN109471394 A CN 109471394A CN 201811465362 A CN201811465362 A CN 201811465362A CN 109471394 A CN109471394 A CN 109471394A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
- G01R19/2506—Arrangements for conditioning or analysing measured signals, e.g. for indicating peak values ; Details concerning sampling, digitizing or waveform capturing
- G01R19/2509—Details concerning sampling, digitizing or waveform capturing
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/21—Pc I-O input output
- G05B2219/21137—Analog to digital conversion, ADC, DAC
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25033—Pc structure of the system structure, control, syncronization, data, alarm, connect I-O line to interface
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/26—Pc applications
- G05B2219/2612—Data acquisition interface
Abstract
The invention discloses a kind of multi-channel wide dynamic range high-speed signal acquisition processing unit, which includes: synchronization module between the road A collection of simulant signal module, the road B collection of simulant signal module, the road C collection of simulant signal module, the road D collection of simulant signal module, plate, core processing module, data off-chip memory module and the data at PC machine end and control signal interaction module and power module.The present apparatus is realized by signal acquisition circuit and is received to the synchronous of four tunnel analog signals under the control of core processor, and is transformed into numeric field.When more plates cascade, Channel Synchronous is carried out by synchronization module.Gained numeric-field data can be cached in off-chip memory module, and the read-write to memory module is carried out by the control command that interactive module is sent to core processing module according to host computer.The present invention has powerful universality and scalability, provides a high performance feasibility platform for the reception processing of the various analog signals under more scenes, has very big realistic meaning.
Description
Technical field
The present invention relates to analog signal processing, high-speed figure-analog-converted design, FPGA design, high-speed chip external storages to set
The fields such as meter, PC machine IE design and optical port design more particularly to a kind of multi-channel wide dynamic range high-speed signal acquisition processing dress
It sets.
Background technique
High-speed signal acquisition processing is widely used in every field, with the rapid development of science and technology, adopts to signal
Collection processing unit also proposed increasingly higher demands.
Existing signal acquisition and processing apparatus sample rate is low, small for the receivable range of input signal, can be supported
Port number is limited, and the mode interacted with host computer is single, relative to now increasingly diversification, high standard application scenarios, it is difficult
To reach its standard.
Summary of the invention
The purpose of the present invention is in view of the deficiencies of the prior art and propose a kind of multi-channel wide dynamic range high speed signal
Acquisition processing device, realizes the acquisition input for the signal of 1mVpp to 10.8Vpp range, and gain adjustment range is up to
80dB, stepping are accurate to 0.5dB.Amplitude is adjusted to after analog-digital converter preferably inputs and carries out analog-digital conversion.
Later, it is passed to FPGA and carries out further signal processing, during this period, data can be temporarily stored in DDR3 SDRAM.Finally
It can be by PC machine IE or optical port, under the control of host computer, by data on-demand delivery to PC machine.
The object of the present invention is achieved like this:
A kind of multi-channel wide dynamic range high-speed signal acquisition processing unit, feature are that the device includes: the road A collection of simulant signal
Synchronous mould between module, the road B collection of simulant signal module, the road C collection of simulant signal module, the road D collection of simulant signal module, plate
Block, core processing module, data off-chip memory module and the data at PC machine end and control signal interaction module and power supply mould
Block, the power module respectively with the road A collection of simulant signal module, the road B collection of simulant signal module, the road C collection of simulant signal
Synchronization module, core processing module, data off-chip memory module and and PC machine between module, the road D collection of simulant signal module, plate
The data and control signal interaction module connection at end；The core processing module respectively with the road A collection of simulant signal module, the road B
Synchronization module, data slice between collection of simulant signal module, the road C collection of simulant signal module, the road D collection of simulant signal module, plate
External storage module and with the data at PC machine end and control signal interaction module connect.
The core processing module is field programmable gate array (FPGA).
It include PCIE interface and optical port (ten thousand mbit ethernets) in the data and control signal interaction module with PC machine end,
It can choose one of both to carry out data transmission.
Cascade signal acquisition process may be implemented by synchronization module between the plate.
Compared with prior art, the beneficial effects of the present invention are:
1) present invention realizes the acquisition input for the signal of 1mVpp to 10.8Vpp range, and gain adjustment range is up to
80dB, stepping are accurate to 0.5dB.
2) present invention realizes the Analog-digital Converter that resolution ratio reaches 16bit, and sample rate is up to 125 MSPS.It mentions significantly
The high precision of sampled data.
3) present invention realizes the input that veneer is up to the analog signal in 4 channels, and 4 channel datas can be located parallel
Reason, substantially increases treatment effeciency.
4) present invention uses synchronization module, realizes with can be convenient and cascades between plate, substantially increases the scalability of system.
5) present invention realizes optional and host computer interactive mode, provides PC machine IE2.0 × 4 and SFP optical port (Wan Zhao
Ethernet) two kinds of approach, substantially increase the universality of device.
Detailed description of the invention
Fig. 1 is structure of the invention block diagram；
Fig. 2 is signal processing flow figure in the embodiment of the present invention 1；
Fig. 3 is the structural block diagram of the embodiment of the present invention 2；
Fig. 4 is signal processing flow figure in the embodiment of the present invention 2.
Specific embodiment
Refering to fig. 1, the present invention includes:
Power module 9, external power supply input interface, including from PC machine IE power supply and external adapter power supply two ways, lead to
The level conversion for crossing DC-DC and LDO two major classes power supply chip, have stablize export 9V, 5V, 3.3V, 2.5V, 2V, 1.8V,
1.5V, 1.2V, 1V, 0.75V amount to 10 kinds of voltages, the respectively road A collection of simulant signal module 1, the road B collection of simulant signal module
2, synchronization module 5, core processing module 6, data between the road C collection of simulant signal module 3, the road D collection of simulant signal module 4, plate
Off-chip memory module 7 and with the data at PC machine end and control signal interaction module 8 provide respectively needed for voltage；
The road A collection of simulant signal module 1, the road B collection of simulant signal module 2, the road C collection of simulant signal module 3, the road D simulation letter
Number acquisition module 4, is connected, for receiving input signal and amplifying/contract with power module 9 and core processing module 6
Small, filtering, analog-digital conversion；
Synchronization module 5 is connect with core processing module 6 between plate, for the synchronization under the cascade mode of more plates, between each access；
Core processing module 6, with the road A collection of simulant signal module 1, the road B collection of simulant signal module 2, the road C collection of simulant signal
Synchronization module 5, data off-chip memory module 7 and the data with PC machine end between module 3, the road D collection of simulant signal module 4, plate
And control signal interaction module 8 connects, and for the control to collection of simulant signal module, handles the number of the numeric field received
According to, data interaction with DDR3 SDRAM, operated with the data interaction of host computer etc.；
Data off-chip memory module 7 is connected with core processing module 6, completes the temporary function of mass data；
With the data and control signal interaction module 8 at PC machine end, it is connected with core processing module 6, completes to core processor
Transmit control instruction and with to host computer transmission data interactive function.
Embodiment 1
Refering to fig. 1 and Fig. 2, by taking veneer works independently as an example.
The four tunnel input signal in 1mVpp to 10.8Vpp range inputs the road A simulation letter by coaxial cable respectively first
Number acquisition module 1, the road B collection of simulant signal module 2, the road C collection of simulant signal module 3 and the road D collection of simulant signal module 4,
The amplification of signal is performed in accordance under the control for the control signal that core processing module 6 provides according to the amplitude of input signal
Or reduce, and complete conversion work from analog domain to numeric field, obtain four railway digital signals, be passed to core processing module 6 into
Row processing.
In core processing module 6, according to from PC machine end data and the control transmitted of control signal interaction module 8 believe
Number, carry out the down-sampled equal operation of certain multiple.During this period, need to carry out data interaction with data off-chip memory module 7, it is real
The temporary function of existing data.
The data completed are handled, from the data and the control signal that transmits of control signal interaction module 8 with PC machine end
Under control, PC machine end is selectively uploaded to.
So far a whole set of acquisition and processing to four road signals are completed.
Embodiment 2
Refering to Fig. 3 and Fig. 4, by taking two boards cascade use as an example.
The eight tunnel input signal in 1mVpp to 10.8Vpp range inputs two systems by coaxial cable respectively first
The road A collection of simulant signal module 1, the road B collection of simulant signal module 2, the road C collection of simulant signal module 3 and the road D analog signal are adopted
Collect module 4, according to the amplitude of input signal, under the control for the control signal that respective core processing module 6 provides, accordingly into
Row signal zooms in or out.Hereafter, between plate under the control of synchronization module 5, the mould of the same-phase of eight road parallel signals is carried out
For near-field to the conversion of numeric field, eight railway digital signals of gained phase coherence are passed to respective core processing module 6 respectively.
In core processing module 6, according to from PC machine end data and the control transmitted of control signal interaction module 8 believe
Number, carry out the down-sampled equal operation of certain multiple.During this period, need to carry out data interaction with data off-chip memory module 7, it is real
The temporary function of existing data.
The data completed are handled, from the data and the control signal that transmits of control signal interaction module 8 with PC machine end
Under control, PC machine end is selectively uploaded to.
So far a whole set of acquisition and processing to eight road signals are completed.
Claims (2)
1. a kind of multi-channel wide dynamic range high-speed signal acquisition processing unit, which is characterized in that the device includes: A simulation letter
Number acquisition module (1), the road B collection of simulant signal module (2), the road C collection of simulant signal module (3), the road D collection of simulant signal mould
Synchronization module (5), core processing module (6), data off-chip memory module (7), data and control with PC machine end between block (4), plate
Signal interaction module (8) processed and power module (9), the power module (9) respectively with the road A collection of simulant signal module (1),
It is synchronous between the road B collection of simulant signal module (2), the road C collection of simulant signal module (3), the road D collection of simulant signal module (4), plate
Module (5), core processing module (6), data off-chip memory module (7) and with the data at PC machine end and control signal interaction mould
Block (8) connection；The core processing module (6) respectively with the road A collection of simulant signal module (1), the road B collection of simulant signal module
(2), synchronization module (5), data slice external memory between the road C collection of simulant signal module (3), the road D collection of simulant signal module (4), plate
It stores up module (7) and is connect with the data at PC machine end and control signal interaction module (8)；Wherein:
The core processing module (6) is field programmable gate array, that is, FPGA；
In the data and control signal interaction module (8) with PC machine end include PCIE interface and optical port select one of both into
The transmission of row data.
2. multi-channel wide dynamic range high-speed signal acquisition processing unit according to claim 1, it is characterised in that: pass through
Synchronization module (5) realizes cascade signal acquisition process between the plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811465362.2A CN109471394B (en) | 2018-12-03 | 2018-12-03 | Multichannel wide dynamic range high-speed signal acquisition processing device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811465362.2A CN109471394B (en) | 2018-12-03 | 2018-12-03 | Multichannel wide dynamic range high-speed signal acquisition processing device |
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| Publication Number | Publication Date |
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| CN109471394A true CN109471394A (en) | 2019-03-15 |
| CN109471394B CN109471394B (en) | 2023-09-26 |
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Citations (5)
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|---|---|---|---|---|
| CA2090862A1 (en) * | 1990-09-04 | 1992-03-05 | Gilbert P. Hyatt | Memory system |
| CN102589611A (en) * | 2011-01-13 | 2012-07-18 | 江苏东华测试技术股份有限公司 | Device for testing, analyzing and collecting dynamic signal |
| CN105278404A (en) * | 2015-09-18 | 2016-01-27 | 广州北航新兴产业技术研究院 | Base-band device based on software radio |
| CN108152768A (en) * | 2017-11-29 | 2018-06-12 | 华东师范大学 | A kind of NMR signal acquisition processing device |
| WO2018113165A1 (en) * | 2016-12-21 | 2018-06-28 | 国网电力科学研究院 | Configurable device for monitoring vibration and swing states of hydraulic turbine set, and data acquisition method |
-
2018
- 2018-12-03 CN CN201811465362.2A patent/CN109471394B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2090862A1 (en) * | 1990-09-04 | 1992-03-05 | Gilbert P. Hyatt | Memory system |
| CN102589611A (en) * | 2011-01-13 | 2012-07-18 | 江苏东华测试技术股份有限公司 | Device for testing, analyzing and collecting dynamic signal |
| CN105278404A (en) * | 2015-09-18 | 2016-01-27 | 广州北航新兴产业技术研究院 | Base-band device based on software radio |
| WO2018113165A1 (en) * | 2016-12-21 | 2018-06-28 | 国网电力科学研究院 | Configurable device for monitoring vibration and swing states of hydraulic turbine set, and data acquisition method |
| CN108152768A (en) * | 2017-11-29 | 2018-06-12 | 华东师范大学 | A kind of NMR signal acquisition processing device |
Non-Patent Citations (1)
| Title |
|---|
| 崔婧;沈三民;叶勇;: "基于FPGA的模数混合编帧的采集系统", 科学技术与工程, no. 01 * |
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| CN109471394B (en) | 2023-09-26 |
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