CN109471178B

CN109471178B - Earth electric field sensor system and electrode embedding method thereof

Info

Publication number: CN109471178B
Application number: CN201811300373.5A
Authority: CN
Inventors: 卢永; 孙振强; 张敏; 单菡; 王佳; 徐年
Original assignee: JIANGSU EARTHQUAKE ADMINISTRATION
Current assignee: JIANGSU EARTHQUAKE ADMINISTRATION
Priority date: 2018-11-02
Filing date: 2018-11-02
Publication date: 2020-10-27
Anticipated expiration: 2038-11-02
Also published as: CN109471178A

Abstract

The invention discloses a ground electric field sensor system and an electrode embedding method thereof. The existing ground electric field signal long-distance transmission loses weak information. The public electrode and the south-north direction electrode are connected into a preceding stage passive band-pass filter of a preceding stage signal conditioning circuit, and the public electrode and the east-west direction electrode are connected into a preceding stage passive band-pass filter of another preceding stage signal conditioning circuit; after the ground electric field signal is transmitted into the front-stage signal conditioning circuit, the ground electric field signal is filtered by a front-stage passive band-pass filter, amplified by a front-stage mixed instrument amplifier, filtered by a front-stage active band-pass filter and signal conditioning by a front-stage single-end-to-differential circuit in sequence in the front-stage signal conditioning circuit, and the differential signal is output to a corresponding rear-stage signal conditioning circuit for further signal conditioning. The pre-stage circuit adopts a hybrid instrument amplifier, and has the advantages of high input impedance, low noise and low offset; the electrode burying method ensures that the electrode can be in good contact with a soil medium, and enhances the long-term stability of the electrode in work.

Description

Earth electric field sensor system and electrode embedding method thereof

Technical Field

The invention relates to the technical field of geophysical electric field exploration, in particular to a geoelectric field sensor system and an electrode embedding method thereof.

Background

The existing domestic ground electric field instrument is mainly a ZD9A type ground electric field instrument, electrode signals of the current domestic ground electric field instrument are collected by a center and directly transmitted to a recording room through a cable without any signal processing, because electric field signals are weak signals, weak useful information is lost in long-distance transmission, the extraction of the ground electric field information is not favorable, and if the recording room is too close to the center collection point, the interference of personnel activities, commercial power and the like in the recording room is difficult to avoid.

Disclosure of Invention

In view of the above technical defects, an object of the present invention is to provide a ground electric field sensor system with front and rear stage monolithic structures, wherein the front stage part performs signal conditioning on a high-impedance weak voltage signal between electrodes nearby, which is beneficial to long-distance transmission of the signal and improves the signal-to-noise ratio; the rear-stage part further conditions signals transmitted from the front-stage part in a long distance, and is suitable for acquiring and processing data. The invention also aims to provide an electrode burying method, which can ensure that the electrode can be in good contact with a soil medium, enhance the long-term stability of the electrode in working, effectively improve the observation quality of a ground electric field, effectively shield the electric field interference of the surrounding environment and ensure the accuracy of electric field signal measurement.

The invention relates to a ground electric field sensor system, which comprises a preceding stage signal conditioning circuit and a subsequent stage signal conditioning circuit; the front stage signal conditioning circuit is placed in a front-end observation field, and the rear stage signal conditioning circuit is placed in an observation room; the preceding-stage signal conditioning circuit comprises a preceding-stage passive band-pass filter, a preceding-stage hybrid instrument amplifier, a preceding-stage active band-pass filter and a preceding-stage single-end-to-differential circuit; the public electrode and the south-north direction electrode are connected into a preceding passive band-pass filter of a preceding signal conditioning circuit, and are connected into a preceding passive band-pass filter of another preceding signal conditioning circuit together with the east-west direction electrode; after ground electric field signals detected by the south-north orientation electrode and the common electrode or the east-west orientation electrode and the common electrode are transmitted into the front-stage signal conditioning circuit, differential signals are output to a corresponding rear-stage signal conditioning circuit after being filtered by a front-stage passive band-pass filter, amplified by a front-stage hybrid instrument amplifier, filtered by a front-stage active band-pass filter and signal conditioning by a front-stage single-end to differential circuit in sequence in the front-stage signal conditioning circuit; the post-stage signal conditioning circuit comprises a post-stage passive band-pass filter, a post-stage instrument amplifier, a zero setting circuit, a post-stage Fliege wave trap, a post-stage voltage following and low-pass filter, a post-stage amplifying and single-end-to-differential circuit, an A/D converter and a controller; after a signal output by the front-stage signal conditioning circuit is filtered by a rear-stage passive band-pass filter, amplified by a rear-stage instrument amplifier, filtered by a rear-stage Fliege trap filter, followed and filtered by a rear-stage voltage follower and low-pass filter, amplified by the rear stage and signal-to-differential circuit signal-conditioned by a single-end conversion circuit in sequence, a differential signal is output to an A/D converter, and the A/D converter performs analog-to-digital conversion and then transmits the differential signal to a controller; the controller calculates a zero-setting voltage value, a D/A converter in the zero-setting circuit generates a zero-setting voltage through a control signal, and the zero-setting voltage is output to a voltage reference pin of a rear-stage instrumentation amplifier after passing through a rear-stage voltage follower in the zero-setting circuit, so that zero setting of the rear-stage instrumentation amplifier is realized.

The front-stage passive band-pass filter comprises a resistor II R2, a resistor III R3, a resistor V R5, a capacitor II C2, a capacitor III C3, a capacitor V C5, a diode I D1, a resistor VI R6, a diode II D2, a capacitor eight C8, a capacitor VI C6, a common-mode choke I T1, a capacitor twelve C12, a resistor thirteen R13, a resistor fifteen R15, a resistor seventeen R17, a capacitor thirteen C13, a capacitor ten C10, a diode III D3, a resistor fourteen R14, a diode four D4, a capacitor fifteen C15 and a capacitor fourteen C14; the common electrode is connected with the input end E1 of the first coil in the first common mode choke coil T1, and the south-north orientation electrode or the east-west orientation electrode is connected with the input end E1+ of the second coil in the first common mode choke coil T1; one end of the capacitor twelve C12 is connected with the output end of the coil I in the common mode choke I T1, and one end of the capacitor three C3 is connected with the output end of the coil II in the common mode choke I T1; one end of the second resistor R2 is connected with one end of the third resistor R3, and the other end of the second resistor R2 is grounded; the other end of the resistor three R3 is connected with one end of a resistor five R5 and the other end of the capacitor three C3; the other end of the resistor five R5 is connected with one end of the capacitor five C5, the cathode of the diode one D1, one end of the resistor six R6 and the cathode of the diode two D2; the other end of the capacitor five C5 is grounded; the anode of the diode I D1 is connected with one end of the capacitor II C2, and the other end of the capacitor II C2 is grounded; the anode of the diode II D2 is connected with one end of the capacitor eight C8, and the other end of the capacitor eight C8 is grounded; the other end of the resistor six R6 is connected with one end of the capacitor six C6 and outputs a Signal +; the other end of the capacitor six C6 is grounded; one end of the resistor seventeen R17 is grounded, and the other end of the resistor seventeen R17 is connected with one end of the resistor fifteen R15; the other end of the resistor fifteen R15 is connected with one end of a resistor thirteen R13 and the other end of the capacitor twelve C12; the other end of the resistor thirteen R13 is connected with one end of a capacitor thirteen C13, the cathode of a diode three D3, one end of a resistor fourteen R14 and the cathode of a diode four D4; the other end of the capacitor thirteen C13 is grounded; the anode of the diode three D3 is connected with one end of the capacitor ten C10, and the other end of the capacitor ten C10 is grounded; the other end of the resistor fourteen R14 is connected with one end of the capacitor fourteen C14 and outputs a Signal-; the other end of the capacitor fourteen C14 is grounded; the anode of the diode quad D4 is connected to one end of the capacitor fifteen C15, and the other end of the capacitor fifteen C15 is grounded.

The pre-stage hybrid instrumentation amplifier comprises an amplifier I1, a capacitor I C1, a resistor I R1, a resistor seven R7, a resistor twenty I R21, a capacitor sixteen C16, an amplifier four U4, a resistor four R4, a resistor sixteen R16, a resistor twenty five R25 and an amplification control chip I2; the models of the first amplifier U1 and the fourth amplifier U4 are AD 745-745 JR-16; pin 3 of the first amplifier U1 is connected with one end of a first capacitor C1, a first resistor R1 and a seventh resistor R7; one end of the resistor IV R4 is connected with pin 3 of the amplification control chip I U2, and the type of the amplification control chip I U2 is INA 128U; a pin 12 of the first amplifier U1 is connected with the other ends of the first capacitor C1, the first resistor R1 and the fourth resistor R4; pin 6 of the first amplifier U1 is connected with a-6V power supply, and pin 13 of the first amplifier U1 is connected with a +6V power supply; the other end of the resistor seven R7 is connected with a pin 3 of an amplifier four U4, one end of a resistor twenty-one R21 and one end of a capacitor sixteen C16; the other end of the resistor twenty-one R21 is connected with the other end of the capacitor sixteen C16, the pin 12 of the amplifier four U4 and one end of the resistor sixteen R16; pin 13 of the amplifier quad U4 is connected with a +6V power supply, and pin 6 of the amplifier quad U4 is connected with a-6V power supply; the other end of the resistor sixteen R16 is connected with a pin 2 of a first amplification control chip U2; one end of the resistor twenty-five R25 is connected with the pin 8 of the first amplification control chip U2, and the other end of the resistor twenty-five R25 is connected with the pin 1 of the first amplification control chip U2; the pin 5 of the first amplification control chip U2 is grounded, the pin 7 is connected with a +6V power supply, the pin 4 is connected with a-6V power supply, and the pin 6 outputs a Signal 1. And pins 5 of the first amplifier U1 and the fourth amplifier U4 are respectively connected with the positive pole and the negative pole of the output signal of the pre-stage passive band-pass filter.

The front-stage active band-pass filter comprises a capacitor nine C9, a resistor ten R10, a resistor twelve R12, a resistor eight R8, a resistor nine R9, a capacitor four C4, a capacitor seven C7, a capacitor eleven C11, an amplifier three U3A and a resistor eleven R11; amplifier three U3A model No. OP 2177; one end of the capacitor nine C9 is connected with the output signal of the pre-stage hybrid instrument amplifier, and the other end is connected with one ends of the resistor ten R10 and the resistor eight R8; the other end of the resistor eight R8 is connected with one end of a resistor nine R9, a capacitor four C4 and a capacitor seven C7; the other end of the resistor decar 10 is connected with one end of a resistor twelve R12; the other end of R12 is grounded; the other end of the resistor nine R9 is connected with one end of the capacitor eleven C11 and a pin 3 of the amplifier three U3A; the other end of the capacitor eleven C11 is grounded; pin 1 of the amplifier three U3A is connected with one end of a resistor eleven R11, the other end of a capacitor four C4 and the other end of a capacitor seven C7, and outputs a Signal 2; pin 2 of the amplifier three U3A is connected with the other end of the resistor eleven R11; pin 4 of the amplifier three U3A is connected with a-6V power supply, and pin 8 is connected with a +6V power supply.

The front-stage single-ended to differential conversion circuit comprises a resistor twenty R20, a resistor eighteen R18, an amplifier five U5A, an amplifier six U5B, a resistor nineteen R19, a resistor twenty-three R23, a resistor twenty-six R26, a resistor twenty-two R22 and a resistor twenty-four R24; one end of the resistor twenty R20 is connected with one end of the resistor twenty-three R23 and is connected with an output signal of the front-stage active band-pass filter in parallel; the other end of the resistor twenty R20 is connected with a pin 3 of the amplifier five U5A, a pin 2 of the amplifier five U5A is connected with one end of a resistor eighteen R18, and the other end of the resistor eighteen R18 is connected with a pin 1 of the amplifier five U5A and one end of a resistor nineteen R19; the other end of the resistor nineteen R19 outputs a Signal3 +; pin 8 of the amplifier five U5A is connected with a +6V power supply, and pin 4 is connected with a-6V power supply; the other end of the resistor twenty-three R23 is connected with one end of a resistor twenty-two R22 and a pin 6 of an amplifier six U5B, a pin 5 of the amplifier six U5B is connected with one end of a resistor twenty-six R26, and the other end of the resistor twenty-six R26 is grounded; a pin 7 of the amplifier six U5B is connected with the other end of the resistor twenty-two R22 and one end of the resistor twenty-four R24, and the other end of the resistor twenty-four R24 outputs a Signal 3-; pin 4 and pin 8 of amplifier six U5B are both floating; amplifier five U5A and amplifier six U5B employ an integrated amplifier model AD822 AR.

The rear-stage passive band-pass filter comprises a resistor twenty-seven R27, a common-mode choke coil II T2, a resistor twenty-nine R29, a resistor thirty R30, a resistor twenty-eight R28, a capacitor seventeen C17, a capacitor eighteen C18 and a capacitor nineteen C19; the input end of the first coil in the second common mode choke coil T2 is connected with the negative electrode of the output signal of the preceding stage signal conditioning circuit, and the input end of the second coil in the second common mode choke coil T2 is connected with the positive electrode of the output signal of the preceding stage signal conditioning circuit; one end of the resistor twenty-seven R27 is grounded, and the other end of the resistor twenty-seven R27 is connected with one end of the resistor twenty-nine R29 and the output end of the second coil in the common mode choke coil II T2; the other end of the resistor twenty-nine R29 is connected with one end of a capacitor seventeen C17 and one end of a capacitor eighteen C18, and the other end of the capacitor seventeen C17 is grounded; one end of the resistor twenty-eight R28 is grounded, and the other end of the resistor twenty-eight R28 is connected with one end of the resistor thirty-R30 and the output end of the first coil in the common mode choke II T2; the other end of the resistor thirty R30 is connected with the other end of the capacitor eighteen C18 and one end of the capacitor nineteen C19, and the other end of the capacitor nineteen C19 is grounded; the rear-stage instrument amplifier comprises a resistor thirty-one R31 and an amplification control chip II U6; the second amplification control chip U6 adopts a chip with the model number INA 128U; pin 1 of the second amplification control chip U6 is connected with one end of a resistor thirty-one R31, and pin 8 of the second amplification control chip U6 is connected with the other end of the resistor thirty-one R31; pin 4 of the second amplification control chip U6 is connected with a-6V power supply, and pin 7 of the second amplification control chip U6 is connected with a +6V power supply; pin 2 of the amplification control chip II U6 is connected with the connecting end of a capacitor seventeen C17 and a capacitor eighteen C18; a pin 3 of the amplification control chip II U6 is connected with the connecting end of a capacitor eighteen C18 and a capacitor nineteen C19; the pin 6 of the second amplification control chip U6 outputs a Signal 4; the zero setting circuit comprises a zero setting circuit and a zero setting circuit, wherein the zero setting circuit comprises a D/A converter and a post-stage voltage follower; the D/A converter comprises an amplification control chip three U7, a resistor thirty-two R32 and a resistor thirty-three R33; the post-stage voltage follower comprises a resistor thirty-four R34, a resistor thirty-five R35 and an amplifier two U10B; the amplification control chip three U7 adopts a chip with the model number of AD5312 ARMZ; the controller adopts a chip with the model number of SAF-C167 CS-L16M; the model of the amplifier II U10B is OP 2177; pin 2 of the amplification control chip three U7 is connected with a +6V power supply, pin 1 and pin 10 are both grounded, pin 5 is connected with one end of a resistor thirty-two R32, and pin 6 is connected with one end of a resistor thirty-three R33;

pins

3 and 4 of the amplification control chip three U7 are both connected with the reference voltage +2.5 VREF; a pin P3.3 of the controller is connected with a pin 7 of the three amplification control chips U7, a pin TXD of the controller is connected with a pin 8 of the three amplification control chips U7, and a pin RXD of the controller is connected with a pin 9 of the three amplification control chips U7; when the pin P3.3 of the controller is set to be low, the communication between the controller and the three U7 of the amplification control chip is started; the other end of the resistor thirty-two R32 is connected with the other end of the resistor thirty-three R33, one end of the resistor thirty-four R34, one end of the resistor thirty-five R35 and the pin 5 of the amplifier II U10B; the other end of the resistor thirty-four R34 is connected with reference voltage-2.5 VREF, and the other end of the resistor thirty-five R35 is grounded; pin 4 of the second amplifier U10B is connected with a-6V power supply, and pin 8 is connected with a +6V power supply; the pin 6 of the second amplifier U10B is connected with the pin 7 of the second amplifier U10B, and amplifies the pin 5 of the second control chip U6.

The later-stage Fliege wave trap comprises a capacitor twenty C20, a capacitor twenty-one C21, a resistor thirty-six R36, a slide rheostat one R39, a slide rheostat two R37, a resistor thirty-eight R38, a resistor forty R40, a capacitor twenty-two C22, a capacitor twenty-three C23, an amplifier seven U8A, an amplifier eight U8B, a resistor forty-one R41, a resistor forty-two R42 and a resistor forty-three R43; one end of a capacitor twenty C20, a capacitor twenty-one C21, a resistor thirty-six R36 and a resistor forty-three R43 are all connected with an output signal of a rear-stage instrument amplifier; the other end of the capacitor twenty C20 is connected with the movable end of the second slide rheostat R37, the other end of the capacitor twenty-one C21, one fixed end of the first slide rheostat R39, the movable end of the first slide rheostat R39 and the pin 3 of the seven U8A amplifier; the other end of the resistor thirty-six R36 is connected with one fixed end of the second sliding rheostat R37; the other fixed end of the sliding rheostat II R37 is connected with one end of a resistor thirty-eight R38, and the other end of the resistor thirty-eight R38 is grounded; the other fixed end of the slide rheostat R39 is connected with one end of a resistor forty R40, and the other end of the resistor forty R40 is connected with one ends of a pin 7 of an amplifier eight U8B, a capacitor twenty-two C22 and a capacitor twenty-three C23; pin 6 of the amplifier eight U8B is connected with pin 2 of the amplifier seven U8A, one end of a resistor forty-one R41, the other end of a capacitor twenty-two C22 and the other end of a capacitor twenty-three C23; pin 5 of the amplifier eight U8B is connected with one end of a resistor forty-two R42 and the other end of a resistor forty-three R43; pin 4 of the seven U8A amplifier is connected with a-6V power supply, and pin 8 is connected with a +6V power supply; pin 4 and pin 8 of the amplifier eight U8B are both floating; pin 1 of the amplifier seven U8A is connected with the other ends of the resistor forty-two R42 and the resistor forty-one R41, and outputs a Signal 5; the seven U8A and eight U8B amplifiers use integrated amplifiers of model AD822 AR.

The post-stage voltage following and low-pass filter comprises an amplifier nine U9A, a resistor forty-four R44, a resistor forty-five R45, a capacitor twenty-six C26, an amplifier ten U9B, a capacitor twenty-four C24, a capacitor twenty-five C25, a resistor forty-six R46, a resistor forty-seventeen R47, a resistor forty-eight R48, a capacitor twenty-nine C29, a resistor forty-nine R49, a capacitor twenty-seven C27, a capacitor twenty-eight C28 and an amplifier eleven U10A; pin 3 of the amplifier nine U9A is connected with the output signal of the Friege wave trap of the later stage; pin 1 of the amplifier nine U9A is connected with pin 2 of the amplifier nine U9A and one end of a resistor forty-four R44, pin 4 is connected with a-6V power supply, and pin 8 is connected with a +6V power supply; the other end of the resistor forty-four R44 is connected with one end of a capacitor twenty-four C24, a capacitor twenty-five C25 and a resistor forty-five R45, the other end of the resistor forty-five R45 is connected with a pin 5 of the amplifier ten U9B and one end of a capacitor twenty-six C26, and the other end of the capacitor twenty-six C26 is grounded; a pin 6 of the amplifier deca U9B is connected with one end of a resistor forty-six R46, and a pin 7 of the amplifier deca U9B is connected with one end of a resistor forty-seven R47, the other end of a capacitor twenty-four C24, the other end of a capacitor twenty-five C25 and the other end of a resistor forty-six R46;

pins

4 and 8 of amplifier tauu 9B are both floating; the nine U9A and ten U9B amplifiers are integrated amplifiers with model OP 2177; the other end of the resistor forty-seven R47 is connected with one end of a capacitor twenty-seven C27, a capacitor twenty-eight C28 and a resistor forty-eight R48, the other end of the resistor forty-eight R48 is connected with a pin 3 of an amplifier eleven U10A and one end of a capacitor twenty-nine C29, and the other end of the capacitor twenty-nine C29 is grounded; pin 2 of the amplifier eleven U10A is connected with one end of a resistor forty-nine R49; pin 1 of the amplifier eleven U10A is connected with the other ends of the capacitor twenty-seven C27, the capacitor twenty-eight C28 and the resistor forty-nine R49, and outputs a Signal 6; pin 4 of the amplifier eleven U10A is connected with a-6V power supply, and pin 8 is connected with a +6V power supply; the amplifier eleven U10A is model OP 2177.

The rear-stage amplification and single-end-to-differential conversion circuit comprises a resistor fifty R50, a resistor fifty-one R51, an amplification control chip four U11, a resistor fifty-three R53, a resistor fifty-six R56, a resistor fifty-seven R57, a resistor fifty-two R52, a resistor fifty-five R55, an amplifier twelve U12A, an amplifier thirteen U12B, a resistor fifty-four R54, a resistor fifty-eight R58, a capacitor thirty-C30 and a capacitor thirty-one C31; the amplification control chip IV U11 adopts a chip with the model number INA 118U; pin 1 of the amplification control chip four U11 is connected with one end of a resistor fifty R50, and the other end of the resistor fifty R50 is connected with pin 8 of the amplification control chip four U11; pin 2 of the amplification control chip four U11 is connected with one end of a resistor fifty-one R51, and the other end of the resistor fifty-one R51 is grounded; a pin 3 of the amplification control chip four U11 is connected with an output signal of a post-stage voltage following and low-pass filter, a pin 4 is connected with a-6V power supply, a pin 7 is connected with a +6V power supply, a pin 5 is connected with one end of a resistor fifty-seven R57 and connected with a reference voltage +2.5VREF, and a pin 6 is connected with one ends of a resistor fifty-three R53 and a resistor fifty-six R56; the other end of the resistor fifty-three R53 is connected with pin 3 of the amplifier twelve U12A; pin 2 of the amplifier twelve U12A is connected with one end of a resistor fifty-two R52, and pin 1 is connected with the other end of the resistor fifty-two R52 and one end of a resistor fifty-four R54; pin 4 of the amplifier twelve U12A is grounded, and pin 8 is connected with a +6V power supply; the other end of the resistor fifty-four R54 is connected with one end of the capacitor thirty-C30 and outputs a signal CH1 +; pin 6 of the amplifier thirteen U12B is connected with the other end of the resistor fifty-six R56 and one end of the resistor fifty-five R55, pin 5 is connected with the other end of the resistor fifty-seven R57, and pin 7 is connected with the other end of the resistor fifty-five R55 and one end of the resistor fifty-eight R58; pin 4 and pin 8 of amplifier thirteen U12B are both floating; the amplifier twelve U12A and the amplifier thirteen U12B adopt an integrated amplifier with model number OP296 GS; the other end of the resistor fifty-eight R58 is connected with one end of the capacitor thirty-one C31 and outputs a signal CH 1-; the other ends of the thirty-one C31 and thirty-C30 capacitors are both grounded.

The invention discloses an electrode embedding method of a ground electric field sensor system, which comprises the following steps:

drilling a well, wherein the depth of the well is more than 3m, and the inner diameter of the well is 136 mm;

step two, the north-south orientation electrode, the east-west orientation electrode and the public electrode are firmly tied by a rope respectively and then are placed at the bottom of a well hole respectively; the public electrode, the south-north orientation electrode, the east-west orientation electrode and the connecting line of the preceding stage signal conditioning circuit are positioned in the underground part and are all arranged in the sleeve, and the preceding stage signal conditioning circuit is arranged above the well hole for placing the public electrode; the top of each well hole is provided with a detection hole; the connecting wire adopts a whole multi-strand copper core insulated wire or a single connecting wire is not long enough, a plurality of connecting wires are welded through a joint, and the joint is buried in a detection hole formed in a welding position after insulation and anticorrosion treatment are carried out; the end of the connecting line of the south-north orientation electrode or the east-west orientation electrode, which is connected with the preceding stage signal conditioning circuit, is provided with a section of detection hole positioned outside the well hole for placing the common electrode;

filling fine soil with the depth of more than 1m into each well hole, compacting, and filling the whole well hole with soil drilled by the well hole and compacting; and a cover plate is arranged at the top of each detection hole.

The invention has the following beneficial effects:

1. the front-stage circuit adopts a mixed instrument amplifier and has the advantages of high input impedance, low noise and low offset.

2. The split structure of the front stage and the rear stage effectively solves the signal attenuation of weak signals in the transmission process.

3. The post-stage circuit adopts a flexible zero setting mode.

4. The differential signal transmission of the front stage and the rear stage effectively reduces common-mode interference.

5. The burying mode of the ground electric field electrode and the erecting mode of the ground electric field external line ensure that the electrode can be in good contact with a soil medium, the long-term stability of the work of the electrode is enhanced, the observation quality of the ground electric field is effectively improved, and the electric field interference of the surrounding environment is effectively shielded.

Drawings

FIG. 1 is a block diagram of a ground electric field sensor system according to the present invention;

FIG. 2 is a block diagram of a preceding stage signal conditioning circuit according to the present invention;

FIG. 3 is a circuit diagram of a preceding passive band pass filter and a preceding hybrid instrumentation amplifier in accordance with the present invention;

FIG. 4 is a circuit diagram of a preceding active band pass filter according to the present invention;

FIG. 5 is a circuit diagram of a preceding stage single-ended to differential circuit of the present invention;

FIG. 6 is a block diagram of a post-stage signal conditioning circuit according to the present invention;

FIG. 7 is a circuit diagram of a post-stage passive band-pass filter, a post-stage instrumentation amplifier, and a zeroing circuit of the present invention;

FIG. 8 is a schematic diagram of a serial communication interface of the controller and the zeroing circuit according to the present invention;

FIG. 9 is a circuit diagram of a later stage Fliege trap of the present invention;

FIG. 10 is a circuit diagram of a post-stage voltage follower and low pass filter of the present invention;

FIG. 11 is a circuit diagram of a post-amplification and single-to-differential conversion circuit according to the present invention;

FIG. 12 is a schematic view showing the burying of the electrodes in the present invention.

Detailed Description

The invention will be further explained with reference to the drawings.

As shown in fig. 1, 2 and 6, the electric field sensor system comprises a front stage signal conditioning circuit 1 and a rear stage signal conditioning circuit 2; the front stage signal conditioning circuit is placed in a front-end observation field, and the rear stage signal conditioning circuit is placed in an observation room; the preceding-stage signal conditioning circuit 1 comprises a preceding-stage passive band-pass filter 1-1, a preceding-stage hybrid instrument amplifier 1-2, a preceding-stage active band-pass filter 1-3 and a preceding-stage single-end-to-differential circuit 1-4; the public electrode O and the south-north direction electrode SN are connected into a preceding stage passive band-pass filter of a preceding stage signal conditioning circuit, and the public electrode O and the south-north direction electrode SN are connected into a preceding stage passive band-pass filter of another preceding stage signal conditioning circuit; after ground electric field signals Q detected by the north-south orientation electrode SN and the common electrode O or the east-west orientation electrode EW and the common electrode O are transmitted into a front-stage signal conditioning circuit, differential signals are output to a corresponding rear-stage signal conditioning circuit after being filtered by a front-stage passive band-pass filter, amplified by a front-stage hybrid instrument amplifier, filtered by a front-stage active band-pass filter and signal conditioned by a front-stage single-end differential circuit in the front-stage signal conditioning circuit; the post-stage signal conditioning circuit 2 comprises a post-stage passive band-pass filter 2-1, a post-stage instrument amplifier 2-2, a zero-setting circuit 2-3, a post-stage Fliege wave trap 2-4, a post-stage voltage following and low-pass filter 2-5, a post-stage amplifying and single-end to differential circuit 2-6, an A/D converter 2-7 and a controller 2-8; after a signal output by the front-stage signal conditioning circuit is filtered by a rear-stage passive band-pass filter, amplified by a rear-stage instrument amplifier, filtered by a rear-stage Fliege trap filter, followed and filtered by a rear-stage voltage follower and low-pass filter, amplified by the rear stage and signal-to-differential circuit signal-conditioned by a single-end conversion circuit in sequence, a differential signal is output to an A/D converter, and the A/D converter performs analog-to-digital conversion and then transmits the differential signal to a controller; the controller calculates a zero-setting voltage value, a D/A converter in the zero-setting circuit 2-3 generates a zero-setting voltage through a control signal, and the zero-setting voltage is output to a voltage reference pin of a rear-stage instrumentation amplifier after passing through a rear-stage voltage follower in the zero-setting circuit, so that zero setting of the rear-stage instrumentation amplifier is realized; the A/D converter 2-7 adopts a chip with the model number of ADS 1254E; the controller adopts a chip with model number SAF-C167 CS-L16M.

As shown in fig. 3, the preceding passive band-pass filter includes a resistor two R2, a resistor three R3, a resistor five R5, a capacitor two C2, a capacitor three C3, a capacitor five C5, a diode one D1, a resistor six R6, a diode two D2, a capacitor eight C8, a capacitor six C6, a common mode choke one T1, a capacitor twelve C12, a resistor thirteen R13, a resistor fifteen R15, a resistor seventeen R17, a capacitor thirteen C13, a capacitor ten C10, a diode three D3, a resistor fourteen R14, a diode four D4, a capacitor fifteen C15, and a capacitor fourteen C14; the common electrode O is connected with the input end E1-of the first coil in the first common mode choke coil T1, and the south-north orientation electrode SN or the east-west orientation electrode EW is connected with the input end E1+ of the second coil in the first common mode choke coil T1; one end of the capacitor twelve C12 is connected with the output end of the coil I in the common mode choke I T1, and one end of the capacitor three C3 is connected with the output end of the coil II in the common mode choke I T1; one end of the second resistor R2 is connected with one end of the third resistor R3, and the other end of the second resistor R2 is grounded; the other end of the resistor three R3 is connected with one end of a resistor five R5 and the other end of the capacitor three C3; the other end of the resistor five R5 is connected with one end of the capacitor five C5, the cathode of the diode one D1, one end of the resistor six R6 and the cathode of the diode two D2; the other end of the capacitor five C5 is grounded; the anode of the diode I D1 is connected with one end of the capacitor II C2, and the other end of the capacitor II C2 is grounded; the anode of the diode II D2 is connected with one end of the capacitor eight C8, and the other end of the capacitor eight C8 is grounded; the other end of the resistor six R6 is connected with one end of the capacitor six C6 and outputs a Signal +; the other end of the capacitor six C6 is grounded; one end of the resistor seventeen R17 is grounded, and the other end of the resistor seventeen R17 is connected with one end of the resistor fifteen R15; the other end of the resistor fifteen R15 is connected with one end of a resistor thirteen R13 and the other end of the capacitor twelve C12; the other end of the resistor thirteen R13 is connected with one end of a capacitor thirteen C13, the cathode of a diode three D3, one end of a resistor fourteen R14 and the cathode of a diode four D4; the other end of the capacitor thirteen C13 is grounded; the anode of the diode three D3 is connected with one end of the capacitor ten C10, and the other end of the capacitor ten C10 is grounded; the other end of the resistor fourteen R14 is connected with one end of the capacitor fourteen C14 and outputs a Signal-; the other end of the capacitor fourteen C14 is grounded; the anode of the diode quad D4 is connected to one end of the capacitor fifteen C15, and the other end of the capacitor fifteen C15 is grounded.

The pre-stage hybrid instrumentation amplifier comprises an amplifier I U1, a capacitor I C1, a resistor I R1, a resistor seven R7, a resistor twenty I R21, a capacitor sixteen C16, an amplifier four U4, a resistor four R4, a resistor sixteen R16, a resistor twenty five R25 and an amplification control chip I2; the models of the first amplifier U1 and the fourth amplifier U4 are AD 745-745 JR-16; pin 3 of the first amplifier U1 is connected with one end of a first capacitor C1, a first resistor R1 and a seventh resistor R7; one end of the resistor IV R4 is connected with pin 3 of the amplification control chip I U2, and the type of the amplification control chip I U2 is INA 128U; a pin 12 of the first amplifier U1 is connected with the other ends of the first capacitor C1, the first resistor R1 and the fourth resistor R4; pin 6 of the first amplifier U1 is connected with a-6V power supply, and pin 13 of the first amplifier U1 is connected with a +6V power supply; the other end of the resistor seven R7 is connected with a pin 3 of an amplifier four U4, one end of a resistor twenty-one R21 and one end of a capacitor sixteen C16; the other end of the resistor twenty-one R21 is connected with the other end of the capacitor sixteen C16, the pin 12 of the amplifier four U4 and one end of the resistor sixteen R16; pin 13 of the amplifier quad U4 is connected with a +6V power supply, and pin 6 of the amplifier quad U4 is connected with a-6V power supply; the other end of the resistor sixteen R16 is connected with a pin 2 of a first amplification control chip U2; one end of the resistor twenty-five R25 is connected with the pin 8 of the first amplification control chip U2, and the other end of the resistor twenty-five R25 is connected with the pin 1 of the first amplification control chip U2; the pin 5 of the first amplification control chip U2 is grounded, the pin 7 is connected with a +6V power supply, the pin 4 is connected with a-6V power supply, and the pin 6 outputs a Signal 1. And pins 5 of the first amplifier U1 and the fourth amplifier U4 are respectively connected with an output Signal + and an output Signal-of the preceding passive band-pass filter.

As shown in fig. 4, the pre-stage active band-pass filter includes a capacitor nine C9, a resistor ten R10, a resistor twelve R12, a resistor eight R8, a resistor nine R9, a capacitor four C4, a capacitor seven C7, a capacitor eleven C11, an amplifier three U3A, and a resistor eleven R11; amplifier three U3A model No. OP 2177; one end of the capacitor nine C9 is connected with an output Signal1 of the pre-stage hybrid instrumentation amplifier, and the other end of the capacitor nine C9 is connected with one end of the resistor decaR 10 and one end of the resistor eight R8; the other end of the resistor eight R8 is connected with one end of a resistor nine R9, a capacitor four C4 and a capacitor seven C7; the other end of the resistor decar 10 is connected with one end of a resistor twelve R12; the other end of R12 is grounded; the other end of the resistor nine R9 is connected with one end of the capacitor eleven C11 and a pin 3 of the amplifier three U3A; the other end of the capacitor eleven C11 is grounded; pin 1 of the amplifier three U3A is connected with one end of a resistor eleven R11, the other end of a capacitor four C4 and the other end of a capacitor seven C7, and outputs a Signal 2; pin 2 of the amplifier three U3A is connected with the other end of the resistor eleven R11; pin 4 of the amplifier three U3A is connected with a-6V power supply, and pin 8 is connected with a +6V power supply.

As shown in fig. 5, the preceding-stage single-ended-to-differential conversion circuit includes a resistor twenty R20, a resistor eighteen R18, an amplifier five U5A, an amplifier six U5B, a resistor nineteen R19, a resistor twenty-three R23, a resistor twenty-six R26, a resistor twenty-two R22, and a resistor twenty-four R24; one end of the resistor twenty R20 is connected with one end of the resistor twenty-three R23 and is connected with the output Signal2 of the front-stage active band-pass filter in parallel; the other end of the resistor twenty R20 is connected with a pin 3 of the amplifier five U5A, a pin 2 of the amplifier five U5A is connected with one end of a resistor eighteen R18, and the other end of the resistor eighteen R18 is connected with a pin 1 of the amplifier five U5A and one end of a resistor nineteen R19; the other end of the resistor nineteen R19 outputs a Signal3 +; pin 8 of the amplifier five U5A is connected with a +6V power supply, and pin 4 is connected with a-6V power supply; the other end of the resistor twenty-three R23 is connected with one end of a resistor twenty-two R22 and a pin 6 of an amplifier six U5B, a pin 5 of the amplifier six U5B is connected with one end of a resistor twenty-six R26, and the other end of the resistor twenty-six R26 is grounded; a pin 7 of the amplifier six U5B is connected with the other end of the resistor twenty-two R22 and one end of the resistor twenty-four R24, and the other end of the resistor twenty-four R24 outputs a Signal 3-; pin 4 and pin 8 of amplifier six U5B are both floating; amplifier five U5A and amplifier six U5B employ an integrated amplifier model AD822 AR.

As shown in fig. 7, the post-stage passive band-pass filter includes a resistor twenty-seven R27, a common mode choke coil two T2, a resistor twenty-nine R29, a resistor thirty R30, a resistor twenty-eight R28, a capacitor seventeen C17, a capacitor eighteen C18, and a capacitor nineteen C19; the input end of the first coil in the second common mode choke T2 is connected with the output Signal 3' of the previous stage Signal conditioning circuit, and the input end of the second coil in the second common mode choke T2 is connected with the output Signal3+ of the previous stage Signal conditioning circuit; one end of the resistor twenty-seven R27 is grounded, and the other end of the resistor twenty-seven R27 is connected with one end of the resistor twenty-nine R29 and the output end of the second coil in the common mode choke coil II T2; the other end of the resistor twenty-nine R29 is connected with one end of a capacitor seventeen C17 and one end of a capacitor eighteen C18, and the other end of the capacitor seventeen C17 is grounded; one end of the resistor twenty-eight R28 is grounded, and the other end of the resistor twenty-eight R28 is connected with one end of the resistor thirty-R30 and the output end of the first coil in the common mode choke II T2; the other end of the resistor thirty R30 is connected with the other end of the capacitor eighteen C18 and one end of the capacitor nineteen C19, and the other end of the capacitor nineteen C19 is grounded.

The rear-stage instrument amplifier comprises a resistor thirty-one R31 and an amplification control chip II U6; the second amplification control chip U6 adopts a chip with the model number INA 128U; pin 1 of the second amplification control chip U6 is connected with one end of a resistor thirty-one R31, and pin 8 of the second amplification control chip U6 is connected with the other end of the resistor thirty-one R31; pin 4 of the second amplification control chip U6 is connected with a-6V power supply, and pin 7 of the second amplification control chip U6 is connected with a +6V power supply; pin 2 of the amplification control chip II U6 is connected with the connecting end of a capacitor seventeen C17 and a capacitor eighteen C18; a pin 3 of the amplification control chip II U6 is connected with the connecting end of a capacitor eighteen C18 and a capacitor nineteen C19; and the pin 6 of the second amplification control chip U6 outputs a Signal 4.

As shown in fig. 7 and 8, the zeroing circuit includes a D/a converter and a post-stage voltage follower; the D/A converter comprises an amplification control chip three U7, a resistor thirty-two R32 and a resistor thirty-three R33; the post-stage voltage follower comprises a resistor thirty-four R34, a resistor thirty-five R35 and an amplifier two U10B; the amplification control chip three U7 adopts a chip with the model number of AD5312 ARMZ; the model of the amplifier II U10B is OP 2177; pin 2 of the amplification control chip three U7 is connected with a +6V power supply, pin 1 and pin 10 are both grounded, pin 5 is connected with one end of a resistor thirty-two R32, and pin 6 is connected with one end of a resistor thirty-three R33;

pins

As shown in fig. 9, the succeeding stage Fliege trap includes a capacitor twenty C20, a capacitor twenty-one C21, a resistor thirty-six R36, a sliding varistor one R39, a sliding varistor two R37, a resistor thirty-eight R38, a resistor forty R40, a capacitor twenty-two C22, a capacitor twenty-three C23, an amplifier seven U8A, an amplifier eight U8B, a resistor forty-one R41, a resistor forty-two R42, and a resistor forty-three R43; one end of each of the capacitor twenty C20, the capacitor twenty-one C21, the resistor thirty-six R36 and the resistor forty-three R43 is connected with an output Signal4 of a rear-stage instrument amplifier; the other end of the capacitor twenty C20 is connected with the movable end of the second slide rheostat R37, the other end of the capacitor twenty-one C21, one fixed end of the first slide rheostat R39, the movable end of the first slide rheostat R39 and the pin 3 of the seven U8A amplifier; the other end of the resistor thirty-six R36 is connected with one fixed end of the second sliding rheostat R37; the other fixed end of the sliding rheostat II R37 is connected with one end of a resistor thirty-eight R38, and the other end of the resistor thirty-eight R38 is grounded; the other fixed end of the slide rheostat R39 is connected with one end of a resistor forty R40, and the other end of the resistor forty R40 is connected with one ends of a pin 7 of an amplifier eight U8B, a capacitor twenty-two C22 and a capacitor twenty-three C23; pin 6 of the amplifier eight U8B is connected with pin 2 of the amplifier seven U8A, one end of a resistor forty-one R41, the other end of a capacitor twenty-two C22 and the other end of a capacitor twenty-three C23; pin 5 of the amplifier eight U8B is connected with one end of a resistor forty-two R42 and the other end of a resistor forty-three R43; pin 4 of the seven U8A amplifier is connected with a-6V power supply, and pin 8 is connected with a +6V power supply; pin 4 and pin 8 of the amplifier eight U8B are both floating; pin 1 of the amplifier seven U8A is connected with the other ends of the resistor forty-two R42 and the resistor forty-one R41, and outputs a Signal 5; the seven U8A and eight U8B amplifiers use integrated amplifiers of model AD822 AR.

As shown in fig. 10, the post-stage voltage follower and low-pass filter includes an amplifier nine U9A, a resistor forty-four R44, a resistor forty-five R45, a capacitor twenty-six C26, an amplifier ten U9B, a capacitor twenty-four C24, a capacitor twenty-five C25, a resistor forty-six R46, a resistor forty-seventeen R47, a resistor forty-eight R48, a capacitor twenty-nine C29, a resistor forty-nine R49, a capacitor twenty-seven C27, a capacitor twenty-eight C28, and an amplifier eleven U10A; pin 3 of the amplifier nine U9A is connected with an output Signal5 of a Friege trap at the later stage; pin 1 of the amplifier nine U9A is connected with pin 2 of the amplifier nine U9A and one end of a resistor forty-four R44, pin 4 is connected with a-6V power supply, and pin 8 is connected with a +6V power supply; the other end of the resistor forty-four R44 is connected with one end of a capacitor twenty-four C24, a capacitor twenty-five C25 and a resistor forty-five R45, the other end of the resistor forty-five R45 is connected with a pin 5 of the amplifier ten U9B and one end of a capacitor twenty-six C26, and the other end of the capacitor twenty-six C26 is grounded; a pin 6 of the amplifier deca U9B is connected with one end of a resistor forty-six R46, and a pin 7 of the amplifier deca U9B is connected with one end of a resistor forty-seven R47, the other end of a capacitor twenty-four C24, the other end of a capacitor twenty-five C25 and the other end of a resistor forty-six R46;

pins

As shown in fig. 11, the rear-stage amplifying and single-end-to-differential circuit includes a resistor fifty R50, a resistor fifty-one R51, an amplifying control chip four U11, a resistor fifty-three R53, a resistor fifty-six R56, a resistor fifty-seven R57, a resistor fifty-two R52, a resistor fifty-five R55, an amplifier twelve U12A, an amplifier thirteen U12B, a resistor fifty-four R54, a resistor fifty-eight R58, a capacitor thirty-C30, and a capacitor thirty-one-C31; the amplification control chip IV U11 adopts a chip with the model number INA 118U; pin 1 of the amplification control chip four U11 is connected with one end of a resistor fifty R50, and the other end of the resistor fifty R50 is connected with pin 8 of the amplification control chip four U11; pin 2 of the amplification control chip four U11 is connected with one end of a resistor fifty-one R51, and the other end of the resistor fifty-one R51 is grounded; pin 3 of the amplification control chip four U11 is connected with an output Signal6 of a post-stage voltage following and low-pass filter, pin 4 is connected with a-6V power supply, pin 7 is connected with a +6V power supply, pin 5 is connected with one end of a resistor fifty-seven R57 and is connected with a reference voltage +2.5VREF, and pin 6 is connected with one ends of a resistor fifty-three R53 and a resistor fifty-six R56; the other end of the resistor fifty-three R53 is connected with pin 3 of the amplifier twelve U12A; pin 2 of the amplifier twelve U12A is connected with one end of a resistor fifty-two R52, and pin 1 is connected with the other end of the resistor fifty-two R52 and one end of a resistor fifty-four R54; pin 4 of the amplifier twelve U12A is grounded, and pin 8 is connected with a +6V power supply; the other end of the resistor fifty-four R54 is connected with one end of the capacitor thirty-C30 and outputs a signal CH1 +; pin 6 of the amplifier thirteen U12B is connected with the other end of the resistor fifty-six R56 and one end of the resistor fifty-five R55, pin 5 is connected with the other end of the resistor fifty-seven R57, and pin 7 is connected with the other end of the resistor fifty-five R55 and one end of the resistor fifty-eight R58; pin 4 and pin 8 of amplifier thirteen U12B are both floating; the amplifier twelve U12A and the amplifier thirteen U12B adopt an integrated amplifier with model number OP296 GS; the other end of the resistor fifty-eight R58 is connected with one end of the capacitor thirty-one C31 and outputs a signal CH 1-; the other ends of the thirty-one C31 and thirty-C30 capacitors are both grounded.

For geoelectric field observation application requirements: 1. the earth electric field observation source impedance is large; 2. the voltage source of the sensor has a large variation range (10uV-1mV), and if strong external interference exists, the variation range can reach hundreds of mV, so the front end is not suitable for being amplified by too high. The measuring electrodes (the north-south orientation electrode SN, the public electrode O and the east-west orientation electrode EW) of the invention adopt Pb-PbCl₂A solid non-polarizing electrode; the preceding-stage signal conditioning circuit is used for conditioning signals aiming at the characteristics of weak ground electric field signals and high impedance, and is favorable for long-distance transmission of the signals. The front-stage signal conditioning circuit adopts a front-stage mixed instrument amplifier comprising 2 AD745JR-16 amplifiers and an INA128U instrument amplifier, has the characteristics of low noise, low drift, low offset and high speed, and is an ideal choice for a ground electric field sensor system because the JFET input bias current of the AD745JR-16 is extremely low for a ground electric observation high-impedance signal source. The post-stage signal conditioning circuit further processes the signal transmitted by the pre-stage signal conditioning circuit, and is suitable for data acquisition of an A/D chip.

As shown in fig. 12, in order to ensure good contact between the electrode and the soil medium and enhance the long-term stability of the electrode operation, after fully considering the environmental conditions such as topography, lithological conditions, interference sources and the like of the electrode embedding point, the invention optimizes the electrode embedding method, specifically as follows:

step one, drilling a well hole, wherein the depth of the well hole is more than 3m, and the inner diameter of the well hole is 136 mm.

Step two, the north-south orientation electrode SN, the east-west orientation electrode EW and the public electrode O are fastened by ropes respectively and then are placed at the bottom of a well hole respectively; in order to reduce the interference of the environment and ensure the connection reliability and the ground insulation of the circuit, the public electrode O, the north-south orientation electrode SN, the east-west orientation electrode EW and the connecting line of the preceding stage signal conditioning circuit are all arranged in the sleeve pipe at the underground part, and the preceding stage signal conditioning circuit is arranged above the well hole for arranging the public electrode O; the top of each well hole is provided with a detection hole; the connecting wire is a whole multi-strand copper core insulated wire; if the single connecting wire is not long enough, a plurality of connecting wires can be welded through the joint, and the joint is buried in a detection hole formed in the welding position after insulation and corrosion prevention treatment are well performed. The end of the connecting line of the south-north orientation electrode SN or the east-west orientation electrode EW connected with the preceding stage signal conditioning circuit is provided with a section of detection hole positioned outside the well hole for placing the common electrode O.

Filling clean fine soil with the depth of more than 1m into each well hole, compacting, and filling the whole well hole with soil drilled by the well hole and compacting; and a cover plate is arranged at the top of each detection hole.

Claims

1. A kind of electric field sensor system of ground, including preceding stage signal conditioning circuit and back stage signal conditioning circuit; the front stage signal conditioning circuit is placed in a front-end observation field, and the rear stage signal conditioning circuit is placed in an observation room; the method is characterized in that: the preceding-stage signal conditioning circuit comprises a preceding-stage passive band-pass filter, a preceding-stage hybrid instrument amplifier, a preceding-stage active band-pass filter and a preceding-stage single-end-to-differential circuit; the public electrode and the south-north direction electrode are connected into a preceding passive band-pass filter of a preceding signal conditioning circuit, and are connected into a preceding passive band-pass filter of another preceding signal conditioning circuit together with the east-west direction electrode; after ground electric field signals detected by the south-north orientation electrode and the common electrode or the east-west orientation electrode and the common electrode are transmitted into the front-stage signal conditioning circuit, differential signals are output to a corresponding rear-stage signal conditioning circuit after being filtered by a front-stage passive band-pass filter, amplified by a front-stage hybrid instrument amplifier, filtered by a front-stage active band-pass filter and signal conditioning by a front-stage single-end to differential circuit in sequence in the front-stage signal conditioning circuit; the post-stage signal conditioning circuit comprises a post-stage passive band-pass filter, a post-stage instrument amplifier, a zero setting circuit, a post-stage Fliege wave trap, a post-stage voltage following and low-pass filter, a post-stage amplifying and single-end-to-differential circuit, an A/D converter and a controller; after a signal output by the front-stage signal conditioning circuit is filtered by a rear-stage passive band-pass filter, amplified by a rear-stage instrument amplifier, filtered by a rear-stage Fliege trap filter, followed and filtered by a rear-stage voltage follower and low-pass filter, amplified by the rear stage and signal-to-differential circuit signal-conditioned by a single-end conversion circuit in sequence, a differential signal is output to an A/D converter, and the A/D converter performs analog-to-digital conversion and then transmits the differential signal to a controller; the controller calculates a zero-setting voltage value, a D/A converter in the zero-setting circuit generates a zero-setting voltage through a control signal, and the zero-setting voltage is output to a voltage reference pin of a rear-stage instrumentation amplifier after passing through a rear-stage voltage follower in the zero-setting circuit, so that zero setting of the rear-stage instrumentation amplifier is realized;

the pre-stage hybrid instrumentation amplifier comprises an amplifier I1, a capacitor I C1, a resistor I R1, a resistor seven R7, a resistor twenty I R21, a capacitor sixteen C16, an amplifier four U4, a resistor four R4, a resistor sixteen R16, a resistor twenty five R25 and an amplification control chip I2; the models of the first amplifier U1 and the fourth amplifier U4 are AD 745-745 JR-16; pin 3 of the first amplifier U1 is connected with one end of a first capacitor C1, a first resistor R1 and a seventh resistor R7; one end of the resistor IV R4 is connected with pin 3 of the amplification control chip I U2, and the type of the amplification control chip I U2 is INA 128U; a pin 12 of the first amplifier U1 is connected with the other ends of the first capacitor C1, the first resistor R1 and the fourth resistor R4; pin 6 of the first amplifier U1 is connected with a-6V power supply, and pin 13 of the first amplifier U1 is connected with a +6V power supply; the other end of the resistor seven R7 is connected with a pin 3 of an amplifier four U4, one end of a resistor twenty-one R21 and one end of a capacitor sixteen C16; the other end of the resistor twenty-one R21 is connected with the other end of the capacitor sixteen C16, the pin 12 of the amplifier four U4 and one end of the resistor sixteen R16; pin 13 of the amplifier quad U4 is connected with a +6V power supply, and pin 6 of the amplifier quad U4 is connected with a-6V power supply; the other end of the resistor sixteen R16 is connected with a pin 2 of a first amplification control chip U2; one end of the resistor twenty-five R25 is connected with the pin 8 of the first amplification control chip U2, and the other end of the resistor twenty-five R25 is connected with the pin 1 of the first amplification control chip U2; pin 5 of the first amplification control chip U2 is grounded, pin 7 is connected with a +6V power supply, pin 4 is connected with a-6V power supply, and pin 6 outputs a Signal 1; pins 5 of the first amplifier U1 and the fourth amplifier U4 are respectively connected with the positive electrode of an output signal and the negative electrode of an output signal of the preceding-stage passive band-pass filter;

the embedding process of the electrode is as follows:

2. An earth-electric field sensor system according to claim 1, wherein: the front-stage passive band-pass filter comprises a resistor II R2, a resistor III R3, a resistor V R5, a capacitor II C2, a capacitor III C3, a capacitor V C5, a diode I D1, a resistor VI R6, a diode II D2, a capacitor eight C8, a capacitor VI C6, a common-mode choke I T1, a capacitor twelve C12, a resistor thirteen R13, a resistor fifteen R15, a resistor seventeen R17, a capacitor thirteen C13, a capacitor ten C10, a diode III D3, a resistor fourteen R14, a diode four D4, a capacitor fifteen C15 and a capacitor fourteen C14; the common electrode is connected with the input end E1 of the first coil in the first common mode choke coil T1, and the south-north orientation electrode or the east-west orientation electrode is connected with the input end E1+ of the second coil in the first common mode choke coil T1; one end of the capacitor twelve C12 is connected with the output end of the coil I in the common mode choke I T1, and one end of the capacitor three C3 is connected with the output end of the coil II in the common mode choke I T1; one end of the second resistor R2 is connected with one end of the third resistor R3, and the other end of the second resistor R2 is grounded; the other end of the resistor three R3 is connected with one end of a resistor five R5 and the other end of the capacitor three C3; the other end of the resistor five R5 is connected with one end of the capacitor five C5, the cathode of the diode one D1, one end of the resistor six R6 and the cathode of the diode two D2; the other end of the capacitor five C5 is grounded; the anode of the diode I D1 is connected with one end of the capacitor II C2, and the other end of the capacitor II C2 is grounded; the anode of the diode II D2 is connected with one end of the capacitor eight C8, and the other end of the capacitor eight C8 is grounded; the other end of the resistor six R6 is connected with one end of the capacitor six C6 and outputs a Signal +; the other end of the capacitor six C6 is grounded; one end of the resistor seventeen R17 is grounded, and the other end of the resistor seventeen R17 is connected with one end of the resistor fifteen R15; the other end of the resistor fifteen R15 is connected with one end of a resistor thirteen R13 and the other end of the capacitor twelve C12; the other end of the resistor thirteen R13 is connected with one end of a capacitor thirteen C13, the cathode of a diode three D3, one end of a resistor fourteen R14 and the cathode of a diode four D4; the other end of the capacitor thirteen C13 is grounded; the anode of the diode three D3 is connected with one end of the capacitor ten C10, and the other end of the capacitor ten C10 is grounded; the other end of the resistor fourteen R14 is connected with one end of the capacitor fourteen C14 and outputs a Signal-; the other end of the capacitor fourteen C14 is grounded; the anode of the diode quad D4 is connected to one end of the capacitor fifteen C15, and the other end of the capacitor fifteen C15 is grounded.

3. An earth-electric field sensor system according to claim 1, wherein: the front-stage active band-pass filter comprises a capacitor nine C9, a resistor ten R10, a resistor twelve R12, a resistor eight R8, a resistor nine R9, a capacitor four C4, a capacitor seven C7, a capacitor eleven C11, an amplifier three U3A and a resistor eleven R11; amplifier three U3A model No. OP 2177; one end of the capacitor nine C9 is connected with the output signal of the pre-stage hybrid instrument amplifier, and the other end is connected with one ends of the resistor ten R10 and the resistor eight R8; the other end of the resistor eight R8 is connected with one end of a resistor nine R9, a capacitor four C4 and a capacitor seven C7; the other end of the resistor decar 10 is connected with one end of a resistor twelve R12; the other end of R12 is grounded; the other end of the resistor nine R9 is connected with one end of the capacitor eleven C11 and a pin 3 of the amplifier three U3A; the other end of the capacitor eleven C11 is grounded; pin 1 of the amplifier three U3A is connected with one end of a resistor eleven R11, the other end of a capacitor four C4 and the other end of a capacitor seven C7, and outputs a Signal 2; pin 2 of the amplifier three U3A is connected with the other end of the resistor eleven R11; pin 4 of the amplifier three U3A is connected with a-6V power supply, and pin 8 is connected with a +6V power supply.

4. An earth-electric field sensor system according to claim 1, wherein: the front-stage single-ended to differential conversion circuit comprises a resistor twenty R20, a resistor eighteen R18, an amplifier five U5A, an amplifier six U5B, a resistor nineteen R19, a resistor twenty-three R23, a resistor twenty-six R26, a resistor twenty-two R22 and a resistor twenty-four R24; one end of the resistor twenty R20 is connected with one end of the resistor twenty-three R23 and is connected with an output signal of the front-stage active band-pass filter in parallel; the other end of the resistor twenty R20 is connected with a pin 3 of the amplifier five U5A, a pin 2 of the amplifier five U5A is connected with one end of a resistor eighteen R18, and the other end of the resistor eighteen R18 is connected with a pin 1 of the amplifier five U5A and one end of a resistor nineteen R19; the other end of the resistor nineteen R19 outputs a Signal3 +; pin 8 of the amplifier five U5A is connected with a +6V power supply, and pin 4 is connected with a-6V power supply; the other end of the resistor twenty-three R23 is connected with one end of a resistor twenty-two R22 and a pin 6 of an amplifier six U5B, a pin 5 of the amplifier six U5B is connected with one end of a resistor twenty-six R26, and the other end of the resistor twenty-six R26 is grounded; a pin 7 of the amplifier six U5B is connected with the other end of the resistor twenty-two R22 and one end of the resistor twenty-four R24, and the other end of the resistor twenty-four R24 outputs a Signal 3-; pin 4 and pin 8 of amplifier six U5B are both floating; amplifier five U5A and amplifier six U5B employ an integrated amplifier model AD822 AR.

5. An earth-electric field sensor system according to claim 1, wherein: the rear-stage passive band-pass filter comprises a resistor twenty-seven R27, a common-mode choke coil II T2, a resistor twenty-nine R29, a resistor thirty R30, a resistor twenty-eight R28, a capacitor seventeen C17, a capacitor eighteen C18 and a capacitor nineteen C19; the input end of the first coil in the second common mode choke coil T2 is connected with the negative electrode of the output signal of the preceding stage signal conditioning circuit, and the input end of the second coil in the second common mode choke coil T2 is connected with the positive electrode of the output signal of the preceding stage signal conditioning circuit; one end of the resistor twenty-seven R27 is grounded, and the other end of the resistor twenty-seven R27 is connected with one end of the resistor twenty-nine R29 and the output end of the second coil in the common mode choke coil II T2; the other end of the resistor twenty-nine R29 is connected with one end of a capacitor seventeen C17 and one end of a capacitor eighteen C18, and the other end of the capacitor seventeen C17 is grounded; one end of the resistor twenty-eight R28 is grounded, and the other end of the resistor twenty-eight R28 is connected with one end of the resistor thirty-R30 and the output end of the first coil in the common mode choke II T2; the other end of the resistor thirty R30 is connected with the other end of the capacitor eighteen C18 and one end of the capacitor nineteen C19, and the other end of the capacitor nineteen C19 is grounded; the rear-stage instrument amplifier comprises a resistor thirty-one R31 and an amplification control chip II U6; the second amplification control chip U6 adopts a chip with the model number INA 128U; pin 1 of the second amplification control chip U6 is connected with one end of a resistor thirty-one R31, and pin 8 of the second amplification control chip U6 is connected with the other end of the resistor thirty-one R31; pin 4 of the second amplification control chip U6 is connected with a-6V power supply, and pin 7 of the second amplification control chip U6 is connected with a +6V power supply; pin 2 of the amplification control chip II U6 is connected with the connecting end of a capacitor seventeen C17 and a capacitor eighteen C18; a pin 3 of the amplification control chip II U6 is connected with the connecting end of a capacitor eighteen C18 and a capacitor nineteen C19; the pin 6 of the second amplification control chip U6 outputs a Signal 4; the zero setting circuit comprises a zero setting circuit and a zero setting circuit, wherein the zero setting circuit comprises a D/A converter and a post-stage voltage follower; the D/A converter comprises an amplification control chip three U7, a resistor thirty-two R32 and a resistor thirty-three R33; the post-stage voltage follower comprises a resistor thirty-four R34, a resistor thirty-five R35 and an amplifier two U10B; the amplification control chip three U7 adopts a chip with the model number of AD5312 ARMZ; the controller adopts a chip with the model number of SAF-C167 CS-L16M; the model of the amplifier II U10B is OP 2177; pin 2 of the amplification control chip three U7 is connected with a +6V power supply, pin 1 and pin 10 are both grounded, pin 5 is connected with one end of a resistor thirty-two R32, and pin 6 is connected with one end of a resistor thirty-three R33; pins 3 and 4 of the amplification control chip three U7 are both connected with the reference voltage +2.5 VREF; a pin P3.3 of the controller is connected with a pin 7 of the three amplification control chips U7, a pin TXD of the controller is connected with a pin 8 of the three amplification control chips U7, and a pin RXD of the controller is connected with a pin 9 of the three amplification control chips U7; when the pin P3.3 of the controller is set to be low, the communication between the controller and the three U7 of the amplification control chip is started; the other end of the resistor thirty-two R32 is connected with the other end of the resistor thirty-three R33, one end of the resistor thirty-four R34, one end of the resistor thirty-five R35 and the pin 5 of the amplifier II U10B; the other end of the resistor thirty-four R34 is connected with reference voltage-2.5 VREF, and the other end of the resistor thirty-five R35 is grounded; pin 4 of the second amplifier U10B is connected with a-6V power supply, and pin 8 is connected with a +6V power supply; the pin 6 of the second amplifier U10B is connected with the pin 7 of the second amplifier U10B, and amplifies the pin 5 of the second control chip U6.

6. An earth-electric field sensor system according to claim 1, wherein: the later-stage Fliege wave trap comprises a capacitor twenty C20, a capacitor twenty-one C21, a resistor thirty-six R36, a slide rheostat one R39, a slide rheostat two R37, a resistor thirty-eight R38, a resistor forty R40, a capacitor twenty-two C22, a capacitor twenty-three C23, an amplifier seven U8A, an amplifier eight U8B, a resistor forty-one R41, a resistor forty-two R42 and a resistor forty-three R43; one end of a capacitor twenty C20, a capacitor twenty-one C21, a resistor thirty-six R36 and a resistor forty-three R43 are all connected with an output signal of a rear-stage instrument amplifier; the other end of the capacitor twenty C20 is connected with the movable end of the second slide rheostat R37, the other end of the capacitor twenty-one C21, one fixed end of the first slide rheostat R39, the movable end of the first slide rheostat R39 and the pin 3 of the seven U8A amplifier; the other end of the resistor thirty-six R36 is connected with one fixed end of the second sliding rheostat R37; the other fixed end of the sliding rheostat II R37 is connected with one end of a resistor thirty-eight R38, and the other end of the resistor thirty-eight R38 is grounded; the other fixed end of the slide rheostat R39 is connected with one end of a resistor forty R40, and the other end of the resistor forty R40 is connected with one ends of a pin 7 of an amplifier eight U8B, a capacitor twenty-two C22 and a capacitor twenty-three C23; pin 6 of the amplifier eight U8B is connected with pin 2 of the amplifier seven U8A, one end of a resistor forty-one R41, the other end of a capacitor twenty-two C22 and the other end of a capacitor twenty-three C23; pin 5 of the amplifier eight U8B is connected with one end of a resistor forty-two R42 and the other end of a resistor forty-three R43; pin 4 of the seven U8A amplifier is connected with a-6V power supply, and pin 8 is connected with a +6V power supply; pin 4 and pin 8 of the amplifier eight U8B are both floating; pin 1 of the amplifier seven U8A is connected with the other ends of the resistor forty-two R42 and the resistor forty-one R41, and outputs a Signal 5; the seven U8A and eight U8B amplifiers use integrated amplifiers of model AD822 AR.

7. An earth-electric field sensor system according to claim 1, wherein: the post-stage voltage following and low-pass filter comprises an amplifier nine U9A, a resistor forty-four R44, a resistor forty-five R45, a capacitor twenty-six C26, an amplifier ten U9B, a capacitor twenty-four C24, a capacitor twenty-five C25, a resistor forty-six R46, a resistor forty-seventeen R47, a resistor forty-eight R48, a capacitor twenty-nine C29, a resistor forty-nine R49, a capacitor twenty-seven C27, a capacitor twenty-eight C28 and an amplifier eleven U10A; pin 3 of the amplifier nine U9A is connected with the output signal of the Friege wave trap of the later stage; pin 1 of the amplifier nine U9A is connected with pin 2 of the amplifier nine U9A and one end of a resistor forty-four R44, pin 4 is connected with a-6V power supply, and pin 8 is connected with a +6V power supply; the other end of the resistor forty-four R44 is connected with one end of a capacitor twenty-four C24, a capacitor twenty-five C25 and a resistor forty-five R45, the other end of the resistor forty-five R45 is connected with a pin 5 of the amplifier ten U9B and one end of a capacitor twenty-six C26, and the other end of the capacitor twenty-six C26 is grounded; a pin 6 of the amplifier deca U9B is connected with one end of a resistor forty-six R46, and a pin 7 of the amplifier deca U9B is connected with one end of a resistor forty-seven R47, the other end of a capacitor twenty-four C24, the other end of a capacitor twenty-five C25 and the other end of a resistor forty-six R46; pins 4 and 8 of amplifier tauu 9B are both floating; the nine U9A and ten U9B amplifiers are integrated amplifiers with model OP 2177; the other end of the resistor forty-seven R47 is connected with one end of a capacitor twenty-seven C27, a capacitor twenty-eight C28 and a resistor forty-eight R48, the other end of the resistor forty-eight R48 is connected with a pin 3 of an amplifier eleven U10A and one end of a capacitor twenty-nine C29, and the other end of the capacitor twenty-nine C29 is grounded; pin 2 of the amplifier eleven U10A is connected with one end of a resistor forty-nine R49; pin 1 of the amplifier eleven U10A is connected with the other ends of the capacitor twenty-seven C27, the capacitor twenty-eight C28 and the resistor forty-nine R49, and outputs a Signal 6; pin 4 of the amplifier eleven U10A is connected with a-6V power supply, and pin 8 is connected with a +6V power supply; the amplifier eleven U10A is model OP 2177.

8. An earth-electric field sensor system according to claim 1, wherein: the rear-stage amplification and single-end-to-differential conversion circuit comprises a resistor fifty R50, a resistor fifty-one R51, an amplification control chip four U11, a resistor fifty-three R53, a resistor fifty-six R56, a resistor fifty-seven R57, a resistor fifty-two R52, a resistor fifty-five R55, an amplifier twelve U12A, an amplifier thirteen U12B, a resistor fifty-four R54, a resistor fifty-eight R58, a capacitor thirty-C30 and a capacitor thirty-one C31; the amplification control chip IV U11 adopts a chip with the model number INA 118U; pin 1 of the amplification control chip four U11 is connected with one end of a resistor fifty R50, and the other end of the resistor fifty R50 is connected with pin 8 of the amplification control chip four U11; pin 2 of the amplification control chip four U11 is connected with one end of a resistor fifty-one R51, and the other end of the resistor fifty-one R51 is grounded; a pin 3 of the amplification control chip four U11 is connected with an output signal of a post-stage voltage following and low-pass filter, a pin 4 is connected with a-6V power supply, a pin 7 is connected with a +6V power supply, a pin 5 is connected with one end of a resistor fifty-seven R57 and connected with a reference voltage +2.5VREF, and a pin 6 is connected with one ends of a resistor fifty-three R53 and a resistor fifty-six R56; the other end of the resistor fifty-three R53 is connected with pin 3 of the amplifier twelve U12A; pin 2 of the amplifier twelve U12A is connected with one end of a resistor fifty-two R52, and pin 1 is connected with the other end of the resistor fifty-two R52 and one end of a resistor fifty-four R54; pin 4 of the amplifier twelve U12A is grounded, and pin 8 is connected with a +6V power supply; the other end of the resistor fifty-four R54 is connected with one end of the capacitor thirty-C30 and outputs a signal CH1 +; pin 6 of the amplifier thirteen U12B is connected with the other end of the resistor fifty-six R56 and one end of the resistor fifty-five R55, pin 5 is connected with the other end of the resistor fifty-seven R57, and pin 7 is connected with the other end of the resistor fifty-five R55 and one end of the resistor fifty-eight R58; pin 4 and pin 8 of amplifier thirteen U12B are both floating; the amplifier twelve U12A and the amplifier thirteen U12B adopt an integrated amplifier with model number OP296 GS; the other end of the resistor fifty-eight R58 is connected with one end of the capacitor thirty-one C31 and outputs a signal CH 1-; the other ends of the thirty-one C31 and thirty-C30 capacitors are both grounded.