CN109471019B - Power chip low noise characteristic testing arrangement - Google Patents
Power chip low noise characteristic testing arrangement Download PDFInfo
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- CN109471019B CN109471019B CN201811535481.0A CN201811535481A CN109471019B CN 109471019 B CN109471019 B CN 109471019B CN 201811535481 A CN201811535481 A CN 201811535481A CN 109471019 B CN109471019 B CN 109471019B
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- low
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- amplifier
- differential input
- noise
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/40—Testing power supplies
Abstract
The invention discloses a low-noise characteristic testing device of a power supply chip, which comprises a power supply chip to be tested; the power frequency signal trap circuit is connected with the power supply chip to be detected; the low-noise amplifier is connected with the power frequency signal trap circuit and can adjust the gain; the single-ended input-to-differential input circuit is connected with the low-noise amplifier; the differential input high-precision digital-to-analog converter is connected with the single-ended input to differential input circuit; the processing unit is connected with the differential input high-precision digital-to-analog converter; the technical scheme that the processing unit is connected with the level converter, and the level converter is connected with the data receiving equipment can be used for testing the low-noise characteristic of the power supply chip.
Description
Technical Field
The invention relates to a low-noise characteristic testing device for a power supply chip.
Background
The low-noise reference voltage tested on the chip has very low noise frequency spectrum, the background noise of the test equipment is far lower than the frequency spectrum of the signal to be tested to accurately complete the test, and the background noise of the test equipment can not meet the requirement of measuring the noise frequency spectrum of the low-noise reference voltage under the normal condition.
Disclosure of Invention
The invention aims to solve the technical problem of providing a power supply chip low-noise characteristic testing device which can amplify the noise of a signal to be tested by a certain multiple, so that the amplified noise is far larger than the background noise of testing equipment, and the accurate measurement of a low-noise reference voltage frequency spectrum is realized.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows: a power chip low noise characteristic testing device comprises a power chip to be tested; the power frequency signal trap circuit is connected with the power supply chip to be detected and is used for filtering the power frequency signal; the low-noise amplifier is connected with the power frequency signal trap circuit and can adjust the gain, and a detected low-noise signal is amplified through the low-noise amplifier; the single-ended input-to-differential input circuit is connected with the low noise amplifier, and the single-ended input-to-differential input circuit effectively inhibits the power supply frequency so as to have better output swing amplitude; the differential input high-precision digital-to-analog converter is connected with the single-ended input to differential input circuit and converts an analog signal into a digital signal through the differential input high-precision digital-to-analog converter; the processing unit is connected with the differential input high-precision digital-to-analog converter and is used for processing and collecting digital signals; the processing unit is connected to a level shifter, by means of which the digital level is converted to an analog level, the level shifter being connected to the data receiving device.
Further, preferably, a dc blocking component is connected between the power frequency signal trap circuit and the power supply chip to be tested.
More preferably, the dc blocking component, the power frequency signal notch circuit, the low-noise amplifier, the single-ended input to differential input circuit, the differential input high-precision digital-to-analog converter, the processing unit, and the level shifter are all disposed in a shielding box.
More preferably, the direct current blocking component is connected with the power supply to be tested through a high-shielding connector.
More preferably, the level shifter is connected to the data receiving device via a standard uarts 2323 interface.
Preferably, the data receiving device comprises an upper computer, an oscilloscope or a mass spectrometer.
More preferably, the dc blocking component comprises a capacitor.
Preferably, the processing unit comprises an FPGA or a microprocessor.
More preferably, the low noise amplifier includes an AD797 amplifier, a positive input terminal of the AD797 amplifier is connected to a first capacitor and a first resistor, the other terminal of the first capacitor is connected to the power frequency signal trap circuit, the other terminal of the first resistor is grounded, a negative input terminal of the AD797 amplifier is connected to an adjustable resistor, a second resistor is connected between the negative input terminal and the output terminal of the AD797 amplifier, the output terminal of the AD797 amplifier is connected to a second capacitor, and the other terminal of the second capacitor is connected to the single-ended input differential input circuit.
More preferably, the adjustable range of the adjustable resistor is 10 Ω -200 Ω.
The invention has the beneficial effects that: according to the invention, the noise of the signal to be tested is amplified through the low-noise amplifier, so that the amplified noise is far larger than the background noise of the test equipment, thereby realizing accurate measurement of the low-noise reference voltage frequency spectrum, and reducing the background noise of the test equipment and the precision requirement of the digital-to-analog converter.
Drawings
FIG. 1 is a schematic diagram of a power chip low noise characteristic testing apparatus according to the present invention;
fig. 2 is a schematic diagram of the structure of the low noise amplifier of the present invention.
Detailed Description
The present invention is further described below in conjunction with the following figures and specific examples so that those skilled in the art may better understand the present invention and practice it, but the examples are not intended to limit the present invention.
Referring to fig. 1, the embodiment discloses a power chip low noise characteristic testing apparatus, which includes a tested power chip 10, the tested power chip 10 is fixed on a testing fixture, a power frequency signal notch circuit 20 connected to the tested power chip 10 filters a power frequency signal in a tested noise signal through the power frequency signal notch circuit 20, a dc blocking component 30 is connected between the power frequency signal notch circuit 20 and the tested power chip 10, the dc blocking component 30 includes a capacitor, and a dc portion in the tested noise signal is blocked through the dc blocking component 30; the gain-adjustable low-noise amplifier 40 connected with the power frequency signal trap circuit 20 amplifies the detected low-noise signal through the low-noise amplifier 40, so that the amplified noise signal is larger than the background noise of the test equipment, and the test equipment comprises an upper computer, an oscilloscope or a mass spectrometer; the single-ended input to differential input circuit 50 connected with the low noise amplifier 40 effectively suppresses the working power supply frequency in the line through the single-ended input to differential input circuit 50, so that the output swing amplitude is better; a differential input high-precision digital-to-analog converter 60 connected to the single-ended input to differential input circuit 50, for converting an analog signal into a digital signal through the differential input high-precision digital-to-analog converter 60; the processing unit 70 is connected with the differential input high-precision digital-to-analog converter 60, the digital signals are processed and collected through the processing unit 70, and the processing unit 70 comprises an FPGA or a microprocessor; the processing unit 70 is connected with the level shifter 80, the level shifter 80 is an RS232 level shifter, the RS232 level shifter 80 is connected with the data receiving device 100, the digital level is converted into an analog level which can be received by the data receiving device 100 through the RS232 level shifter 80, the RS232 level shifter 80 is connected with the data receiving device 100 through a standard uarts RS2323 interface 90, the data receiving device 100 comprises an upper computer, an oscilloscope or a mass spectrometer, and the noise signal is displayed through the data receiving device 100;
the direct current blocking component 30, the power frequency signal trap circuit 20, the low noise amplifier 40, the single-ended input to differential input circuit 50, the differential input high-precision digital-to-analog converter 60, the processing unit 70 and the RS232 level converter 80 are all arranged in the shielding box 200, external signal interference is isolated through the shielding box 200, the direct current blocking component 30 is connected with the power chip 10 to be tested through the high-shielding connector 110, the shielding box 200 is provided with a first interface, the first interface is connected with the direct current blocking component 30 in the shielding box 200, and the power chip 10 to be tested is connected with the first interface through the high-shielding connector 110;
the low noise amplifier 40 comprises an AD797 amplifier, the AD797 amplifier has the characteristics of extremely low noise and low distortion, the positive input end of the AD797 amplifier is connected with a first capacitor C1 and a first resistor R1, the capacitance value of the first capacitor C1 is 1300 muF, the resistance value of the first resistor R1 is 1k omega, the other end of the first capacitor C1 is connected with the power frequency signal trap circuit 20, the other end of the first resistor R1 is grounded, the negative input end of the AD797 amplifier is connected with an adjustable resistor Rf, the adjustable range of the adjustable resistor Rf is 10 omega-200 omega, the amplification factor of the AD797 amplifier can be adjusted through the adjustable resistor Rf, a second resistor R2 is connected between the negative input end and the output end of the AD797 amplifier, the resistance value of the second resistor R2 is 200k omega, the output end of the AD797 amplifier is connected with a second capacitor C2, the capacitance value of the second capacitor C2 is 20 muF, and the other end of the second capacitor C2 is connected with the single-ended input differential input circuit 50.
The above embodiments are merely preferred embodiments for fully illustrating the present invention, and the scope of the present invention is not limited thereto. The equivalent substitution or change made by the technical personnel in the technical field on the basis of the invention is all within the protection scope of the invention. The protection scope of the invention is subject to the claims.
Claims (10)
1. The utility model provides a power chip low noise characteristic testing arrangement which characterized in that: comprises a power supply chip to be tested; the power frequency signal trap circuit is connected with the power supply chip to be detected and is used for filtering the power frequency signal; the low-noise amplifier is connected with the power frequency signal trap circuit and can adjust the gain, and a detected low-noise signal is amplified through the low-noise amplifier; the single-ended input-to-differential input circuit is connected with the low noise amplifier, and the single-ended input-to-differential input circuit effectively inhibits the power supply frequency so as to have better output swing amplitude; the differential input high-precision digital-to-analog converter is connected with the single-ended input to differential input circuit and converts an analog signal into a digital signal through the differential input high-precision digital-to-analog converter; the processing unit is connected with the differential input high-precision digital-to-analog converter and is used for processing and collecting digital signals; the processing unit is connected to a level shifter, by means of which the digital level is converted to an analog level, the level shifter being connected to the data receiving device.
2. The apparatus for testing low noise characteristics of a power chip as claimed in claim 1, wherein a dc blocking unit is connected between the power frequency signal trap circuit and the power chip to be tested.
3. The power chip low-noise characteristic testing device of claim 2, wherein the dc blocking component, the power frequency signal trap circuit, the low-noise amplifier, the single-ended input to differential input circuit, the differential input high-precision digital-to-analog converter, the processing unit and the level shifter are all disposed in a shielding box.
4. The device for testing the low noise characteristics of the power chip as claimed in claim 3, wherein the DC blocking component is connected to the power source to be tested through a high-shielding connector.
5. The power supply chip low noise characteristic testing device as claimed in claim 3, wherein the level shifter is connected with the data receiving equipment through a standard UARTRS2323 interface.
6. The power supply chip low noise characteristic testing device according to claim 1, wherein the data receiving equipment comprises an upper computer, an oscilloscope or a mass spectrometer.
7. The power chip low-noise characteristic testing device as claimed in claim 2, wherein the dc blocking component includes a capacitor.
8. The power supply chip low noise characteristic testing device as claimed in claim 1, wherein the processing unit comprises an FPGA or a microprocessor.
9. The device for testing the low noise characteristics of the power chip as claimed in claim 3, wherein the low noise amplifier comprises an AD797 amplifier, a positive input terminal of the AD797 amplifier is connected to a first capacitor and a first resistor, the other terminal of the first capacitor is connected to the power frequency signal trap circuit, the other terminal of the first resistor is grounded, a negative input terminal of the AD797 amplifier is connected to the adjustable resistor, a second resistor is connected between the negative input terminal and the output terminal of the AD797 amplifier, the output terminal of the AD797 amplifier is connected to a second capacitor, and the other terminal of the second capacitor is connected to the single-ended input differential input circuit.
10. The power chip low-noise characteristic testing device as claimed in claim 9, wherein the adjustable range of the adjustable resistor is 10 Ω -200 Ω.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811535481.0A CN109471019B (en) | 2018-12-14 | 2018-12-14 | Power chip low noise characteristic testing arrangement |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811535481.0A CN109471019B (en) | 2018-12-14 | 2018-12-14 | Power chip low noise characteristic testing arrangement |
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| Publication Number | Publication Date |
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| CN109471019A CN109471019A (en) | 2019-03-15 |
| CN109471019B true CN109471019B (en) | 2021-10-19 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102252670A (en) * | 2011-05-27 | 2011-11-23 | 哈尔滨工程大学 | Digital closed loop-based optic fiber gyroscope output signal detecting device and method |
| CN104242831A (en) * | 2014-10-17 | 2014-12-24 | 绵阳雷迪创微电子科技有限公司 | Wideband amplification device with low noise |
| CN107528559A (en) * | 2017-08-30 | 2017-12-29 | 海鹰企业集团有限责任公司 | Noiselike signal modulate circuit |
| CN108897711A (en) * | 2018-09-21 | 2018-11-27 | 北京神经元网络技术有限公司 | Analog front-end device applied to two-wire system bus |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10050336C1 (en) * | 2000-10-11 | 2002-07-25 | Infineon Technologies Ag | Programmable echo compensation filter for transceiver uses programmable resistance circuits with parallel resistors and associated controlled switches |
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- 2018-12-14 CN CN201811535481.0A patent/CN109471019B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102252670A (en) * | 2011-05-27 | 2011-11-23 | 哈尔滨工程大学 | Digital closed loop-based optic fiber gyroscope output signal detecting device and method |
| CN104242831A (en) * | 2014-10-17 | 2014-12-24 | 绵阳雷迪创微电子科技有限公司 | Wideband amplification device with low noise |
| CN107528559A (en) * | 2017-08-30 | 2017-12-29 | 海鹰企业集团有限责任公司 | Noiselike signal modulate circuit |
| CN108897711A (en) * | 2018-09-21 | 2018-11-27 | 北京神经元网络技术有限公司 | Analog front-end device applied to two-wire system bus |
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Address after: 215100 South 3rd and 4th Floors of Huanxiu Lake Building, Xiangcheng High-speed Railway New Town, Suzhou City, Jiangsu Province Applicant after: Jiangsu Ji Ju micro automation system and equipment Technology Research Institute Co., Ltd. Address before: 215100 F003 workstation, 3rd floor, 58 South Tiancheng Road, Xiangcheng High-speed Railway New Town, Suzhou City, Jiangsu Province Applicant before: Jiangsu Ji Ju micro automation system and equipment Technology Research Institute Co., Ltd. |
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