CN109462513A - A kind of dispatch terminal double nip fast replacing method based on FPGA - Google Patents
A kind of dispatch terminal double nip fast replacing method based on FPGA Download PDFInfo
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- CN109462513A CN109462513A CN201811599628.2A CN201811599628A CN109462513A CN 109462513 A CN109462513 A CN 109462513A CN 201811599628 A CN201811599628 A CN 201811599628A CN 109462513 A CN109462513 A CN 109462513A
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- fpga
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- dispatch terminal
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/06—Management of faults, events, alarms or notifications
- H04L41/0654—Management of faults, events, alarms or notifications using network fault recovery
- H04L41/0663—Performing the actions predefined by failover planning, e.g. switching to standby network elements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/10—Active monitoring, e.g. heartbeat, ping or trace-route
Abstract
The invention discloses a kind of dispatch terminal double nip fast replacing method based on FPGA; include the following steps: that FPGA receives active link by primary interface and spare interface respectively and protects the link information of link, and the bit error rate of real-time statistics active link and protection link；When the bit error rate of active link A is more than error threshold value, FPGA carries out active and standby interface switching, and sends local side for switching messages.This method uses FPGA parallel processing, real-time monitoring link state and fast reaction, realizes when the primary interface circuit failure of dispatch terminal, can quickly switch business to spare interface route, and realize the continuous business of reversed process.
Description
Technical field
The present invention relates to a kind of dispatch terminal double nip fast replacing methods, belong to data communication technology field.
Background technique
Train is the national main vehicles of going on a journey, and railway communication traffic control is the orderly fortune of train safety and stability
Capable indispensable guarantee.With the continuous speed-raising of train or even the appearance of high-speed rail, brought more to railway communication traffic control
Strict requirements and challenge.So railway communication controlling equipment will realize hardware 1+1 backup to improve product reliability, scheduling
Terminal is the equipment directly used in railway staff's work on duty, is used for 1+ using two line interfaces on dispatch terminal
1 protection.
Currently, traditional masterslave switchover is realized by program, mainly bottom software timing detects primary route shape
State, when main line interrupts, bottom software is able to detect that communication disruption, at the same bottom by bottom interrupt event with the shape of message
Formula is sent to application layer software, after application layer receives message, switches the business to extension wire.
But the mode of this automatic regular polling detection and message transmission, the time from line interruption to business recovery is longer,
The phenomenon that even will appear dropped calls once in a while.It, can will so need a kind of method to realize when main line breaks down
Call is switched to extension wire, and not broken words of conversing.
Summary of the invention
In view of the deficiencies of the prior art, technical problem to be solved by the present invention lies in provide a kind of scheduling based on FPGA
Terminal double nip fast replacing method.
For achieving the above object, the present invention uses following technical solutions:
A kind of dispatch terminal double nip fast replacing method based on FPGA, includes the following steps:
FPGA receives active link by primary interface and spare interface respectively and protects the link information of link, and in real time
The bit error rate of statistical work link and protection link；
When the bit error rate of active link is more than error threshold value, FPGA carries out active and standby interface switching, and switching messages are sent out
It is sent to local side.
Wherein more preferably, the FPGA receives active link and protection link both links business simultaneously, dispatches with local side
Central office service plate is communicated.
Wherein more preferably, when active link works normally, the active link carries out normal call and business transmission；
The protection link carries out basic overhead processing.
Wherein more preferably, the FPGA is used to active link and the double hair modes of protection link and is communicated with local side.
Wherein more preferably, in the detection process of link failure, the bit error rate of FPGA real-time statistics standby usage link passes through
The link information of fixed overhead position monitoring local side transmission active link.
Wherein more preferably, after terminal CPU subjectivity, which has issued, switches order, activation switchover request, and pass through fixed overhead
Local side is sent by switch messages.
Wherein more preferably, when the bit error rate of active link is more than error threshold value, before FPGA carries out active and standby interface switching,
Further include following steps:
Judge to protect whether link breaks down, FPGA is cut without active and standby interface if protection link breaks down
It changes；Otherwise downlink traffic is switched to the corresponding protection link of former spare interface by FPGA.
Wherein more preferably, when link model is 1+1 model, active link and protection chain road duplication service flow,
Active link maintains current business path to work on after switching；Until active link breaks down again.
Wherein more preferably, the dispatch terminal double nip fast replacing method based on FPGA, further includes following steps:
After receiving switch messages, local side carries out link switching according to switch messages.
Dispatch terminal double nip fast replacing method provided by the present invention based on FPGA, FPGA by primary interface and
Spare interface receives active link respectively and protects the link information of link, and the mistake of real-time statistics active link and protection link
Code rate；When the bit error rate of active link is more than error threshold value, FPGA carries out active and standby interface switching, i.e. FPGA cuts downlink traffic
Change to the corresponding protection link of former spare interface；And local side is sent by switching messages；It realizes when the primary of dispatch terminal connects
When mouth line fault, business can quickly be switched to spare interface route, the continuous business of reversed process.
Detailed description of the invention
Fig. 1 is the flow chart of the dispatch terminal double nip fast replacing method provided by the present invention based on FPGA；
Fig. 2 is the knot of dispatch terminal and scheduling switch progress information exchange in one embodiment provided by the present invention
Structure schematic diagram.
Specific embodiment
Detailed specific description is carried out to technology contents of the invention in the following with reference to the drawings and specific embodiments.
Dispatch terminal double nip fast replacing method provided by the present invention based on FPGA is mainly used in railway communication
The dispatch terminal of industry is dispatched, the hardware characteristics based on the dispatch terminal, two interfaces (primary interface 1 and spare interface 2) are even
The same FPGA is met, realizes that double nip is quickly switched when main line breaks down, guarantee business is not interrupted.If dispatch terminal
Two interfaces connect different FPGA, then need further to be communicated by cpu in inside, what is substantially used remains
The mode of existing soft detection communication disruption can not reach call being switched to extension wire when main line breaks down, and
The effect of call not broken words.Dispatch terminal double nip fast replacing method provided by the present invention based on FPGA, based on above-mentioned
Hardware characteristics, using FPGA parallel processing, the primary interface for working as dispatch terminal is realized in real-time monitoring link state and fast reaction
When line fault, business can quickly be switched to spare interface route, and the continuous business of reversed process.
As shown in Figure 1, the dispatch terminal double nip fast replacing method provided by the present invention based on FPGA, including it is as follows
Step: firstly, FPGA receives active link A by primary interface 1 and spare interface 2 respectively and protects the link information of link B,
And the bit error rate of real-time statistics active link A and protection link B；When the bit error rate of active link A is more than error threshold value, FPGA
Judge to protect whether link B can be used, carries out active and standby interface switching when protecting link available, and send office for switching messages
End.Detailed specific description is carried out to this process below.
S1, FPGA receive active link A by primary interface 1 and spare interface 2 respectively and the link of link B are protected to believe
Breath, and the bit error rate of real-time statistics active link A and protection link B.
FPGA (Field-Programmable Gate Array, i.e. field programmable gate array) passes through primary interface 1
It receives active link A respectively with spare interface 2 and protects the link information of link B.In embodiment provided by the present invention,
FPGA realizes that pretection switch function protects model using mainstay dual-port, i.e. FPGA receives work from interface conversion unit simultaneously
Make link A and protection link B both links business, is communicated with corresponding local side dispatching telephone control board business board, as shown in Figure 2.
Wherein, active link A is normally conversed, business is transmitted etc., i.e. the link information of active link A is normal
Call, business transmission etc.；Protection link B carries out basic overhead processing, and distally in place, working condition, reception state etc.
Instruction, i.e. the link information of active link B is basic overhead processing, and the finger such as distal end is in place, working condition, reception state
Show.
The FPGA of terminal incites somebody to action CPU in current each state reporting to local terminal.Business down direction, FPGA first choice main line (work
Make link A) speech channel business is received, when main line failure, then extension wire (protection link B) is selected to receive speech channel business, on
Line direction, FPGA is used to the double hair modes of master spare circuit and is communicated with local side, when reducing main line failure when pretection switch
Between.
In the detection process of link failure, the bit error rate of FPGA real-time statistics standby usage link passes through fixed overhead position
Set the link information for the active link A that monitoring local side is sent.
S2, when the bit error rate of active link A is more than error threshold value, FPGA carries out active and standby interface switching, and will switch and disappear
Breath is sent to local side.
When the bit error rate of active link A exceeds certain thresholding, i.e. error threshold value, guarantor that FPGA is configured by control centre
Shield switch mode is switched fast, i.e., reporting interruption to CPU passively switches or actively switches.And it sends switching messages to
Local side.Wherein, when the bit error rate of active link A is more than error threshold value, FPGA carry out further include before the switching of active and standby interface as
Lower step:
Judge to protect whether link breaks down, FPGA is cut without active and standby interface if protection link breaks down
It changes；Otherwise downlink traffic is switched to the corresponding protection link of former spare interface by FPGA.
Specifically, when terminal works normally, up direction switches expense and indicates link state byte send always " can
With ".When terminal detects link failure, the cost links state byte of switching of current failure link sends " unavailable " (attention
No matter it is current whether standby usage).Primary operational is as follows when breaking down to link: when terminal detects protection link failure or work
Make link and protection link all failure when, still maintain work at present path, until certain link state release " unavailable " touch afterwards
Hair switches behavior；When terminal detection active link error protection link is normal, behavior is switched in triggering immediately.
In embodiment provided by the present invention, it is as follows to switch the operation that behavior occurs according to link model: when link mould
Type be 1+1 model when, active link and protection chain road will duplication service flow, active link switch after maintain currently
Service path works on；Until active link breaks down again.
In embodiment provided by the present invention, when being more than error threshold value in addition to the bit error rate of active link A, FPGA will be fallen
Request is changed to be sent to outside local side, after terminal CPU subjectivity is handed down to FPGA related command (such as Forced Switch, Manual Switch),
Activation switchover request, and local side is sent for switch messages by fixed overhead.Wherein, which includes main/slave link
Link state.Specifically, FPGA, which is switched to protection chain road, following triggering form: 1) terminal works entity is by switching expense
Detect that active link fails, FPGA carries out link switching (i.e. the bit error rate is more than error threshold value)；2) local side interchanger hair is received
The pressure switching request come, terminal equally carry out link switching；3) operator passes through the human-computer interaction interface or key of terminal
Carry out the link switching of triggering terminal.
When the bit error rate, which exceeds, to be changed more than error threshold value or route standby usage information, the timely trigger link failure of meeting
Related event interrupt reports CPU.
Further include following steps in embodiment provided by the present invention:
S3, after receiving switch messages, local side carries out link switching according to switch messages.
In conclusion FPGA receives active link by primary interface and spare interface respectively and the link of link is protected to believe
Breath, and the bit error rate of real-time statistics active link and protection link；When the bit error rate of active link is more than error threshold value, FPGA
Active and standby interface switching is carried out, i.e. downlink traffic is switched to the corresponding protection link of former spare interface by FPGA.And by switching messages
It is sent to local side.The characteristics of due to FPGA concurrent working, does not need real time polling compared to CPU, and generating fault detection can be straight
It connects automatic switchover or occurs to interrupt control centre's initiation switching command.
The present invention has the advantage that
Pretection switch technology is a kind of means for improving communication reliability, by time to the detection of failure and flow
Switching, the negotiation of sourcesink node, guarantee business can be repaired quickly when breaking down.Using base provided by the present invention
In the dispatch terminal double nip fast replacing method of FPGA, applicable mode is set as according to practical application, switches behavior
When can theoretically guarantee service disconnection be no more than 10ms so that service damage is preferably minimized, speech quality is almost without influence.Together
When design cost it is lower, using FPGA Parallel transmutation characteristic quick response operate, without CPU poll increase the waiting time, significantly
Enhance availability.
The dispatch terminal double nip fast replacing method to provided by the present invention based on FPGA has carried out detailed above
Explanation.For those of ordinary skill in the art, it is done under the premise of without departing substantially from true spirit any
Obvious change, the infringement for all weighing composition to the invention patent will undertake corresponding legal liabilities.
Claims (9)
1. a kind of dispatch terminal double nip fast replacing method based on FPGA, it is characterised in that include the following steps:
FPGA receives active link by primary interface and spare interface respectively and protects the link information of link, and real-time statistics
The bit error rate of active link and protection link；
When the bit error rate of active link A is more than error threshold value, FPGA carries out active and standby interface switching, and sends switching messages to
Local side.
2. the dispatch terminal double nip fast replacing method based on FPGA as described in claim 1, it is characterised in that:
The FPGA receives active link and protection link both links business simultaneously, is led to local side dispatching telephone control board business board
Letter.
3. the dispatch terminal double nip fast replacing method based on FPGA as described in claim 1, it is characterised in that:
When active link works normally, the active link carries out normal call and business transmission；The protection link into
The basic overhead processing of row.
4. the dispatch terminal double nip fast replacing method based on FPGA as described in claim 1, it is characterised in that:
The FPGA is used to active link and the double hair modes of protection link and is communicated with local side.
5. the dispatch terminal double nip fast replacing method based on FPGA as described in claim 1, it is characterised in that:
In the detection process of link failure, the bit error rate of FPGA real-time statistics standby usage link is supervised by fixed overhead position
Survey the link information that local side sends active link.
6. the dispatch terminal double nip fast replacing method based on FPGA as described in claim 1, it is characterised in that:
After terminal CPU subjectivity, which has issued, switches order, activation switchover request, and sent switch messages to by fixed overhead
Local side.
7. the dispatch terminal double nip fast replacing method based on FPGA as described in claim 1, it is characterised in that work as work
When the bit error rate of link is more than error threshold value, it further includes before following steps that FPGA, which carries out active and standby interface switching:
Judge to protect whether link breaks down, FPGA switches without active and standby interface if protection link breaks down；It is no
Then downlink traffic is switched to the corresponding protection link of former spare interface by FPGA.
8. the dispatch terminal double nip fast replacing method based on FPGA as claimed in claim 7, it is characterised in that:
When link model is 1+1 model, active link and protection chain road duplication service flow, active link are switched
Current business path is maintained to work on afterwards；Until active link breaks down again.
9. the dispatch terminal double nip fast replacing method based on FPGA as described in claim 1, it is characterised in that further include
Following steps:
After receiving switch messages, local side carries out link switching according to switch messages.
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| CN201811599628.2A CN109462513A (en) | 2018-12-26 | 2018-12-26 | A kind of dispatch terminal double nip fast replacing method based on FPGA |
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| CN201811599628.2A CN109462513A (en) | 2018-12-26 | 2018-12-26 | A kind of dispatch terminal double nip fast replacing method based on FPGA |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110798359A (en) * | 2019-11-06 | 2020-02-14 | 中国电子科技集团公司第三十研究所 | Automatic switching high-reliability user number allocation method |
| CN111221755A (en) * | 2019-12-28 | 2020-06-02 | 重庆秦嵩科技有限公司 | Io interrupt control method for FPGA2 submodule |
| CN112217721A (en) * | 2020-09-29 | 2021-01-12 | 北京东土军悦科技有限公司 | Communication path determining method in switching chip, computer device and storage medium |
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| US20110149788A1 (en) * | 2000-05-12 | 2011-06-23 | Justing Che-I Chuang | Method and System for Integrates Link Adaptation and Power Control to Improve Error and Throughput Performance in Wireless Packet Networks |
| CN106533938A (en) * | 2016-11-01 | 2017-03-22 | 上海斐讯数据通信技术有限公司 | Wireless router having service protection function and working method thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110798359A (en) * | 2019-11-06 | 2020-02-14 | 中国电子科技集团公司第三十研究所 | Automatic switching high-reliability user number allocation method |
| CN110798359B (en) * | 2019-11-06 | 2022-02-25 | 中国电子科技集团公司第三十研究所 | Automatic switching high-reliability user number allocation method |
| CN111221755A (en) * | 2019-12-28 | 2020-06-02 | 重庆秦嵩科技有限公司 | Io interrupt control method for FPGA2 submodule |
| CN112217721A (en) * | 2020-09-29 | 2021-01-12 | 北京东土军悦科技有限公司 | Communication path determining method in switching chip, computer device and storage medium |
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Application publication date: 20190312 |