CN109459607B - Isolated accurate zero-crossing detection circuit - Google Patents
Isolated accurate zero-crossing detection circuit Download PDFInfo
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- CN109459607B CN109459607B CN201811271253.7A CN201811271253A CN109459607B CN 109459607 B CN109459607 B CN 109459607B CN 201811271253 A CN201811271253 A CN 201811271253A CN 109459607 B CN109459607 B CN 109459607B
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- 238000001514 detection method Methods 0.000 title claims abstract description 105
- 238000002955 isolation Methods 0.000 claims abstract description 53
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims abstract description 14
- 239000003990 capacitor Substances 0.000 claims description 53
- 230000005669 field effect Effects 0.000 claims description 31
- 238000000034 method Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 8
- 230000000087 stabilizing effect Effects 0.000 description 5
- 238000007599 discharging Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/175—Indicating the instants of passage of current or voltage through a given value, e.g. passage through zero
Abstract
The invention provides an isolated accurate zero-crossing detection circuit, which comprises: the device comprises a waveform positive and negative detection circuit, an isolation circuit and a signal generation circuit; the alternating current signal of the alternating current detection source is transmitted into a waveform positive and negative detection circuit, and the waveform positive and negative detection circuit controls an isolation circuit to transmit the waveform positive and negative signals to a signal generation circuit. The method has the advantages that zero-crossing detection of an alternating current source is realized, larger detection errors existing in normal zero-crossing detection are avoided, and isolation of a circuit is realized by utilizing an optocoupler.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a zero-crossing detection circuit.
Background
Zero crossing detection refers to detection by the system as the waveform transitions from a positive half cycle to a negative half cycle through zero in an ac system. The zero crossing detection may be a switching circuit or a frequency detection. The method has wide application in power factor correction of a rectifying circuit, synchronous grid connection of a grid island and the like, synchronization of circuit loads and the like.
However, the existing zero-crossing detection circuit has the following drawbacks:
1. the common photoelectric coupler zero-crossing detection circuit emits pulses at the zero crossing point of the alternating current detection source, positive and negative half cycles cannot be distinguished, and the zero-crossing pulse width cannot be controlled.
2. The zero-crossing detection circuit is effectively controlled by the triode, but the zero-crossing detection precision is low and is easy to be interfered by clutter.
3. Zero crossing detection is performed through the comparator, so that the current and effective electric isolation cannot be realized, and the current and effective electric isolation is easy to interfere.
Disclosure of Invention
The invention provides an isolated type accurate zero-crossing detection circuit, which overcomes the defects of the prior art.
The invention provides an isolated accurate zero-crossing detection circuit, which comprises: the device comprises a waveform positive and negative detection circuit, an isolation circuit and a signal generation circuit; the waveform positive and negative detection compensation circuit comprises a current limiting resistor R2, a diode D1 and a detection compensation capacitor C1; the isolation circuit includes: the device comprises a current limiting resistor R1, an isolation optocoupler U2, a field effect transistor U1, a current limiting resistor R3 and a current limiting resistor R4; one end of the current limiting resistor R2 is connected with one end of the INPUT signal INPUT, and the other end of the current limiting resistor R2 is connected with the anode of the diode D1; the negative electrode of a diode D1 at one end of the detection compensation capacitor C1 is connected, and the other end of the detection compensation capacitor C1 is connected with the other end of the INPUT signal INPUT; one end of the detection compensation capacitor C1 is also connected with one input end of the isolation optocoupler U2 of the isolation circuit; one input end of the isolation optocoupler U2 is connected with one end of the detection compensation capacitor C1, and the other input end of the isolation optocoupler U2 is connected with one end of the current-limiting resistor R3; the other end of the current limiting resistor R3 is connected with the drain electrode of the field effect transistor U1; the source electrode of the field effect transistor U1 is connected with the other end of the detection compensation capacitor C1 and the other end of the INPUT signal INPUT; one end of the current limiting resistor R1 is connected with the grid electrode of the field effect transistor U1, and the other end of the current limiting resistor R1 is connected with one end of the INPUT signal INPUT; one output end of the isolation optocoupler U2 is connected with an auxiliary power supply VCC of the signal generating circuit, and the other output end of the isolation optocoupler U2 is connected with the signal generating circuit and is grounded after passing through a current limiting resistor R4.
Further, the invention provides an isolated accurate zero-crossing detection circuit, which can also have the following characteristics: the waveform positive and negative detection compensation circuit also comprises a zener diode D2; the zener diode D2 is connected in parallel to both ends of the detection compensation capacitor C1.
Further, the invention provides an isolated accurate zero-crossing detection circuit, which can also have the following characteristics: the negative electrode of the zener diode D2 is connected to the negative electrode of the diode D1, and the positive electrode is connected to the other end of the INPUT signal INPUT.
Further, the invention provides an isolated accurate zero-crossing detection circuit, which can also have the following characteristics: the field effect transistor U1 is an N-type field effect transistor.
Further, the invention provides an isolated accurate zero-crossing detection circuit, which can also have the following characteristics: the isolation circuit further comprises a zener diode D3; the zener diode D3 is connected in parallel with two ends of the grid electrode and the source electrode of the N-type field effect transistor U1; one end of the current limiting resistor R1 is also connected with the cathode of the zener diode D3.
Further, the invention provides an isolated accurate zero-crossing detection circuit, which can also have the following characteristics: the signal generation circuit includes: a NAND gate chip U3, a NAND gate chip U4, a NAND gate chip U5 and a maintaining capacitor C2; one input end of the NAND gate chip U3 is connected with the output port of the NAND gate chip U4, and the other input end of the NAND gate chip U3 is connected with the other output end of the isolation optocoupler U2; one input end of the NAND gate chip U4 is connected with the output end of the NAND gate chip U3; one end of the maintaining capacitor C2 is connected with the output end of the NAND gate chip U3, and the other end of the maintaining capacitor C is connected with the other input end of the NAND gate chip U4; two input ends of the NAND gate chip U5 are connected with the OUTPUT end of the NAND gate chip U4, and the OUTPUT end is connected with the signal OUTPUT end.
Further, the invention provides an isolated accurate zero-crossing detection circuit, which can also have the following characteristics: the signal generation circuit further includes: pull-up resistor R5, pull-down resistor R6, pull-up resistor R7, pull-up resistor R8, and auxiliary power supply VCC; one output end of the isolation optocoupler U2 is connected with an auxiliary power supply VCC of the signal generation circuit; the output end of the NAND gate chip U3 is connected with an auxiliary power supply VCC through a pull-up resistor R5; the output end of the NAND gate chip U4 is connected with an auxiliary power supply VCC through a pull-up resistor R7; the output end of the NAND gate chip U5 is connected with an auxiliary power supply VCC through a pull-up resistor R8; the other input of the nand gate chip U4 is grounded through a pull-down resistor R6.
Further, the invention provides an isolated accurate zero-crossing detection circuit, which can also have the following characteristics: the INPUT signal INPUT is an alternating current signal of 110-400V and 50/60 HZ.
Further, the invention provides an isolated accurate zero-crossing detection circuit, which can also have the following characteristics: the other end of the INPUT signal INPUT, the other end of the detection compensation capacitor C1, and the source of the field effect transistor U1 are grounded.
The invention provides an isolated type accurate zero-crossing detection circuit, which realizes zero-crossing detection of an alternating current source, avoids larger detection errors existing in normal zero-crossing detection, and realizes isolation of the circuit by utilizing an optocoupler.
Drawings
Fig. 1 is a circuit diagram of an isolated accurate zero crossing detection circuit of the present invention.
Fig. 2 is a waveform positive-negative detection circuit diagram of the present invention.
Fig. 3 is an isolated circuit diagram of the present invention.
Fig. 4 is a signal generation circuit diagram of the present invention.
Detailed Description
The invention is further described below with reference to the drawings and specific embodiments.
Fig. 1 is a circuit diagram of an isolated accurate zero crossing detection of the present invention.
As shown in fig. 1, an isolated precise zero-crossing detection circuit in this embodiment includes a waveform positive-negative detection circuit, an isolation circuit, and a signal generation circuit. The alternating current signal of the alternating current detection source is transmitted into a waveform positive and negative detection circuit, and the waveform positive and negative detection circuit controls an isolation circuit to transmit the waveform positive and negative signals to a signal generation circuit.
Fig. 2 is a waveform positive-negative detection circuit diagram of the present invention.
As shown in fig. 1 and 2, the waveform positive-negative detection compensation circuit includes: the device comprises a current limiting resistor R2, a diode D1, a detection compensation capacitor C1 and a voltage stabilizing diode D2.
One end of the current limiting resistor R2 is connected with one end of the INPUT signal INPUT, and the other end of the current limiting resistor R2 is connected with the anode of the diode D1. The negative electrode of the diode D1 at one end of the detection compensation capacitor C1 is connected, and the other end of the detection compensation capacitor C1 is connected with the other end of the INPUT signal INPUT. One end of the detection compensation capacitor C1 is also connected with one input end of the isolation optocoupler U2 of the isolation circuit. The zener diode D2 is connected in parallel to two ends of the detection compensation capacitor C1, and the cathode of the zener diode D2 is connected to the cathode of the diode D1, and the anode is connected to the other end of the INPUT signal INPUT.
The INPUT signal INPUT in this embodiment is an alternating current signal of 110-400V, 50/60 HZ. The alternating current signal is connected with the detection compensation capacitor C1 through the current limiting resistor R2 and the diode D1, the detection compensation capacitor C1 can be charged, and the voltage stabilizing diode stabilizes the voltage of the detection compensation capacitor C1. The detection compensation capacitor C1 is connected with the isolation optocoupler U2 and the N-type field effect transistor U1, and when the isolation optocoupler U2 and the N-type field effect transistor U1 are conducted, discharging can be conducted through the isolation optocoupler U2 and the N-type field effect transistor U1.
Fig. 3 is an isolated circuit diagram of the present invention.
As shown in fig. 1 and 3, the isolation circuit includes: the isolation optocoupler U2, the N-type field effect transistor U1, the current limiting resistor R3, the current limiting resistor R4 and the zener diode D3.
One input end of the isolation optocoupler U2 is connected with one end of the detection compensation capacitor C1, and the other input end of the isolation optocoupler U2 is connected with one end of the current-limiting resistor R3; the ac signal and the detection compensation capacitor C1 may be discharged to be turned on. The other end of the current limiting resistor R3 is connected with the drain electrode of the N-type field effect transistor U1; limiting the magnitude of the current through the branch. The source electrode of the N-type field effect transistor U1 is connected with the other end of the detection compensation capacitor C1 and the other end of the INPUT signal INPUT, and is used for controlling the on-off of the branch and controlling the discharge time of the detection compensation capacitor C1. The zener diode D3 is connected in parallel with two ends of the grid electrode and the source electrode of the N-type field effect transistor U1; and the positive electrode of the zener diode D3 is connected with the source electrode of the N-type field effect transistor U1, and the negative electrode is connected with the grid electrode of the N-type field effect transistor U1. One end of the current limiting resistor R1 is connected with the grid electrode of the N-type field effect transistor U1 and the cathode of the zener diode D3, and the other end of the current limiting resistor R1 is connected with one end of the INPUT signal INPUT. The zener diode D3 controls the on-off voltage of the N-type field effect transistor U1.
The other end of the INPUT signal INPUT, the other end of the detection compensation capacitor C1, the positive electrode of the zener diode D2, and the source electrode of the N-type field effect transistor U1 are grounded.
One output end of the isolation optocoupler U2 is connected with an auxiliary power supply VCC of the signal generating circuit, and the other output end of the isolation optocoupler U2 is connected with the signal generating circuit and is grounded after passing through a current limiting resistor R4. The current limiting resistor R4 is connected between the output port of the isolation optocoupler U2 and GND, and transmits the alternating current signals of positive and negative half cycles to the post-stage signal generating circuit.
Fig. 4 is a signal generation circuit diagram of the present invention.
As shown in fig. 1 and 4, the signal generating circuit includes: the NAND gate chip U3, the NAND gate chip U4, the NAND gate chip U5, the maintaining capacitor C2, the pull-up resistor R5, the pull-down resistor R6, the pull-up resistor R7, the pull-up resistor R8 and the auxiliary power supply VCC.
One input end of the NAND gate chip U3 is connected with the output port of the NAND gate chip U4, and the other input end of the NAND gate chip U3 is connected with the other output end of the isolation optocoupler U2. One input end of the NAND gate chip U4 is connected with the output end of the NAND gate chip U3. One end of the holding capacitor C2 is connected with the output end of the NAND gate chip U3, and the other end is connected with the other input end of the NAND gate chip U4. Two input ends of the NAND gate chip U5 are connected with the OUTPUT end of the NAND gate chip U4, and the OUTPUT end is connected with the signal OUTPUT end.
The output end of the NAND gate chip U3 is connected with an auxiliary power supply VCC through a pull-up resistor R5. The output end of the NAND gate chip U4 is connected with an auxiliary power supply VCC through a pull-up resistor R7. The output end of the NAND gate chip U5 is connected with an auxiliary power supply VCC through a pull-up resistor R8. The other input of the nand gate chip U4 is grounded through a pull-down resistor R6. The auxiliary power supply VCC supplies power to the NOT chip U3, the NAND chip U4 and the NAND chip U5.
When the output end of the NAND gate chip U3 suddenly changes, the voltage of the two ends of the maintaining capacitor C2 is kept unchanged, so that the purpose of transmitting signals to the NAND gate chip at the later stage is achieved. Meanwhile, the maintaining capacitor C2 is charged and discharged through the pull-up resistor R5 and the pull-down resistor R6, and the discharging time can be adjusted.
When the alternating current detection source is in the positive half cycle, the diode D1 charges the detection compensation capacitor C1 through the current limiting resistor R1, meanwhile, the N-type field effect transistor U1 is conducted through the voltage stabilizing diode D3 in the direction of the current limiting resistor R2, the alternating current detection source discharges through the current limiting resistor R1, the diode D1, the isolation optocoupler U2 and the N-type field effect transistor U1, the isolation optocoupler U2 is conducted, signals are transmitted to a rear-stage circuit, and when the detection compensation capacitor C1 is charged to the limit voltage of the voltage stabilizing diode D2, the detection compensation capacitor C1 stops charging. When the AC detection source just crosses zero or is about to approach zero, the detection compensation capacitor and the N-type field effect transistor U1 are conducted when the supplied voltage is insufficient, and at the moment, the detection compensation capacitor C1 begins to discharge to compensate the AC detection source, so that the purpose of accurate zero crossing detection is achieved.
When the alternating current detection source is in a negative half cycle, current flows through the voltage stabilizing diode D3, the current limiting resistor R2 is turned on and the voltage drop is caused to turn off U1, so that the isolation optocoupler U2 is turned off, the detection compensation capacitor C1 has no discharge loop, and the voltage at the zero crossing point is maintained.
When the alternating current detection source is in the positive half cycle, the output end of the isolation optocoupler U2 is conducted, the input end of the NAND gate chip U3 connected with the isolation optocoupler U2 is in a high level (1), the other input end of the NAND gate chip U3 is connected with the auxiliary power supply VCC through the pull-up resistor R7 and is also in a high level, at the moment, the output end of the NAND gate chip U3 is in a low level (0), then both input ends of the NAND gate chip U4 are in a low level, and accordingly the output of the NAND gate chip U4 is in a high level, and after the input of the lower level, the final output of the NAND gate chip U5 is in a low level.
When the alternating current detection source is switched from the zero crossing of the positive half cycle to the zero crossing of the negative half cycle, the isolation optocoupler U2 is turned off, the input end of the NAND gate chip U3 connected with the isolation optocoupler U2 is instantly changed from the high level to the low level, the output of the NAND gate chip U3 is instantly increased from the low level to the high level, the input end of the NAND gate chip U4 connected with the maintaining capacitor C2 is instantly increased from the low level to the high level due to the maintaining capacitor C2, the output of the NAND gate chip U4 is at the low level, and the final output of the NAND gate chip U5 is at the high level.
Then, the pull-up resistor R5 and the pull-down resistor R6 of the auxiliary power supply charge the holding capacitor C2 (the charging time is adjustable), after a period of time, the voltage value at two ends of the holding capacitor C2 is VCC, the connection end of the holding capacitor C2 and the nand gate chip U4 is pulled back down to GND, at this time, the output end of the nand gate chip U4 changes to high level again, and the output end of the nand gate chip U5 changes to low level again.
When the power supply passes through the zero again and reaches the positive half cycle, the detection compensation capacitor C1 discharges to enable the isolation optocoupler U2 to be conducted, the output end of the NAND gate chip U3 is easy to push to be changed from high level to low level, the voltages at two ends of the maintenance capacitor C2 are kept unchanged instantaneously, the input end of the NAND gate chip U4 is pulled lower, and finally the low level output of the NAND gate chip U5 is kept unchanged.
The above is shown only a preferred embodiment of the present invention, and the present invention is not limited to the above examples. It will be appreciated that other modifications and variations which may be directly derived or suggested to those skilled in the art without departing from the basic concept of the present invention are deemed to be included within the scope of the present invention.
Claims (9)
1. An isolated accurate zero crossing detection circuit which is characterized in that: the device comprises a waveform positive and negative detection circuit, an isolation circuit and a signal generation circuit;
the waveform positive and negative detection compensation circuit comprises a current limiting resistor R2, a diode D1 and a detection compensation capacitor C1;
the isolation circuit includes: the device comprises a current limiting resistor R1, an isolation optocoupler U2, a field effect transistor U1, a current limiting resistor R3 and a current limiting resistor R4;
one end of the current limiting resistor R2 is connected with one end of the INPUT signal INPUT, and the other end of the current limiting resistor R2 is connected with the anode of the diode D1; the negative electrode of a diode D1 at one end of the detection compensation capacitor C1 is connected, and the other end of the detection compensation capacitor C1 is connected with the other end of the INPUT signal INPUT; one end of the detection compensation capacitor C1 is also connected with one input end of the isolation optocoupler U2 of the isolation circuit;
one input end of the isolation optocoupler U2 is connected with one end of the detection compensation capacitor C1, and the other input end of the isolation optocoupler U2 is connected with one end of the current-limiting resistor R3; the other end of the current limiting resistor R3 is connected with the drain electrode of the field effect transistor U1; the source electrode of the field effect transistor U1 is connected with the other end of the detection compensation capacitor C1 and the other end of the INPUT signal INPUT; one end of the current limiting resistor R1 is connected with the grid electrode of the field effect transistor U1, and the other end of the current limiting resistor R1 is connected with one end of the INPUT signal INPUT;
one output end of the isolation optocoupler U2 is connected with an auxiliary power supply VCC of the signal generating circuit, and the other output end of the isolation optocoupler U2 is connected with the signal generating circuit and is grounded after passing through a current limiting resistor R4.
2. The isolated precision zero-crossing detection circuit of claim 1, wherein:
the waveform positive and negative detection compensation circuit also comprises a zener diode D2; the zener diode D2 is connected in parallel to both ends of the detection compensation capacitor C1.
3. The isolated precision zero-crossing detection circuit of claim 2, wherein:
the negative electrode of the zener diode D2 is connected to the negative electrode of the diode D1, and the positive electrode is connected to the other end of the INPUT signal INPUT.
4. The isolated precision zero-crossing detection circuit of claim 1, wherein:
the field effect transistor U1 is an N-type field effect transistor.
5. The isolated precision zero-crossing detection circuit of claim 1, wherein:
the isolation circuit further comprises a zener diode D3;
the zener diode D3 is connected in parallel with two ends of the grid electrode and the source electrode of the N-type field effect transistor U1; one end of the current limiting resistor R1 is also connected with the cathode of the zener diode D3.
6. The isolated precision zero-crossing detection circuit of claim 1, wherein:
the signal generation circuit includes: a NAND gate chip U3, a NAND gate chip U4, a NAND gate chip U5 and a maintaining capacitor C2;
one input end of the NAND gate chip U3 is connected with the output port of the NAND gate chip U4, and the other input end of the NAND gate chip U3 is connected with the other output end of the isolation optocoupler U2;
one input end of the NAND gate chip U4 is connected with the output end of the NAND gate chip U3;
one end of the maintaining capacitor C2 is connected with the output end of the NAND gate chip U3, and the other end of the maintaining capacitor C is connected with the other input end of the NAND gate chip U4;
two input ends of the NAND gate chip U5 are connected with the OUTPUT end of the NAND gate chip U4, and the OUTPUT end is connected with the signal OUTPUT end.
7. The isolated precision zero-crossing detection circuit of claim 6, wherein:
the signal generation circuit further includes: pull-up resistor R5, pull-down resistor R6, pull-up resistor R7, pull-up resistor R8, and auxiliary power supply VCC;
one output end of the isolation optocoupler U2 is connected with an auxiliary power supply VCC of the signal generation circuit;
the output end of the NAND gate chip U3 is connected with an auxiliary power supply VCC through a pull-up resistor R5; the output end of the NAND gate chip U4 is connected with an auxiliary power supply VCC through a pull-up resistor R7; the output end of the NAND gate chip U5 is connected with an auxiliary power supply VCC through a pull-up resistor R8; the other input of the nand gate chip U4 is grounded through a pull-down resistor R6.
8. An isolated precision zero crossing detection circuit as claimed in any one of claims 1 to 7, wherein: the INPUT signal INPUT is an alternating current signal of 110-400V and 50/60 HZ.
9. An isolated precision zero crossing detection circuit as claimed in any one of claims 1 to 7, wherein:
the other end of the INPUT signal INPUT, the other end of the detection compensation capacitor C1, and the source of the field effect transistor U1 are grounded.
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| CN110346637A (en) * | 2019-08-23 | 2019-10-18 | 邢台子中电子科技有限公司 | A kind of method and device of sinusoid information Digital Extraction |
| CN114113759A (en) | 2021-12-22 | 2022-03-01 | 杭州联芯通半导体有限公司 | Zero-crossing detection circuit |
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| Zero Cross Detection Using Phase Locked Loop;LadislavStastny等;IFAC (International Federation of Automatic Control);294-298 * |
| 基于PLL技术的BLDCM转子位置检测;周子龙等;信息技术;149-152 * |
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| CN109459607A (en) | 2019-03-12 |
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