CN109446015A - A kind of NVMe prototype simulating, verifying structure - Google Patents
A kind of NVMe prototype simulating, verifying structure Download PDFInfo
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- CN109446015A CN109446015A CN201811255540.9A CN201811255540A CN109446015A CN 109446015 A CN109446015 A CN 109446015A CN 201811255540 A CN201811255540 A CN 201811255540A CN 109446015 A CN109446015 A CN 109446015A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
Abstract
The present invention relates to NVMe prototype simulating, verifying structures, wherein includes: simulation framework memory for simulation framework memory；It extracts data and printing receives package informatin module for data to be extracted in data packet, execute decoding, and the package informatin received Printed to File；Decoder module wraps and sends the header packet information wrapped for analyzing to receive；Group packet module is used for the format according to packet, the data or order group packet to be sent；Simulation RAM is for simulating random access memory；It receives array to be used to be stored to the packet received in reception array, sends array and sent in array for the array to be sent to be stored to；NVMe controller is module to be authenticated；Printing sends package informatin module, used in the information for sending packet to be Printed to File.
Description
Technical field
The present invention relates to simulating, verifying technology more particularly to the simulating, verifying structures of NVMe a kind of.
Background technique
Solid state hard disk (SSD) is fast, noiseless, light-weight etc. with speed relative to mechanical hard disk as a kind of electronic hard disc
Advantage.Present more and more computers begin to use solid state hard disk.The AHCI and SATA protocol that solid state hard disk originally uses, with
The progress of SSD, AHCI and SATA become the bottleneck of speed raising.There is NVMe and PCIe protocol to improve speed.
PCIe is a kind of high-speed bus agreement, and PCIe3.0 speed can reach 8Gbps.NVMe agreement has number relative to AHCI protocol, performance
Promotion again, is greatly lowered delay, supports 64000 queues, and the depth of each queue is 64000.Because NVMe's is huge
Advantage, many mechanisms carry out the exploitation of NVMe equipment.In designing and developing NVMe device procedures, existing verifying emulation platform is needed
Two processors are wanted, a processor is as host-processor, processor of another processor as equipment end, each place
Reason device has the software of oneself, therefore expends very much the time when emulation.
Summary of the invention
The purpose of the present invention is to provide a kind of NVMe prototype simulating, verifying structures, for solving asking for the above-mentioned prior art
Topic.
A kind of NVMe prototype simulating, verifying structure of the present invention, wherein include: simulation framework memory (1), decoder module (2),
It extracts data and printing receives package informatin module (10), printing sends package informatin module (11), receives array (14), sends array
(15), packet module (3) and simulation RAM (6) are organized；Simulation framework memory (1) is used for simulation framework memory；Extract data and printing
Package informatin module (10) are received for data to be extracted in data packet, execute decoding, and the package informatin received is beaten
It prints in file；Decoder module (2) wraps and sends the header packet information wrapped for analyzing to receive；Group packet module (3) is used for basis
The format of packet, the data or order group packet to be sent；Simulation RAM (6) is for simulating random access memory；Array (14) are received to use
It is received in array in the packet received is stored to, sends array (15) and be used to be stored to the array to be sent in transmission array；
NVMe controller (5) is module to be authenticated；Printing sends package informatin module (11), for the information for sending packet to be printed to
In file.
One embodiment of NVMe prototype simulating, verifying structure according to the present invention, wherein after receiving write order, by a group packet
After module (3) group packet, it has been sent to NVMe controller (5), NVMe controller (5) issues a read request after receiving write order,
After decoder module (2) decoding, the data to be write are taken to simulation framework memory (1) is inner, data are by group packet module (3) group packet
Afterwards, after NVMe controller (5), it is sent to simulation RAM (6).
One embodiment of NVMe prototype simulating, verifying structure according to the present invention, wherein after receiving read command, by a group packet
After module (3) group packet, it is sent to NVMe controller (5)；NVMe controller (5) issues a write request after receiving read command, from
It simulates RAM (6) and takes out data, after decoder module (2) decoding, it is inner that data are put into simulation framework memory (1).
One embodiment of NVMe prototype simulating, verifying structure according to the present invention, wherein further include: dsport module is used
In the communication for the physical layer and data link layer for carrying out host side PCIe.
One embodiment of NVMe prototype simulating, verifying structure according to the present invention, wherein further include: user's test interface
(7), the interface used for being supplied to user receives the NVMe order for needing to verify.
One embodiment of NVMe prototype simulating, verifying structure according to the present invention, wherein after receiving write order, by a group packet
Module (3) and dsport module (4), are sent to NVMe controller (5), and NVMe controller (5) issues one after receiving write order
Read request by dsport module (4), receives array (14), decoder module (2) and extracts data and printing receives packet letter
It ceases module (10), takes the data to be write to simulation framework memory (1) is inner；Data arrive dsport module (4) by group packet module (3)
And NVMe controller (5), it is sent to simulation RAM (6).
One embodiment of NVMe prototype simulating, verifying structure according to the present invention, wherein after receiving read command, by group
It after packet module (3) and dsport module (4), is sent to NVMe controller (5), NVMe controller (5) is sent out after receiving read command
A write request out takes out data from simulation RAM (6), by dsport module (4), receives array (14), decoder module (2)
And data and printing reception package informatin module (10) are extracted, it is inner to simulation framework memory (1).
One embodiment of NVMe prototype simulating, verifying structure according to the present invention, wherein the data or order to be sent
It is assembled into TLP packet.
One embodiment of NVMe prototype simulating, verifying structure according to the present invention, wherein further include: need to verify instruction packet
Doorbell instruction is write in the instruction and NVMe for having contained instruction, the BAR initialization of system initialization.
One embodiment of NVMe prototype simulating, verifying structure according to the present invention, wherein simulation framework memory (1) is stored with
I/O instruction queue, to complete instruction queue and management instruction queue.
NVMe prototype simulating, verifying structure of the invention, can overcome the speed of existing simulation and verification platform slow, structure is multiple
Miscellaneous disadvantage, can be realized and fast, easily emulate.
Detailed description of the invention
Fig. 1 show the module map of NVMe prototype simulating, verifying structure of the present invention；
Fig. 2 show the module map of an embodiment of NVMe prototype simulating, verifying structure of the present invention.
Specific embodiment
To keep the purpose of the present invention, content and advantage clearer, with reference to the accompanying drawings and examples, to of the invention
Specific embodiment is described in further detail.
Fig. 1 show the module map of NVMe prototype simulating, verifying structure of the present invention, and it is imitative that Fig. 2 show NVMe prototype of the present invention
The module map of one embodiment of true verifying structure, as shown in Figure 1 and Figure 2, NVMe prototype simulating, verifying structure of the present invention includes:
Simulation framework memory (1), extracts data and printing receives package informatin module (10), and printing sends package informatin module (11), decoding
Module (2) receives array (14), sends array (15), organizes packet module (3), dsport module (4), simulates RAM (6), user
Test interface (7).
As shown in Figure 1 and Figure 2, NVMe simulating, verifying structure of the invention, each component are designed using hardware language,
Processor and software are not needed, includes simulation framework memory (1), decoder module (2), group packet module (3), dsport module
(4), RAM (6), user test interface (7) are simulated.Simulation framework memory (1) and decoder module (2) are unidirectionally to connect, simulation master
Machine memory (1) and group packet module (3) are unidirectionally to connect, and user test interface (7) and group packet module (3) are unidirectionally to connect, decoding
Module (2) and dsport module (4) are unidirectionally to connect, and organize packet module (3) and dsport module (4) is unidirectionally to connect, dsport
Module (4) and tested NVMe controller (5) are to be bi-directionally connected, and being tested NVMe controller (5) and simulation RAM (6) is to be bi-directionally connected.
Simulation framework memory (1) and extraction data and printing receive package informatin module (10) unidirectionally connection, extract data and printing receives
Package informatin module (10) and decoder module (2) are unidirectionally to connect, and receive array (14) and decoder module (2) is unidirectionally to connect, beat
Printing and distributing package informatin (11) and decoder module (2) is unidirectionally to connect, and sends array (15) and decoder module (2) is unidirectionally to connect, hair
Array (15) and group packet (3) is sent unidirectionally to connect.
As shown in Figure 1 and Figure 2, simulation framework memory (1) effect is simulation framework memory, and there is I/O instruction queue in the inside,
Instruction queue and management instruction queue are completed, is realized using the array of hardware description language.The function of decoder module (2) is handle
The data packet received is unpacked, and decoding extracts and receives data, according to the execution module for extracting data execution response operation.
The data or order to be sent are assembled into TLP packet according to the format of packet by group packet module (3).The master that dsport module (4) is realized
The physical layer of generator terminal PCIe and the function of data link layer.Simulation RAM (6) is one random access memory of simulation, is realized with array.
User test interface (7) is available to the interface that user uses, and can input the various NVMe orders for needing to verify in the interface.
NVMe writes the workflow of data: user test interface (7) sends out a write order, by a group packet module (3),
Dsport module (4) has been sent to NVMe controller (5).NVMe controller (5) issues a read request after receiving write order,
The data to be write are taken by dsport module (4), decoder module (2), to simulation framework memory (1) is inner.Data are by group Bao Mo
Block (3) arrives dsport module (4), NVMe controller (5), is sent to simulation RAM (6).
NVMe reading data workflow: user test interface (7) send out a read command, by a group packet module (3),
Dsport module (4) has been sent to NVMe controller (5).NVMe controller (5) issues a write request after receiving read command,
Data are taken out from simulation RAM (6), by dsport module (4), decoder module (2), data are put into simulation framework memory (1)
In.
NVMe writes the workflow of data: user test interface (7) sends out a write order, by a group packet module (3),
Dsport module (4) has been sent to NVMe controller (5).NVMe controller (5) issues a read request after receiving write order,
By dsport module (4), array (14), decoder module (2), extraction data and printing reception package informatin module (10) are received,
The data to be write are taken to simulation framework memory (1) is inner.Data arrive dsport module (4), NVMe controller by group packet module (3)
(5), it is sent to simulation RAM (6).
NVMe reading data workflow: user test interface (7) send out a read command, by a group packet module (3),
Dsport module (4) has been sent to NVMe controller (5).NVMe controller (5) issues a write request after receiving read command,
Data are taken out from simulation RAM (6), by dsport module (4), array (14), decoder module (2), extraction data is received and beats
Print receives package informatin module (10), inner to simulation framework memory (1).
As shown in Figure 1 and Figure 2, simulation framework memory (1) uses array simulation framework memory.It extracts data and printing connects
Packet receiving information module (10) extracts data in packet, and decoding executes.The package informatin received is printed to one simultaneously
In file.Printing sends package informatin module (11) and the information for sending packet is printed in a file.Decoder module (2) analysis connects
The head information of packet receiving.Send the head information that decoder module (2) analysis sends packet.Reception array (14), which is stored to the packet received, to be connect
It receives in array.Array (15) are sent to be stored in transmission array the array to be sent.Group packet module (3) presses the data to be sent
Packet is assembled into according to the format of packet.Dsport module (4) is the physical layer and data link layer functions of host side PCIe.User test
Interface (7) be user provide need verify instruction module contain the instruction of system initialization, BAR in this embodiment
The instruction of initialization, NVMe write doorbell instruction.Tested NVMe controller (5) are modules to be authenticated.
The invention discloses one kind be directed to NVMe prototype simulating, verifying structure (8), specifically include that simulation framework memory (1),
Decoder module (2), group packet module (3), dsport module (4), simulation RAM (6), user test interface (7).Simulation framework memory
(1) and decoder module (2) is unidirectionally to connect, and emulating host computer memory (1) and group packet module (3) are unidirectionally to connect, user interface (7)
Unidirectionally to connect with a group packet module (3), decoder module (2) and dsport module (4) they are unidirectionally to connect, organize packet module (3) and
Dsport module (4) is unidirectionally to connect, and dsport module (4) and tested NVMe controller (5) are to be bi-directionally connected, and is tested NVMe control
Device (5) processed and simulation RAM (6) are to be bi-directionally connected.Different NVMe orders can be added in user by (7), send after order group packet
To tested NVMe controller (5), then complete to be written and read simulation RAM (6).The present invention is designed using hardware language, no
Using processor and software, quickly various NVMe can be instructed and carry out simulating, verifying.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, several improvement and deformations can also be made, these improvement and deformations
Also it should be regarded as protection scope of the present invention.
Claims (10)
1. a kind of NVMe prototype simulating, verifying structure characterized by comprising simulation framework memory (1), mentions decoder module (2)
Evidence of fetching and printing receive package informatin module (10), printing sends package informatin module (11), receives array (14), sends array
(15), packet module (3) and simulation RAM (6) are organized；
Simulation framework memory (1) is used for simulation framework memory；It extracts data and printing receives package informatin module (10) and is used for from number
Data are extracted according in packet, execute decoding, and the package informatin received Printed to File；The use of decoder module (2)
Packet is received in analysis and sends the header packet information of packet；Group packet module (3) is used for the format according to packet, the data or life to be sent
Enable group packet；Simulation RAM (6) is for simulating random access memory；Array (14) are received the packet received is used to be stored to reception array
In, it sends array (15) and is used to be stored to the array to be sent in transmission array；NVMe controller (5) is mould to be authenticated
Block；Printing sends package informatin module (11), used in the information for sending packet to be Printed to File.
2. NVMe prototype simulating, verifying structure as described in claim 1, which is characterized in that after receiving write order, by a group packet
After module (3) group packet, it has been sent to NVMe controller (5), NVMe controller (5) issues a read request after receiving write order,
After decoder module (2) decoding, the data to be write are taken to simulation framework memory (1) is inner, data are by group packet module (3) group packet
Afterwards, after NVMe controller (5), it is sent to simulation RAM (6).
3. NVMe prototype simulating, verifying structure as described in claim 1, which is characterized in that after receiving read command, by a group packet
After module (3) group packet, it is sent to NVMe controller (5)；NVMe controller (5) issues a write request after receiving read command, from
It simulates RAM (6) and takes out data, after decoder module (2) decoding, it is inner that data are put into simulation framework memory (1).
4. NVMe prototype simulating, verifying structure as described in claim 1, which is characterized in that further include: dsport module is used for
Carry out the communication of the physical layer and data link layer of host side PCIe.
5. NVMe prototype simulating, verifying structure as described in claim 1, which is characterized in that further include: user's test interface
(7), the interface used for being supplied to user receives the NVMe order for needing to verify.
6. NVMe prototype simulating, verifying structure as claimed in claim 5, which is characterized in that after receiving write order, by a group packet
Module (3) and dsport module (4), are sent to NVMe controller (5), and NVMe controller (5) issues one after receiving write order
Read request by dsport module (4), receives array (14), decoder module (2) and extracts data and printing receives packet letter
It ceases module (10), takes the data to be write to simulation framework memory (1) is inner；Data arrive dsport module (4) by group packet module (3)
And NVMe controller (5), it is sent to simulation RAM (6).
7. NVMe prototype simulating, verifying structure as claimed in claim 5, which is characterized in that after receiving read command, by group
It after packet module (3) and dsport module (4), is sent to NVMe controller (5), NVMe controller (5) is sent out after receiving read command
A write request out takes out data from simulation RAM (6), by dsport module (4), receives array (14), decoder module (2)
And data and printing reception package informatin module (10) are extracted, it is inner to simulation framework memory (1).
8. NVMe prototype simulating, verifying structure as described in claim 1, which is characterized in that the data or order group to be sent
Dress up TLP packet.
9. NVMe prototype simulating, verifying structure as described in claim 1, which is characterized in that further include: need to verify instruction packet
Doorbell instruction is write in the instruction and NVMe for having contained instruction, the BAR initialization of system initialization.
10. NVMe prototype simulating, verifying structure described in claim 1, which is characterized in that simulation framework memory (1) is stored with IO
Instruction queue, to complete instruction queue and management instruction queue.
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