CN109428844B

CN109428844B - Communication device and communication method

Info

Publication number: CN109428844B
Application number: CN201710785235.XA
Authority: CN
Inventors: 谢凯安; 谢依峻
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2017-09-04
Filing date: 2017-09-04
Publication date: 2021-07-16
Anticipated expiration: 2037-09-04
Also published as: CN109428844A

Abstract

A communication device comprises an input end, an output end and an interference reduction module. The interference reduction module is coupled between the input end and the output end. The input receives a time-varying data signal. The interference reduction module obtains first local data of the data signal at a first time and generates a first offset result and a second offset result according to the first local data. The interference reduction module obtains second local data of the data signal at a second time. The interference reduction module selects one of the first offset result and the second offset result as a selection result according to the second local data, and transmits the selection result to the output end.

Description

Communication device and communication method

Technical Field

The present disclosure relates to a communication apparatus and a communication method for receiving a signal, and more particularly, to an apparatus and a method for reducing interference in a communication system.

Background

In digital communication systems, Inter Symbol Interference (ISI) has been a common problem in signal transmission, and simply, adjacent signal symbols affect each other to cause so-called inter-symbol interference.

In the application of high-speed transmission interface, if the characteristics of the transmission channel (such as the length, resistance, inductance, etc.) can be known in advance, the compensation method can be used to prevent the inter-symbol interference. However, since the channel characteristics of the wire cannot be known in advance or simply, it is difficult to compensate effectively, so that the transmitter and the receiver cannot communicate effectively, thereby greatly affecting the signal quality.

Disclosure of Invention

The present disclosure provides an apparatus for a communication system, the apparatus comprising an input, an output, and an interference reduction module. The interference reduction module is coupled between the input end and the output end. The input receives a time-varying data signal. The interference reduction module is used for obtaining first local data of the data signal at a first time and generating a first offset result and a second offset result according to the first local data. The interference reduction module is further configured to obtain second local data of the data signal at a second time. In addition, the interference reduction module selects one of the first offset result and the second offset result as a selection result according to the second local data and transmits the selection result to the output end.

The present disclosure also provides a communication method for a communication system. The method comprises the following steps: receiving a time-varying data signal; obtaining first local data of a data signal at a first time, and generating a first offset result and a second offset result according to the first local data; obtaining second local data of the data signal at a second time; and selecting one of the first offset result and the second offset result as a selection result according to the second local data and transmitting the selection result to the output end.

Drawings

The description of the drawings in the specification is as follows:

fig. 1 is a schematic diagram of a communication system according to an embodiment of the present disclosure.

Fig. 2 is a functional block diagram of a communication device according to an embodiment of the present disclosure.

Fig. 3A is a circuit architecture diagram of the communication device of fig. 2 in an embodiment.

Fig. 3B shows a circuit architecture diagram of the communication device of fig. 2 in an embodiment.

Fig. 4 is a flow chart illustrating a communication method according to an embodiment of the present disclosure.

Fig. 5 is a schematic diagram of a data signal processed by an interference reduction module according to an embodiment of the disclosure.

Fig. 6 is a functional block diagram of a communication device according to an embodiment of the present disclosure.

Fig. 7 is a flow chart illustrating a communication method according to an embodiment of the present disclosure.

Fig. 8 is a signal diagram illustrating a data signal processed by the communication method of fig. 7 according to an embodiment of the present disclosure.

Fig. 9 is a functional block diagram of a communication device according to an embodiment of the present disclosure.

Description of reference numerals:

100: communication device REF 1: first reference signal

110: input terminal REF 2: second reference signal

120: interference reduction module S0: selection signal

121-124: offset module S1: selection signal

125: processing modules S402-S410: step (ii) of

126: total adders RA 1-RA 3: offset result

127: multiplexers RB 1-RB 3: offset result

128: decision feedback equalizer RC1, RC 2: offset result

130: output terminals RD1, RD 2: offset result

200: communication systems aRA1, aRB 1: analog offset signal

210: signal transmission sources aRC1, aRD 1: analog offset signal

DIN: data signal T1: first time

And (D) is as follows: digital signal T2: the second time

310 a: voltage level conversion circuit T3: the third time

310 b: voltage level conversion circuit VT 1: local data

320a,320 b: comparator VT 2: local data

330a,330 b: retarder VT 3: local data

340: comparators S702-S710: step (ii) of

350: delay device

REF 0: predetermined value

Detailed Description

Fig. 1 is a schematic diagram of a communication system 200 shown in accordance with an embodiment of the present disclosure. Communication system 200 includes signal source 210 and communication device 100. communication device 100 receives data signal DIN from signal source 210. in one embodiment, data signal DIN may be an analog signal that is time-varying and serialized.

The communication device 100 includes an input 110, an interference reduction module 120, and an output 130. The interference reduction module 120 is coupled between the input terminal 110 and the output terminal 130. The input terminal 110 receives the time-varying data signal DIN, and in one embodiment, the input terminal 110 may include a linear equalizer (not shown) for performing a preliminary processing on the data signal DIN to adjust the intensity gain of the data signal DIN in each frequency band. In one embodiment, the output 130 includes a deserializer (not shown), which deserializes the data signal DIN received by the communication device 100 and outputs the deserialized result to other circuits.

Referring to fig. 2, fig. 2 is a functional block diagram of the communication apparatus 100 according to an embodiment of the disclosure, in which the interference reduction module 120 includes

offset modules

121 and 122, a processing module 125, a total adder 126, and a multiplexer 127. In one embodiment, the data signals DIN transmitted from signal transmission source 210 to communication apparatus 100 may have data levels at different time points that interfere with each other, such as inter-symbol interference, during transmission and reception. In one embodiment, the interference reduction module 120 is used for reducing the interference phenomenon of the data signal DIN between different time points at the receiving end (i.e., the communication device 100).

At a first time, the local data of the data signal DIN at the first time is transmitted to the

offset modules

121 and 122 through the total adder 126. The offset module 121 adds a first offset to the local data of the data signal DIN at the first time to generate an offset result RA1, and the offset module 122 adds a second offset to the local data at the first time to generate an offset result RB 1.

At a second time after the first time, the processing module 125 obtains the local data of the data signal DIN at the second time. In an embodiment, the first time and the second time are separated by one sampling unit time (e.g. 0.5ms,1ms, or determined according to actual circuit requirements), but the disclosure is not limited thereto. At this time, the local data of the data signal DIN at the second time may be different from the local data at the first time, and the local data at the first time and the local data at the second time may have different voltage levels and/or represent the same or different data meanings. In an embodiment, the offset

modules

121 and 122 add a delay of one sampling unit time when generating the offset results RA1 and RB1 according to the local data of the first time, respectively, but the disclosure is not limited thereto.

In one embodiment, the first time and the second time are separated by one sampling unit time, the offset results RA1 and RB1 are delayed by one sampling unit time from the local data of the first time, the processing module 125 outputs the selection signal S0 according to the local data of the second time, and the offset results RA1, RB1 and the selection signal S0 are simultaneously transmitted to the multiplexer 127. The multiplexer 127 selects one of the offset results RA1 and RB1 as the selection result according to the selection signal S0 and transmits the selection result to the output terminal 130. That is, the local data of the data signal DIN at the first time can be adjusted to the offset results RA1 and RB1, respectively, and the offset results RA1 or RB1 are selected according to the local data of the subsequent data signal DIN at the second time. In this way, the input voltage level of the previous (e.g., the first time) data signal DIN can be correspondingly adjusted according to the subsequent (e.g., the second time) data signal DIN. Such adjustments help compensate for interference of a subsequently transmitted symbol with a previously transmitted symbol, i.e., help to reduce preamble ISI.

Fig. 3A shows a circuit architecture diagram of the communication device 100 in fig. 2 in an embodiment, as shown in fig. 3A, the offset module 121 may include a voltage level shifter (level shifter)310a, where the voltage level shifter 310a is configured to shift the local data of the data signal DIN by a first predetermined potential difference, for example, the local data of the data signal DIN at a first time is boosted by a potential difference Vth to serve as the analog offset signal aRA1, where the first predetermined potential difference is + Vth. The potential of the analog offset signal aRA1 is generated to be equal to DIN + Vth. The comparator 320a then compares the analog offset signal aRA1 with a predetermined value REF0 to output a digitized offset signal. Finally, the digitized offset signal is passed through the delay 330a as the candidate offset result RA1 and is sent to the multiplexer 127. In one embodiment, the predetermined value REF0 is a reference value for identifying between a high level (also referred to as logic 1) and a low level (also referred to as logic 0) in the digitized signal, and if the level of the analog offset signal aRA1 is higher than the predetermined value REF0, the offset result RA1 is high (logic 1). If the potential of the analog offset signal aRA1 is lower than the predetermined value REF0, the offset result RA1 is low (logic 0).

The shifting module 122 may include a voltage level shifter 310b, the voltage level shifter 310b is used for shifting the local data of the data signal DIN by a second predetermined potential difference, for example, the local data of the data signal DIN at a first time is reduced by a potential difference Vth, i.e., the second predetermined potential difference is-Vth, to serve as the analog shifting signal aRB 1. The potential of the analog offset signal aRB1 is now equal to DIN-Vth. The comparator 320b then compares the analog offset signal aRB1 with a predetermined value REF0 to output a digitized offset signal. Finally, the digitized offset signal is passed through the delay 330b as the candidate offset result RB1 and is sent to the multiplexer 127.

In some embodiments, the delay time of the

delays

330a and 330b may be one sample unit time or an integer multiple thereof.

In the above embodiment, the offset results RA1 and RB1 respectively boost and reduce two different offset results of the voltage from the original level of the local data of the data signal DIN at the first time, so that the offset result RB1 may be selected when the interference reduction module 120 determines that the local data at the second time may pull up the local data at the first time (i.e., the inter-symbol interference caused by the pull-up on the local data at the first time); conversely, when the interference reduction module 120 determines that the local data at the second time is likely to reduce the local data at the first time (i.e., cause reduced inter-symbol interference to the local data at the first time), the offset result RA1 may be selected. By the above selection, the influence of the local data at the subsequent time on the local data at the previous time can be offset/reduced.

The processing module 125 is coupled to the input terminal 110, and in the embodiment of fig. 3A, the processing module 125 includes a comparator 340 and a delay 350. The multiplexer 127 is coupled to the processing module 125, the offset

modules

121 and 122, and selects one of the offset result RA1 and the offset result RB1 according to the selection signal S0, and outputs the selected result to the output terminal 130.

In some embodiments, the comparator 340 is used to compare the local data with a threshold value to generate the selection signal S0, wherein the threshold value is determined according to the property of the data signal DIN. For example, if the attribute of the data signal DIN corresponds to a binary signal, the threshold value may be set to an average level (e.g., 0V or 0.5V) between a high level and a low level, assuming that the representation of the binary signal is switched between the high level (e.g., 1V) or the low level (e.g., -1V or 0V). In one embodiment, the selection signal S0 causes the multiplexer 127 to output the offset result RA1 when the data signal DIN is smaller than the threshold, and the selection signal S0 causes the multiplexer to output the offset result RB1 when the data signal DIN is larger than the threshold. In another embodiment, the threshold value and the manner of selecting the offset result RA1/RB1 may be determined according to the inter-symbol interference characteristics of the data signal DIN.

In some embodiments, the delay 350 is one sample unit time less delayed than the delay 330a, and if the delay time of the delay 330a in the offset module 121 or the delay 330b in the offset module 122 is N sample unit times, the delay 350 of the processing module 125 has N-1 sample unit times. In addition, in case that N is 1, the delay 350 is set to zero delay, or there is no delay 350 in the processing module 125. The local data of the data signal DIN at the second time passes through the comparator 340 to output the digitized local data, where the digitized local data at the second time forms the selection signal S0 to be input to the multiplexer 127, it should be noted that in fig. 3A, the selection signal S0 is indicated at the output of the delay 350 for convenience of describing the operation of the multiplexer 127 (i.e., timing synchronization).

The decision feedback equalizer 128 is coupled to the processing module 125 and the multiplexer 127 for generating the gain feedback signal according to the local data (e.g., the local signal at the second time) and the selection result. In some embodiments, the dfe 128 generates the gain feedback signal according to the selection signal S0 corresponding to the local data and the selection result. The overall adder 126 is coupled to the input terminal 110, the decision feedback equalizer 128, the offset

modules

121 and 122, and the processing module 125, and receives the gain feedback signal to adjust the local data of the data signal DIN at a subsequent time.

The decision feedback equalizer 128 is used for collecting the level of the data signal DIN from the previous (e.g., second time) data signal DIN, and correspondingly feeding back the level to the overall adder 126 to adjust the input voltage level of the subsequent (e.g., third time) data signal DIN. Such adjustments help compensate for interference of a previously transmitted symbol with a subsequently transmitted symbol, i.e., help to reduce post-driver inter-symbol interference (postcursor ISI).

Referring to fig. 2, 3A, 4 and 5 together, fig. 4 is a flowchart illustrating a communication method 400 according to an embodiment of the disclosure, and fig. 5 is a signal diagram illustrating a data signal DIN processed by the interference reduction module 120 according to an embodiment of the disclosure. The communication method 400 may be implemented by the following steps. In step S402, the data signal DIN varying with time is received. In step S404, the local data VT1 of the data signal DIN at the first time T1 is obtained, the shift module 121 generates the shift result RA1 according to the local data VT1, and the shift module 122 generates the shift result RB1 according to the local data VT 1.

As shown in FIG. 5, at a first time T1, the local data VT1 of the data signal DIN at a first time T1 is sent to the offset

modules

121 and 122 by the global adder 126. The shift module 121 adds a first shift (the first shift is + Vth in an embodiment) to the local data VT1 of the data signal DIN at a first time T1 to generate an analog shift signal aRA1, and the shift module 122 is used for adding a second shift (the second shift is-Vth in an embodiment) to the local data VT1 to generate an analog shift signal aRB 1. The analog offset signals aRA1 and aRB1 in FIG. 5 are respectively passed through the

comparators

320a and 320b in FIG. 3A and processed by the

delays

330a and 330b to form digitized offset results RA1 and RB 1.

In step S406, the local data VT2 of the data signal DIN at the second time T2 is obtained at a second time T2 after the first time T1.

In step S408, one of the shift results RA1 and RB1 is selected as the selection result according to the local data VT2 and is transmitted to the output terminal 130, at which time the output terminal 130 regards one of the shift results RA1 and RB1 as the data of the data signal DIN at the first time T1.

In one embodiment, the interference reduction module 120 further includes a global adder 126, and in step S410, the decision feedback equalizer 128 is configured to generate a gain feedback signal according to the local data VT2 and the selection result of the multiplexer 127, and feed the gain feedback signal back to the global adder 126 to adjust subsequent data, such as the local data VT3 at the third time T3. In some embodiments, the decision feedback equalizer 128 generates the gain feedback signal according to the selection signal S0 (corresponding to the local data VT2) and the selection result of the multiplexer 127.

That is, the dfe 128 may generate the gain feedback signal for adjusting subsequent data, such as the local data VT3 at the third time T3, based on the previous time points, such as the received selection signal S0 (corresponding to the second time T2) and the selection result (corresponding to the first time T1). Thus, the decision feedback equalizer 128 may be used to reduce the back-drive inter-symbol interference.

The first and second offsets may be respectively voltage values of the same magnitude but opposite positive and negative, e.g., the first offset may be a positive potential difference + Vth and the second offset may be a negative potential difference-Vth. The foregoing is merely an example, and the disclosure is not limited thereto. The offset of the data signal DIN to generate the offset results RA1 and RB1, and the determination of the signals at subsequent times, reduces the effects of channel noise effects, thereby compensating for the effects of inter-symbol interference on signal quality. In one embodiment, the absolute value of the potential difference Vth used for the first and second offsets can be obtained by a least mean square algorithm, for example, but the disclosure is not limited thereto.

It should be noted that the interference reduction module 120 compensates for the time, that is, the interference reduction module 120 may repeat steps S404 to S410 in fig. 4 in a loop. For the second time T2, in step S404, the local data VT2 of the data signal DIN at the second time T2 is obtained, and the local data VT2 of the data signal DIN at the second time T2 is transferred to the

shift modules

121 and 122 by the global adder 126. The shift module 121 is used for adding a first shift (in one embodiment, + Vth) to the local data VT2 of the data signal DIN at a second time T2 to generate a shift result RA2 (corresponding to aRA2), and the shift module 122 is used for adding a second shift (in one embodiment, -Vth) to the local data VT2 at the second time to generate a shift result RB2 (corresponding to aRB 2).

At a third time T3 after the second time T2, in step S406, the local data VT3 of the data signal DIN at the third time T3 is obtained. In step S408, one of the shift results RA2 and RB2 is selected as the selection result according to the local data VT3 and is transmitted to the output terminal 130, at which time the output terminal 130 regards one of the shift results RA2 and RB2 as the data of the data signal DIN at the second time T2.

In step S410, the dfe 128 receives the local data VT3 and the selection result (offset result RA2 or RB2) of the multiplexer 127, and generates a gain feedback signal according to the local data VT3 and the selection result. The interference reduction module 120 further comprises a total adder 126, which receives the gain feedback signal and adjusts subsequent data (e.g., fourth local data (not shown) or local data sampled at a later time) by feeding back the data to the total adder 126.

Referring to fig. 3B, fig. 3B shows a circuit architecture diagram of the communication device 100 of fig. 2 in an embodiment. The above-mentioned communication method 400 can be implemented by using the circuit architecture diagram of fig. 3B, and can also achieve the similar effect as fig. 3A. In contrast to FIG. 3A, the voltage level converting circuits 310a and 310B in the offset

modules

121 and 122 in FIG. 3B add the first offset and the second offset to the predetermined value REF0 to generate the reference signals REF1 and REF2, respectively. The reference signals REF1 and REF2 are then respectively passed through the

comparators

320a,320b to be compared with the local data VT1 of the data signal DIN, thereby generating digitized offset signals. Finally, the digitized offset signal is passed through

delays

330a and 330b to generate offset results RA1 and RB1 to multiplexer 127, and fed into decision feedback equalizer 128 to adjust the local data sampled at a later time. In the embodiment of FIG. 3B, the first offset and the second offset are applied to the predetermined value REF0 to generate different reference signals REF1 (equal to REF0+ Vth) and REF2 (equal to REF0-Vth), respectively. The same local data VT1 is compared with different reference signals REF1 and REF2 to obtain digitized shift results RA1 and RB 1.

Referring to fig. 6-8 together, fig. 6 is a functional diagram of a communication device according to another embodiment of the present disclosure. The interference reduction module 120 includes offset

modules

123 and 124 in addition to the offset

modules

121 and 122 shown in fig. 2 and 3A or 3B. FIG. 7 is a flow chart of a method shown in accordance with an embodiment of the present disclosure. Fig. 8 is a signal diagram illustrating a data signal processed by the method of fig. 7 according to an embodiment of the present disclosure.

In step S702, a time-varying data signal DIN is received.

In step S704, the local data VT1 of the data signal DIN at the first time T1 is obtained, and the shift modules 121-124 respectively generate shift results RA1, RB1, RC1 and RD1 according to the local data VT 1. Further, the offset modules 121-124 respectively provide different offsets to the local data VT1, i.e., the voltage level conversion circuits 310 a-310 d of the offset modules 121-124 respectively generate the analog offset signals aRA1, aRB1, aRC1 and aRD1, and the comparators 320 a-320 d and the delays 330 a-330 d generate the offset results RA1, RB1, RC1 and RD 1. As shown in fig. 4, in one embodiment, in step S704, the analog offset signals aRA1, aRB1, aRC1 and aRD1 with different degrees of offset are added and compared with predetermined values to obtain offset results RA1, RB1, RC1 and RD 1. In another embodiment, the local data VT1 is compared with different shifted predetermined values to generate the shift results RA1, RB1, RC1 and RD1 by adding different shift voltages to the predetermined values, respectively.

In an embodiment of fig. 8, the analog offset signal aRA1 is an offset voltage for increasing the local data VT1 by a certain amount, the analog offset signal aRC1 is an offset voltage for increasing the local data VT1 by two times, the analog offset signal aRB1 is an offset voltage for decreasing the local data VT1 by a certain amount, and the analog offset signal aRD1 is an offset voltage for decreasing the local data VT1 by two times, but the disclosure is not limited thereto.

In some embodiments, the degree and direction of the offsets of the analog offset signals aRA1, aRB1, aRC1, and aRD1 may be determined according to the interference-based characteristics of the data signal DIN. Assuming that the leading-symbol interference characteristic of the data signal DIN is significantly inclined to the leading data signal leading to the reduction of the previous data signal, the offset directions of the analog offset signals aRA1, aRB1, aRC1 and aRD1 may all be raised offset voltages (respectively raised offset voltages of different degrees), or a majority of the analog offset signals aRA1, aRB1 and aRC1 are raised offset voltages and a minority of the analog offset signals aRD1 are reduced offset voltages. Conversely, assuming that the leading-symbol interference characteristic of the data signal DIN is significantly biased towards the leading data signal that will cause the leading data signal to increase, the offset directions of the analog offset signals aRA1, aRB1, aRC1 and aRD1 may all be reduced offset voltages (respectively reduced offset voltages of different degrees), or a majority of the analog offset signals aRA1, aRB1 and aRC1 are reduced offset voltages and a minority of the analog offset signals aRD1 are increased offset voltages.

In step S706, the processing module 125 of the interference reduction module 120 further obtains the local data VT2 of the data signal DIN at the second time T2 and the local data VT3 at the third time T3, thereby generating the selection signals S0 and S1 for the decision of the multiplexer 127. In some embodiments, the processing module 125 may compare the local data VT2 with a first threshold to generate the select signal S0, and compare the local data VT3 with a second threshold to generate the select signal S1, wherein the first and second thresholds are the same or different values depending on the property of the data signal DIN.

In step S708, the multiplexer 127 of the interference reduction module 120 is further configured to select one of the shift results RA1, RB1, RC1 and RD1 corresponding to the local data VT1 as a selection result to be transmitted to the output terminal 130 according to the selection signals S0 and S1.

In one embodiment, the offset

modules

123 and 124 may be implemented using the same architecture as the offset module 121. The rest of the operations in FIG. 6 are similar to those in FIG. 2, and thus are not repeated.

In step S710, the dfe 128 generates a gain feedback signal according to the selection result, the local data VT2 and the local data VT3, thereby adjusting the subsequent data. In some embodiments, the decision feedback equalizer 128 may receive the selection signal S0 (corresponding to the local data VT2), the selection signal S1 (corresponding to the local data VT3), and the selection result, thereby generating the gain feedback signal.

Fig. 9 is a functional block diagram illustrating a communication device 100 according to an embodiment of the present disclosure. FIG. 9 is an expanded view of FIGS. 2 and 6 of the present disclosure having a2^NA general example of the offset module, wherein N is a positive integer. The structure and operation mode of fig. 9 are similar to those of fig. 2 and 6, and therefore are not described in detail.

Although specific embodiments of the present disclosure have been disclosed in the foregoing detailed description, the present disclosure is not limited thereto, and it will be apparent to those skilled in the art from this disclosure that various changes and modifications can be made without departing from the spirit and scope of the disclosure, and therefore, the scope of the disclosure is to be determined by the appended claims.

Claims

1. A communication device, comprising:

an input terminal for receiving a data signal varying with time;

an output terminal; and

a interference reduction module coupled between the input terminal and the output terminal, the interference reduction module being configured to obtain a first local data of the data signal at a first time and generate a first offset result and a second offset result according to the first local data, the interference reduction module being further configured to obtain a second local data of the data signal at a second time, and the interference reduction module selecting one of the first offset result and the second offset result as a selection result according to the second local data and transmitting the selection result to the output terminal;

wherein the interference reduction module further comprises:

a first offset module for adding a first offset to the first local data to generate a first offset result; and

a second offset module for adding a second offset to the first local data to generate a second offset result;

a processing module, coupled to the input terminal, for obtaining the second local data of the data signal at the second time; and

a multiplexer, coupled to the processing module, the first shift module and the second shift module, for selecting the first shift result and the second shift result according to the second local data and outputting the selected result.

2. The communication device of claim 1, wherein the first and second shifting modules each comprise:

a voltage level conversion circuit for adding the first local data to the first offset or the second offset;

a comparator for comparing the shifted first local data with a predetermined value to generate a digitized shift signal; and

a delay device for delaying the digitized offset signal and generating the first offset result or the second offset result.

3. The communication device of claim 1, wherein the first and second shifting modules each comprise:

a voltage level shifter for adding a predetermined value to the first offset or the second offset;

a comparator for comparing the first local data with the shifted predetermined value to generate a digitized shift signal; and

4. The communication device of claim 1, wherein the interference reduction module further comprises:

a decision feedback equalizer coupled to the processing module and the multiplexer for receiving the second local data and the selection result and generating a gain feedback signal according to the second local data and the selection result; and

a total adder, coupled to the input terminal, the decision feedback equalizer, the first offset module, the second offset module, and the processing module, for receiving the gain feedback signal to adjust a third local data of the data signal at a third time.

5. The communications apparatus of claim 1, wherein the interference reduction module is further configured to generate a third offset result and a fourth offset result according to the first local data, the interference reduction module is further configured to obtain a third local data of the data signal at a third time, and the interference reduction module is further configured to select one of the first offset result, the second offset result, the third offset result and the fourth offset result as a selection result to be transmitted to the output terminal according to the second local data and the third local data.

6. A method of communication, comprising:

receiving a data signal that varies with time;

obtaining a first local data of the data signal at a first time, adding a first offset to the first local data to generate a first offset result, and adding a second offset to the first local data to generate a second offset result;

obtaining a second local data of the data signal at a second time; and

selecting one of the first offset result and the second offset result as a selection result according to the second local data and transmitting the selection result to an output terminal.

7. The communication method according to claim 6, wherein the first local data added with the first offset is compared with a predetermined value to obtain the first offset result, the first local data added with the second offset is compared with the predetermined value to obtain the second offset result, and the second local data not offset is compared with the predetermined value.