CN109428480B

CN109428480B - Low-current low-noise charge pump circuit and frequency synthesizer

Info

Publication number: CN109428480B
Application number: CN201710778829.8A
Authority: CN
Inventors: 陈瑞斌
Original assignee: Holtek Semiconductor Inc
Current assignee: Holtek Semiconductor Inc
Priority date: 2017-08-29
Filing date: 2017-09-01
Publication date: 2020-07-24
Anticipated expiration: 2037-09-01
Also published as: CN109428480A; TWI645660B; TW201914188A

Abstract

A low-current and low-noise charge pump circuit comprises an output capacitor, a first current source unit, a second current source unit, a charging switch, a discharging switch and a bypass switch. The charging switch is turned on in response to the switching signal in the on-period of the switching signal to charge the output capacitor with the charging current from the first current source unit. The discharge switch responds to the switch signal and is conducted in the off interval of the switch signal to enable the output capacitor to discharge through the second current source unit. The switch signal controls the charging switch to be switched on before and after the charging switch is switched on in the switching-on interval, and the bypass signal controls the bypass switch to be switched on so that the charging current flows to the grounding end. The bypass signal controls the bypass switch to be not conducted during the period that the switch signal controls the charging switch to be conducted in the conducting interval.

Description

Low-current low-noise charge pump circuit and frequency synthesizer

Technical Field

The present invention relates to a charge pump circuit, and more particularly, to a low current and low noise charge pump circuit and a frequency synthesizer.

Background

Frequency synthesizers are commonly found in wireless communication systems. Such frequency synthesizers supply high frequency signals within the determined frequency band to cover a telecommunications band, such as the U.S. ISM band (902 to 928 MHz).

In general, a frequency synthesizer is operated in which a phase detector detects the phase difference between the crystal oscillator output and the down-converted vco output. The phase difference signal is transmitted to the charge pump to control the charge pump to charge and discharge the capacitor. The output end of the capacitor is filtered to form a voltage signal so as to further control the voltage-controlled oscillator. Thus forming a loop to provide a stable frequency.

In the early phase detector control to drive the switch charge pump circuit, the whole charge pump circuit is turned off. This results in a transient voltage being formed at the drain of the current source. Further, the jitter of the current source output causes the non-linear relationship between the phase and the output current. This non-linearity then causes the high frequency noise of the charge pump circuit to fold back into the low frequency.

Therefore, there are currently widely used charge pump circuits that bypass the amplifier supply voltage (as shown in fig. 1A). When the charge pump 900 charges and discharges the capacitor 901, the waveform of the current source is shown in fig. 1B. The waveform of the output current of the capacitor is shown as 1C. When the charge pump 900 is not charging or discharging the capacitor 901, the bypass is turned on. That is, when the switch of the charge pump 900 is switched such that the current source does not charge or discharge the capacitor 901, the current of the current source changes to the bypass path. Therefore, the current output by the current source can be kept flowing, and the instantaneous voltage generated at the drain electrode of the current source is avoided. However, when the frequency synthesizer is locked, the charge pump 900 only charges and discharges the capacitor 901 for a short time, and the charge and discharge time only occupies a small portion of the crystal oscillation period. This causes the current of the current source to be discarded through the bypass path most of the time. In other words, such a design would result in unnecessary energy waste.

In view of the above, it is necessary to provide a feasible solution to solve the foregoing problems, so as to reduce unnecessary waste.

Disclosure of Invention

An embodiment of the invention provides a low-current and low-noise charge pump circuit, which includes an output capacitor, a first current source unit, a second current source unit, a charge switch, a discharge switch, and a bypass switch. The first current source unit provides a charging current according to a rated voltage. The second current source unit is coupled between the output capacitor and the ground terminal. The charging switch is coupled between the output capacitor and the first current source unit and controlled by a switching signal. The charging switch receives the switching signal and is conducted in the conducting interval of the switching signal to enable the charging current to charge the output capacitor. The discharge switch is coupled between the output capacitor and the second current source unit and controlled by a switching signal. The discharge switch receives the switching signal and is switched on in an off interval of the switching signal to discharge the output capacitor. The bypass switch is coupled between the first current source unit and the ground terminal and controlled by a bypass signal. Before and after the switch signal controls the charging switch to be conducted in the conducting interval, the bypass signal controls the bypass switch to be conducted so that the charging current flows to the grounding end. And the bypass signal controls the bypass switch not to be conducted when the switching signal controls the conduction of the charging switch in the conduction interval.

Another embodiment of the present invention provides a frequency synthesizer, which includes a charge pump circuit, a phase frequency detection circuit, a phase shift pwm circuit, and a logic operation circuit. The charge pump circuit comprises an output capacitor, a first current source unit, a second current source unit, a charging switch, a discharging switch and a bypass switch. The first current source unit provides a charging current according to a rated voltage. The second current source unit is coupled between the output capacitor and the ground terminal. The charging switch is coupled between the output capacitor and the first current source unit and controlled by a switching signal. The charging switch receives the switching signal and is conducted in the conducting interval of the switching signal to enable the charging current to charge the output capacitor. The discharge switch is coupled between the output capacitor and the second current source unit and controlled by a switching signal. The discharge switch receives the switching signal and is switched on in an off interval of the switching signal to discharge the output capacitor. The bypass switch is coupled between the first current source unit and the ground terminal and controlled by a bypass signal. The phase frequency detection circuit is coupled with the charging switch and the discharging switch. The phase frequency detection circuit outputs a switching signal according to the frequency signal and the frequency division signal. The phase-shift pulse width modulation circuit outputs a phase-shift pulse signal according to the frequency signal. The time of the phase-shifting pulse signal at high level covers the conducting interval of the switch signal. The logic operation circuit is coupled among the phase frequency detection circuit, the phase shift circuit and the bypass switch. The logic operation circuit generates a bypass signal according to the switching signal and the phase-shift pulse signal.

According to the foregoing embodiment, the charge pump circuit is turned off when not in use, and before the charge/discharge switch is switched to be conductive and before the charge/discharge switch is switched to be non-conductive, the bypass switch is switched to be non-conductive after the drain of the current source unit reaches the steady-state voltage by the pilot-on bypass switch, and the charge/discharge switch is switched. Therefore, the steady-state voltage between the current source unit and the charge and discharge switch can be maintained. And the voltage generated by the accumulation of the charging current between the first current source unit and the charging switch can be avoided. And also reduces the current discarded through the bypass switch to save current. In addition, a linear relation between the phase and the output current can be kept to avoid high-frequency noise of the charge pump circuit from folding to low frequency. Furthermore, when applied to a frequency synthesizer, it does not interfere with the frequency synthesizer operation.

Drawings

FIG. 1A is a schematic diagram of a prior art architecture.

Fig. 1B is a waveform diagram of an output current of a current source of the prior art.

Fig. 1C is a waveform diagram of an output current of a prior art capacitor.

Fig. 2 is a schematic diagram of an embodiment of a charge pump circuit according to the present invention.

FIG. 3A is a waveform diagram of an embodiment of the clock signal of FIG. 2.

FIG. 3B is a waveform diagram of an embodiment of the switching signal of FIG. 2.

FIG. 3C is a waveform diagram of one embodiment of the bypass signal of FIG. 2.

FIG. 3D is a waveform diagram of an embodiment of the phase shifted pulse signal of FIG. 2.

Fig. 3E is a waveform diagram of an embodiment of the output voltage of the first current source unit of fig. 2.

FIG. 3F is a waveform diagram of an embodiment of the output voltage of the output capacitor of FIG. 2.

Fig. 3G is a waveform diagram of an embodiment of the output current of the first current source unit of fig. 2.

FIG. 3H is a waveform diagram of an embodiment of an output current of the output capacitor of FIG. 2.

Fig. 4 is a schematic diagram of another embodiment of a charge pump circuit according to the present invention.

Wherein the reference numerals are:

10 output capacitor 20 first current source unit

30 second current source unit 40 charging switch

50 discharge switch 60 bypass switch

61 bypass switch 62 amplifier

70 phase frequency detection circuit 80 phase shift type pulse width modulation circuit

90 logic operation circuit 900 charge pump

901 capacitor SS-U, SS-D, S-switch switching signal

SB-U, SB-D, S-bypass signal

Conduction intervals of t11, t21 and t22

t12, t23, t24 break interval

S-clk frequency signal

S-div frequency divided signal

S-shift phase shift pulse signal

Vi1, Vcout output voltage

Ii1, Icout output current

Detailed Description

Fig. 2 is a schematic diagram of an embodiment of a charge pump circuit according to the present invention. Referring to fig. 2, the charge pump circuit includes: the circuit comprises an output capacitor 10, a first current source unit 20, a second current source unit 30, a charging switch 40, a discharging switch 50 and a bypass switch 60. The charging switch 40 is coupled between the first current source unit 20 and the output capacitor 10. The discharge switch 50 is coupled between the second current source unit 30 and the output capacitor 10. The bypass switch 60 is coupled between the first current source unit 20 and the ground. The first current source unit 20 is coupled to the charge switch 40 and the bypass switch 60. The second current source unit 30 is coupled between the discharge switch 50 and the ground.

In one embodiment, the other end of the first current source unit 20 opposite to the charging switch 40 is coupled to a rated voltage circuit (which provides a rated voltage). That is, the input terminal of the first current source unit 20 is coupled to the rated voltage circuit and receives the rated voltage supplied by the rated voltage circuit. The output terminal of the first current source unit 20 is coupled to the first terminal of the charging switch 40 and to the first terminal of the bypass switch 60. A second terminal of the charge switch 40 is coupled to the output capacitor 10. The first current source unit 20 is used to provide a charging current with a fixed value according to a rated voltage, and the charging current can charge the output capacitor 10 through the charging switch 40. Wherein the rated voltage is a fixed value.

In one embodiment, the other end of the second current source unit 30 opposite to the discharge switch 50 is coupled to the ground terminal. That is, the input terminal of the second current source unit 30 is coupled to the first terminal of the discharge switch 50. The output terminal of the second current source unit 30 is coupled to the ground terminal. A second terminal of the discharge switch 50 is coupled to the output capacitor 10. When the discharge switch 50 is turned on, the output capacitor 10 can discharge with a constant discharge current through the discharge switch 50 and the second current source unit 30. Here, the charge switch 40 and the discharge switch 50 are not turned on at the same time.

The current values of the charging current and the discharging current may be the same or different, but the current values of the charging current and the discharging current are not limited in the present invention.

In one embodiment, the switch signal SS-U or SS-D (hereinafter referred to as S-switch) has an ON interval and an OFF interval.

The control terminal of the charging switch 40 receives the switching signal SS-U, and the charging switch 40 is turned on at the conducting interval t11 according to the switching signal SS-U, so that the charging current charges the output capacitor 10 through the charging switch 40. In other words, the charging switch 40 is non-conductive in response to the switching signal SS-U at the off interval t 12.

The control terminal of the discharging switch 50 receives the switching signal SS-D, and the discharging switch 50 is turned on in the conducting interval according to the switching signal SS-D, so that the output capacitor 10 is discharged at the rated current value (discharging current) of the second current source unit 30. In other words, the discharge switch 50 is non-conductive in response to the switching signal SS-U during the off period.

In one embodiment, the time when the switch signal S-switch is maintained at the high voltage level is an ON interval, and the time when the switch signal S-switch is maintained at the low voltage level is an OFF interval. In other words, when the control terminal of the charging switch 40 receives the switching signal SS-U with a high voltage level, the charging switch 40 is switched to be on, and the charging switch 40 maintains the on state during the period (i.e., the on period) when the switching signal SS-U is maintained at the high voltage level. When the charging switch 40 is turned on, the charging current outputted by the first current source unit 20 flows through the charging switch 40 and then flows to the output capacitor 10 to charge the output capacitor 10.

Similarly, when the control terminal of the discharging switch 50 receives the switching signal SS-D at the high voltage level, the discharging switch 50 is switched on, and the discharging switch 50 maintains the conducting state during the period (i.e., the conducting period) when the switching signal SS-D is maintained at the high voltage level. When the discharge switch 50 is turned on, the output capacitor 10 is coupled to the second current source unit 30 through the discharge switch 50, and is coupled to the ground through the discharge switch 50 and the second current source unit 30, so as to discharge at the rated current value (discharge current) of the second current source unit 30.

In some embodiments, the charging switch 40 and the discharging switch 50 may be NMOS, PMOS, CMOS, transistor, or other switching elements, respectively, but the invention is not limited thereto.

For example, if the charge switch 40 is a MOS switch device, the charge switch 40 has a gate, a source and a drain. The source is connected to the rated voltage circuit to receive the rated voltage. The drain is connected to the charge switch 40. The grid receives the switch signal S-switch, and the source and the drain can be conducted or not conducted according to the switch signal S-switch.

In one embodiment, the bypass signal S-bypass (SB-D or SB-U) has a conducting interval and a breaking interval.

In one embodiment, the control terminal of the bypass switch 60 receives a bypass signal SB-D, and the bypass switch 60 is turned on or off according to the bypass signal SB-D. In other words, the bypass switch 60 is turned on in response to the bypass signal SB-D during the on period of the bypass signal SB-D, and the bypass switch 60 is turned off in response to the bypass signal SB-U during the off period of the bypass signal SB-D. When the bypass switch 60 is turned on, the charging current provided by the first current source unit 20 can flow to the ground terminal through the bypass switch 60.

Here, the bypass switch 60 is turned on by the bypass signal SB-D before the charging switch 40 is turned on by the switching signal SS-U and after the charging switch 40 is switched from on to off by the switching signal SS-U. While the charge switch 40 is turned on by the switch signal SS-U, the bypass switch 60 is turned off by the bypass signal SB-U. In other words, before and after the conduction interval of the switching signal SS-U occurs, the bypass signal SB-D occurs for a predetermined time conduction interval. While the on-period of the switching signal SS-U occurs, the off-period of the bypass signal SB-D occurs. This prevents the charge pump circuit from accumulating the generated voltage between the first current source unit 20 and the charge switch 40 due to the charge current. And also reduces the current discarded through the bypass switch 60 to save current and also maintains a linear relationship between phase and output current to avoid high frequency noise of the charge pump circuit folding to low frequencies.

In some embodiments, the charge pump circuit may further include another bypass switch 61. The bypass switch 61 couples the discharge switch 50 and the second current source unit 30. The bypass switch 61 is turned on or off according to the bypass signal SB-D. Here, the bypass switch 60 and the bypass switch 61 are not turned on at the same time.

Here, bypass switch 61 is turned on by bypass signal SB-U before discharge switch 50 is turned on by switching signal SS-D and after discharge switch 50 is switched from on to off by switching signal SS-D. While the discharge switch 50 is turned on by the switch signal SS-D, the bypass switch 61 is turned off by the bypass signal SB-D. This allows the charge pump circuit not to accumulate voltage between the second current source unit 30 and the discharge switch 50. And the linear relation between the phase and the output current can be kept, and the problem of high-frequency noise folding can be avoided.

In some embodiments, the bypass switches 60, 61 may be NMOS, PMOS, CMOS, transistor, etc. switch elements, but the invention is not limited thereto. FIG. 3A is a waveform diagram of an embodiment of the switch signal S-switch of FIG. 2. Referring to FIG. 3A, the switch signal S-switch includes an ON interval t11 and an OFF interval t 12. Here, the switching signal S-switch is at a high potential during the on period t11, and the switching signal S-switch is about 1 volt (V) as shown in fig. 3A. The switching signal S-switch is at a low potential during the off interval t12, and is about 0V as shown in fig. 3B.

FIG. 3B is a waveform diagram of one embodiment of the bypass signal S-bypass of FIG. 2. Referring to FIG. 3B, the bypass signal S-bypass includes on-intervals t21, t22 and off-intervals t23, t 24. Here, the bypass signal S-bypass is at a high level during the conduction intervals t21 and t22, and the bypass signal S-bypass is about 1 volt (V) as shown in fig. 3B. The bypass signal S-bypass is at a low level during the off-intervals t23 and t24, and the bypass signal S-bypass is about 0V as shown in fig. 3C.

Referring to fig. 3A and 3B, in the on interval t11 of the switch signal S-switch, the switch signal S-switch drives the charge switch 40 (or the discharge switch 50) to be turned on, and the bypass signal S-bypass drives the bypass switch 60 (or 61) to be turned off (i.e. the bypass signal S-bypass is the off interval t 23). That is, the bypass signal S-bypass is pulled high (entering the conducting interval t21) a predetermined time (the time duration of t21) before the switch signal S-switch enters the conducting interval t 11. When the switch signal S-switch enters the conducting interval t11, the bypass signal S-bypass is pulled to the low level (the time boundary between t21 and t 23). And the time length (off interval t23) of the bypass signal S-bypass at the low voltage level is approximately equal to the time length of the on interval t11 of the switch signal S-switch. When the on-period t11 of the switch signal S-switch is over and the switch signal S-switch enters the off-period t12 (the time boundary between t23 and t 12), the bypass signal S-bypass is pulled to the high level (entering the on-period t22) for a predetermined time (the time length of t22) and then pulled back to the low level (the time boundary between t22 and t 24). In other words, the on-interval t21, the off-interval t23 and the on-interval t22 of the bypass signal S-bypass occur sequentially, and the off-interval t23 of the bypass signal S-bypass is substantially synchronized with the on-interval t11 of the switch signal S-switch.

In other words, the on interval t11 of the switch signal S-switch is a time interval with a voltage of 1V as shown in FIG. 3A. At the same time during this time interval (the on interval t11), the bypass signal S-bypass in fig. 3B is at the low level (the off interval t 23). At this time, the charge switch 40 (or the discharge switch 50) is turned on, and the bypass switch 60 (or 61) is not turned on. In a predetermined time before and after the on-period t11 of the switch signal S-switch, i.e., in a predetermined time before and after the time period when the voltage of the switch signal S-switch is 1V, the bypass signal S-bypass is set at a high level (the on-period t21, t 22). At this time, the charge switch 40 (or the discharge switch 50) is not turned on, but the bypass switch 60 (or 61) is turned on, so that the voltage between the current source unit (20 or 30) and the charge and discharge switch (the charge switch 40 or the discharge switch 50) is allowed to flow to the ground. Therefore, before the charging and discharging switch is conducted, the voltage between the current source unit and the charging and discharging switch reaches the steady-state voltage in advance. Further, the high voltage flowing to the output capacitor 10 at the instant when the charge switch 40 is turned on can be prevented. Therefore, the linear relation between the phase and the output current can be kept, and the problem of high-frequency noise folding can be avoided. The time length of the preset time is not limited in the present invention. In addition, the preset time before and after the conducting interval t11 of the switch signal S-switch of the bypass signal S-bypass may be the same (i.e., the time length of the conducting interval t21 is the same as the conducting interval t22) or different (i.e., the time length of the conducting interval t21 is different from the conducting interval t22), which may be adjusted according to the requirement.

In one embodiment, referring back to fig. 2, when the charge pump circuit is applied to the frequency synthesizer, the charge pump circuit is further coupled to the phase frequency detection circuit 70, the phase shift type pwm circuit 80 and the logic operation circuit 90. An output terminal of the phase frequency detection circuit 70 is coupled to an input terminal of the logic operation circuit 90, a control terminal of the charge switch 40, and a control terminal of the discharge switch 50. The input of the phase-shift PWM circuit 80 receives the clock signal S-clk. The output terminal of the phase shift type pulse width modulation circuit 80 is coupled to the input terminal of the logic operation circuit 90. The output terminal of the logic operation circuit 90 is coupled to the control terminal of the bypass switch 60 (and the control terminal of the bypass switch 61).

The phase frequency detection circuit 70 receives the frequency signal S-clk and the frequency divided signal S-div, and outputs a switching signal SS-U (or SS-D) according to the frequency signal S-clk and the frequency divided signal S-div. The phase shift type pulse width modulation circuit 80 receives the clock signal S-clk, and performs phase shift and pulse width modulation on the clock signal S-clk to generate a phase shift pulse signal S-shift. The logic operation circuit 90 generates the bypass signal SB-U (or SB-D) according to the switching signal SS-U (or SS-D) and the phase-shifted pulse signal S-shift.

In one embodiment, the logic operation circuit 90 includes an exclusive-OR gate. The inputs of the XOR gate are coupled to the phase frequency detection circuit 70 and the phase shift pulse width modulation circuit 80, respectively, and receive the switch signal S-switch and the phase shift pulse signal S-shift, respectively. The output terminal of the exclusive or gate is coupled to the control terminal of the bypass switch 60 (and the control terminal of the bypass switch 61), and outputs the bypass signal S-bypass. That is, when the switch signal S-switch and the phase shift pulse signal S-shift have different potentials, the bypass signal S-bypass output by the XOR gate is at a low potential. When the switch signal S-switch and the phase shift pulse signal S-shift are at the same potential, the bypass signal S-bypass output by the exclusive OR gate is at a high potential. Thus, the conduction interval of the switch signal S-switch drives the charging switch 40 to conduct, so that the bypass switch 60 is not conducted.

For example, when the charge pump circuit employs two

bypass switches

60 and 61, the logic operation circuit 90 may utilize two exclusive OR gates to generate the bypass signal SB-U, SB-D. In other words, one of the XOR gates receives the switch signal SS-U and the phase-shifted pulse signal S-shift and outputs the bypass signal SB-U, and the other of the XOR gates receives the switch signal SS-D and the phase-shifted pulse signal S-shift and outputs the bypass signal SB-D.

In some embodiments, the clock signal S-clk can be generated by an oscillation circuit (not shown). The frequency dividing signal S-div can be generated by a frequency dividing circuit (not shown).

FIG. 3C is a waveform diagram of an embodiment of the clock signal S-clk of FIG. 2. Referring to FIG. 3C, the phase frequency detection circuit 70 performs phase detection on the divided frequency signal S-div by using the frequency signal S-clk as a reference signal, and generates the corresponding switch signal SS-U or SS-D when the divided frequency signal S-div is not synchronized with the frequency signal S-clk. In this embodiment, the clock signal S-clk has about 50% duty cycle.

Referring to fig. 3A to 3C, when the phase frequency detecting circuit 70 detects that the clock signal S-clk leads the divided clock signal S-div, the phase frequency detecting circuit 70 outputs the switching signal SS-U at a high voltage (conducting interval t11) until the clock signal S-clk is synchronized with the divided clock signal S-div, and does not output the switching signal SS-D (or maintains the switching signal SS-D at a low voltage). At this time, the switch signal S-switch shown in FIG. 3A is representative of the switch signal SS-U, and the bypass signal S-bypass shown in FIG. 3B is representative of the bypass signal SB-U.

When the phase frequency detecting circuit 70 detects that the frequency-divided signal S-div leads the frequency signal S-clk, the phase frequency detecting circuit 70 outputs the switching signal SS-D at a high voltage level (the conducting interval t11) until the frequency signal S-clk is synchronized with the frequency-divided signal S-div, but does not output the switching signal SS-U (or the switching signal SS-U maintained at a low voltage level). At this time, the switch signal S-switch shown in FIG. 3A is representative of the switch signal SS-D, and the bypass signal S-bypass shown in FIG. 3B is representative of the bypass signal SB-D.

When the phase frequency detecting circuit 70 detects that the frequency signal S-clk is synchronized with the frequency divided signal S-div, the phase frequency detecting circuit 70 does not output the switching signal SS-U, SS-D (or the switching signals SS-U, SS-U, which are both maintained at a low level). At this time, the bypass signals SB-U, SB-D are also all maintained at low levels.

FIG. 3D is a waveform diagram of one embodiment of the phase shifted pulse signal S-shift of FIG. 2. In one embodiment, referring back to fig. 3A to 3D, the phase-shift pwm circuit 80 shifts a phase difference and a pulse width difference of the clock signal S-clk to output the phase-shifted pulse signal S-shift. Here, the time when the phase shift pulse signal S-shift is at the high level covers the on period t11 of the switch signal S-switch. That is, while the phase shift pulse signal S-shift is maintained at the high potential, the ON period t11 of the switch signal S-switch occurs. The on period t11 of the switch signal S-switch is shorter than the period during which the phase shift pulse signal S-shift is maintained at the high potential.

In one embodiment, the period of the phase-shift pulse signal S-shift is equal to the period of the bypass signal S-bypass, and the duration of the high-level period of the phase-shift pulse signal S-shift is substantially equal to the duration of the on-intervals t21, t22 of the bypass signal S-bypass plus the duration of the on-interval t11 of the switch signal S-switch.

Herein, the time length (predetermined time) of the conducting intervals t21 and t22 of the bypass signal S-bypass can be determined by adjusting the time point and the time length of the phase shift pulse signal S-shift at the high level. The time length of the phase-shift pulse signal S-shift at the high level is not limited in the present invention, and can be adjusted according to the requirement.

Fig. 3E is a waveform diagram of an embodiment of the output voltage Vi1 of the first current source unit 20 in fig. 2. Fig. 3F is a waveform diagram of an embodiment of the output voltage Vcout of the output capacitor 10 of fig. 2. Fig. 3G is a waveform diagram of an embodiment of the output current Ii1 of the first current source unit 20 in fig. 2. Fig. 3H is a waveform diagram of an embodiment of the output current Icout of the output capacitor 10 of fig. 2. Referring to fig. 3A to 3H, the bypass switch 60 is driven to be turned on or off by the bypass signal S-bypass, so that the charging current does not accumulate a voltage between the first current source unit 20 and the charging switch 40. And the linear relation between the phase and the output current can be kept, and the problem of high-frequency noise folding can be avoided.

In one embodiment, the charge pump circuit may not employ an amplifier, and the second terminal of the bypass switch 60 is coupled to the ground terminal. Therefore, when the bypass switch 60 is turned on, the charging current provided by the first current source unit 20 can flow to the ground terminal through the bypass switch 60. In addition, when the charge pump circuit is provided with the bypass switch 61, a first terminal of the bypass switch 61 is coupled to the discharge switch 50 and the second current source unit 30, and a second terminal of the bypass switch 61 is coupled to the rated voltage circuit.

In one embodiment, the charge pump circuit may employ an amplifier. Fig. 4 is a schematic diagram of another embodiment of a charge pump circuit according to the present invention. Referring to fig. 4, the charge pump circuit may further include an amplifier 62. An input terminal of the amplifier 62 is coupled to the second terminal of the charge switch 40 and the output capacitor 10. An output of the amplifier 62 is coupled to a second terminal of the bypass switch 60 (and to a second terminal of the further bypass switch 61). That is, the second terminal of the other bypass switch 61 is coupled to both the second terminal of the bypass switch 60 and the output terminal of the amplifier 62. A first terminal of the bypass switch 61 is coupled to the second current source unit 30 and a first terminal of the discharge switch 50. This also allows the bypass switch 61 to be turned on before and after the discharge switch 50 is turned on, and to be turned off during the turning on of the discharge switch 50. The bypass switch 61 is not turned on during the period in which the charge switch 40 is turned on.

According to the above embodiments, the charge pump circuit is turned off when not in use, and then the bypass switch 60 (or 61) is turned on before the charge/discharge switch (the charge switch 40 or the discharge switch 50) is turned on and before the charge/discharge switch is turned off, so that the drain of the current source unit (20 or 30) reaches the steady-state voltage, and then the bypass switch 60 (or 61) is turned off, and the charge/discharge switch is switched. Therefore, the steady-state voltage between the current source unit and the charge and discharge switch can be maintained. It is also possible to prevent the generated voltage from accumulating between the first current source unit 20 and the charge switch 40 due to the charge current. And also reduces the current discarded through the bypass switch 60 (or 61) to save current. In addition, a linear relation between the phase and the output current can be kept to avoid high-frequency noise of the charge pump circuit from folding to low frequency. Furthermore, when applied to a frequency synthesizer, it does not interfere with the frequency synthesizer operation.

Claims

1. A low current, low noise charge pump circuit, comprising:

an output capacitor;

a first current source unit for providing a charging current according to a rated voltage;

a second current source unit coupled between the output capacitor and the ground terminal;

a charging switch coupled between the output capacitor and the first current source unit and controlled by a switching signal, wherein the charging switch receives the switching signal and is turned on in a conducting interval of the switching signal to charge the output capacitor with the charging current;

a discharge switch coupled between the output capacitor and the second current source unit and controlled by the switching signal, wherein the discharge switch receives the switching signal and is turned on in an off interval of the switching signal to discharge the output capacitor; and

a bypass switch coupled between the first current source unit and the ground terminal and controlled by a bypass signal;

before and after the switch signal controls the charging switch to be conducted in the conducting interval, the bypass signal controls the bypass switch to be conducted so that the charging current flows to the grounding terminal; and

during the period that the switch signal controls the charging switch to be conducted in the conducting interval, the bypass signal controls the bypass switch to be not conducted; the switch signal is generated based on a frequency signal and a frequency dividing signal, the bypass signal is generated based on the switch signal and a phase-shifting pulse signal, and a phase difference and a pulse width difference exist between the phase-shifting pulse signal and the frequency signal.

2. The low-current low-noise charge pump circuit of claim 1, further comprising another bypass switch coupled between the discharge switch and the second current source unit.

3. The low current, low noise charge pump circuit of claim 2, further comprising an amplifier having an input coupled to said output capacitor and an output coupled between said bypass switch and said another bypass switch.

4. The low current, low noise charge pump circuit of claim 1, wherein the time that the phase-shifted pulse signal is at the high level covers the on-state of the switch signal.

5. The low-current low-noise charge pump circuit of claim 4, wherein the period of the phase-shifted pulse signal is equal to the period of the bypass signal, and the time that the phase-shifted pulse signal is at the high level is equal to the sum of the time that the bypass signal is at the high level and the on-period of the switch signal.

6. The low current, low noise charge pump circuit of claim 5, further comprising a logic operation circuit coupled to said bypass switch, said logic operation circuit receiving said phase shifted pulse signal and said switch signal and generating said bypass signal according to said switch signal and said phase shifted pulse signal.

7. The low-current low-noise charge pump circuit of claim 6, wherein the logic operation circuit comprises an exclusive-or gate, an input terminal of the exclusive-or gate receives the switching signal and the phase-shifted pulse signal, and an output terminal of the exclusive-or gate outputs the bypass signal.

8. A frequency synthesizer, comprising:

a low current, low noise charge pump circuit as claimed in any one of claims 1 to 3;

a phase frequency detection circuit coupled to the charge switch and the discharge switch for outputting the switch signal according to a frequency signal and a frequency-divided signal;

a phase-shift pulse width modulation circuit, outputting a phase-shift pulse signal according to the frequency signal, wherein the time of the phase-shift pulse signal at high potential covers the conducting interval of the switch signal; and

a logic operation circuit coupled between the phase frequency detection circuit, the phase-shift pulse width modulation circuit and the bypass switch, the logic operation circuit generating the bypass signal according to the switch signal and the phase-shift pulse signal.

9. The frequency synthesizer of claim 8, wherein the period of the phase-shifted pulse signal is equal to the period of the bypass signal, and the time that the phase-shifted pulse signal is at the high level is equal to the sum of the time that the bypass signal is at the high level and the on-state duration of the switch signal.