CN109427967A - The processing method of semiconductor structure - Google Patents
The processing method of semiconductor structure Download PDFInfo
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- CN109427967A CN109427967A CN201710778937.5A CN201710778937A CN109427967A CN 109427967 A CN109427967 A CN 109427967A CN 201710778937 A CN201710778937 A CN 201710778937A CN 109427967 A CN109427967 A CN 109427967A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000003672 processing method Methods 0.000 title claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 106
- 230000008569 process Effects 0.000 claims abstract description 69
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 52
- 238000010438 heat treatment Methods 0.000 claims abstract description 51
- 238000012545 processing Methods 0.000 claims description 24
- 238000007669 thermal treatment Methods 0.000 claims description 8
- 230000001351 cycling effect Effects 0.000 claims description 2
- 238000007689 inspection Methods 0.000 description 29
- 238000002474 experimental method Methods 0.000 description 13
- 230000008859 change Effects 0.000 description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 8
- 230000014759 maintenance of location Effects 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 8
- 239000001301 oxygen Substances 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 7
- 238000005476 soldering Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000003860 storage Methods 0.000 description 5
- 229910000314 transition metal oxide Inorganic materials 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 3
- 229910001431 copper ion Inorganic materials 0.000 description 3
- 238000011160 research Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 150000004770 chalcogenides Chemical class 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 238000010992 reflux Methods 0.000 description 2
- 229910000906 Bronze Inorganic materials 0.000 description 1
- 229910000618 GeSbTe Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229930002839 ionone Natural products 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 230000036647 reaction Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a kind of processing methods of semiconductor structure, comprising: provides the semiconductor structure with multiple memory components；A formation process is carried out, to initialize the operation of memory component；One is carried out to semiconductor structure and forms heat treatment；And after carrying out forming heat treatment, storing data to memory component.
Description
Technical field
The invention belongs to technical field of semiconductors, it is related to a kind of processing method of semiconductor structure, and in particular to
A kind of processing method for the semiconductor structure improving data reservation.
Background technique
In recent years, variable resistance type memory (the Conductive bridge resistive random of conductive bridge
Access memory) due to its high switching current ratio, high speed operation and good scalability, and cause correlative study person
Interest.The variable resistance type memory of one conductive bridge generally comprises a hearth electrode；One memory layer (such as silica), shape
At in hearth electrode and an ion supplying layer (ion supplying layer, that is, a top electrode, be formed on memory layer) it
Between.The ion supplying layer of chalcogenide, such as germanium antimony tellurium alloy (Ge2Se2Te5, GST) and it include metal ion such as copper ion
One source.Copper reacts with chalcogenide and forms a bronze medal-GST compound, can discharge rapidly copper ion.It is operated in setting
When (SET operation), applies one and be biased in memory component to cause copper ion to be moved in memory layer and formed and lead
Electrical filament (conducting filaments, CF), process is such as electronic deposition (electro-deposition).Work as conductive filament
It is long enough to bridging memory layer, then reaches a low resistance state (low resistance state, LRS).It is operated resetting
In (RESET operation), applies reverse biased and supplied with causing the copper of conductive filament to dissolve in memory layer and returning to ion
To layer.When conductive filament disintegration, then a high-impedance state (high resistance state, HRS) is returned to.CB ReRAM typically hinders
It is worth transfer characteristic to be controlled by cell reaction (electrolytic reactions), and the formation of the conductive filament in memory layer
(setting) and disintegration (reset) are then respectively low resistance state and high-impedance state.
Also can setting (SET) and reset (RESET) state between switch over operation other known forms can
Changing resistor type memory.With the variable resistance type memory of transition metal oxide (transition metal oxide, TMO)
For, handover mechanism is the movement and redistribution (oxygen movement and re-distribution) according to oxygen.
TMO variable resistance type memory component includes a hearth electrode (bottom electrode), a memory layer (memory
Layer) (i.e includes transition metal oxide material such as hafnium oxide, tantalum oxide, titanium oxide etc.) and a top electrode.When operation,
Voltage is applied to element to move oxygen (or mobile oxygen vacancy) and redistribute oxygen concentration to have a high value or a low resistance.
In setting operation (SET operation), an oxygen vacancy conductive filament (oxygen vacancy filament) can be formed and deposited
Low resistance state is caused in reservoir layer；And in resetting operation (RESET operation), conductive filament (that is, vacancy is lined up
Path) it is disintegrated and is formed in the component the film layer of a tool high value, cause high-impedance state.
In the fabrication process, ReRAM element (ex: chip) will be installed in a circuit board, wherein with a solder reflow process
(soldering reflow process) carries out element installation.In order to reduce cost, encapsulation chip be installed on circuit board it
The preceding data that are preferably first written are in encapsulation chip.After reflow, the data that memory component is written must maintain or still have enough
Window memory (represents the coded data after high temperature reflow to still have to recognize 0/1 numerical value to meet the requirement of memory component
It maintains).However, its coded data of typical ReRAM element has the problem of being easy loss under high temperature, such as 250 DEG C~260
DEG C solder reflow process during, coded data be easy be lost.
Summary of the invention
A kind of processing method of the present invention about semiconductor structure, especially a kind of half with multiple memory components
The processing method of conductor structure, to improve the data retention properties of solder reflow process background storage element.
According to an embodiment, a kind of processing method of semiconductor structure is proposed, comprising: providing has multiple memory components
Semiconductor structure；A formation process (forming process) is carried out to initialize the operation of memory component；To semiconductor
Structure carries out one and forms heat treatment (forming thermal treatment)；And after carrying out forming heat treatment, storage
Data are to memory component.
More preferably understand to have to above-mentioned and other aspect of the invention, special embodiment below, and cooperates appended attached
Detailed description are as follows for figure:
Detailed description of the invention
Fig. 1 is the flow chart of the processing method of the semiconductor structure of first embodiment of the invention.
After the reflow that Fig. 2 is shown in high temperature checks, by and without through the memory component for formation heat treatment (FTT)
Change in resistance.
After the reflow that Fig. 3 is shown in high temperature checks, by and without through the memory component for formation heat treatment (FTT)
Change in resistance, wherein these memory components operate (SET/RESET by setting/reset cycle before reflow inspection
operations)。
Fig. 4 A and Fig. 4 B are the flow chart of two kinds of manufacture semiconductor structures.
Fig. 5 is the flow chart of the processing method of the semiconductor structure of second embodiment of the invention.
Fig. 6 is painted the reflow inspection (250 DEG C of ex:>) with the memory component of the method processing of second embodiment in high temperature
Later, the variation of resistance value.
Fig. 7 is to reset 1 (DB1) of quasi- baking, reset 2 (DB2) of quasi- baking, reset 3 (DB3) of quasi- baking and reflow inspection (S)
Later, four resistance value curves obtained, wherein resistance value increases with the number of baking.
Fig. 8 is painted the structure change of a memory cell in different operation steps.
[symbol description]
101-104,106-108,201-205,206,208: step；
80: resistance conversion layer；
801: defect；
811-817: part.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in more detail.
In embodiment disclosed by the invention, a kind of processing method of semiconductor structure is proposed, it is especially a kind of with more
The processing method of the semiconductor structure (such as a wafer) of a memory component (such as variable resistance type memory (ReRAM)).
According to the processing method that embodiment proposes, before storing data to these memory components, first carry out at least one formation heat
It manages (forming thermal treatment).The method invented according to embodiment, also with an additional heat treatment step
Suddenly, it is applied to after formation process (forming process) and writes data into before element, can improves and deposit
The retention properties (retention properties) of memory element, to pass through solder reflow process (soldering reflow
Process) and promote the ability that long term data retains.The method of one embodiment can be applied to stablize the resistance value (SET of setting state
state resistance)；Furthermore the method for other embodiments can be applied to the resistance value for further stablizing reset state
(RESET state resistance)。
Related embodiment set forth below, the processing method that cooperation attached drawing is proposed so that the present invention will be described in detail.However this hair
It is bright to be not limited to that.Narration in embodiment, such as treatment conditions, processing details and technique application order, are only for example
Purposes of discussion, the range to be protected of the present invention are not limited only to the embodiment described.Furthermore, it should be noted that, the present invention is not
Show all possible embodiment, those skilled in the art can be without departing from the spirit and scope of the present invention to embodiment
Structure and technique are changed and are modified, to meet needed for practical application.Therefore, not in other embodiments proposed by the present invention
It may can apply.Therefore, the description and the appended drawings content is only described herein embodiment and is used, rather than protects model as the present invention is limited
It encloses and is used.
Furthermore the use of ordinal number such as " first ", " second ", " third " etc. used in specification and claims
Word is the element in order to modify claim, itself and unexpectedly contain and represent the element have it is any before ordinal number, also not generation
The sequence or the sequence in manufacturing method of a certain element of table and another element, the use of these ordinal numbers are only used to make have certain
One element of name is able to that clear differentiation can be made with another element with identical name.
<first embodiment>
Fig. 1 is the flow chart of the processing method of the semiconductor structure of first embodiment of the invention.In first embodiment, one
The processing method of kind semiconductor structure includes at least: providing the semiconductor knot with multiple memory components (such as ReRAM)
Structure (such as a wafer) (step 101)；A formation process (forming process) (step 102) is carried out, to initialize these
The operation of memory component；One formation heat treatment (forming thermal treatment) (step 103) of progress (such as make
Semiconductor structure with memory component is by forming heat treatment)；And after carrying out the formation heat treatment, storing data
To memory component (step 106).
Furthermore in one embodiment, after being previously formed heat treatment (step 103), this method also selectively includes:
Before storing data to these memory components, (electrical-cycling) these memory component (steps are electrically recycled
It is rapid 104) for example in a low resistance state (low resistance state, LRS) and a high-impedance state (high resistance
State, HRS) between.
In general, carrying out above-mentioned formation process by applying formation voltage (forming voltage)
(forming process) (step 102), to initialize the operation of memory component.In the operation of formation process, Dang Yite
It is shaped as the electrode that voltage is applied to memory component, then the internal flaw of memory component can be arranged in one or more continuitys
Path.And storing data described in step 106 for example refers to reset/setting data encoding (RESET/SET to memory component
data coding).Therefore, step 106 may also mean that a data write step (data writing step) in this text.
Formation process and reset/setting data encoding details of operation are known to general knowledge known in this field, and this will not be repeated here.
According to the method as disclosed in first embodiment, additional formation heat treatment step (forming thermal
Treatment it) can anneal to small conductive filament (filament) generated in (electronics) formation process, these are small
Conductive filament is gathered into big conductive filament, to carry out the operation of subsequent setting/reset.In the first embodiment, heat treatment step is formed
(step 103) can carry out between about 200 DEG C to about 250 DEG C ranges of a temperature and under the enough processing time.In one example,
One formation heat treatment step carries out processing in the time about 1 hour to about 100 hours at about 200 DEG C of temperature.In another example, one
Form the processing that heat treatment step carries out the time about 1 minute to about 100 minutes at about 250 DEG C of temperature.In one embodiment, shape
It may be expressed as: at the processing time of heat treatment
108800/K-16.82< treatment time < 108800/K-14.82,
Wherein, K is absolute temperature, and the unit for handling the time is the second.It is worth noting that, the processing time may also be longer,
As long as in the process not on element cause damage and influence its function and property, can all apply, view application actual conditions and
Appropriate selection can be done.
After storing data to memory component (ex: reset/setting data encoding), outside memory component is installed on
Portion's circuit board or when being tested the property to check memory component, the method for embodiment can further include: in a reflow temperature
Spend these memory components of reflow under (a reflowing temperature) (as shown in the step 108 of Fig. 1).In general,
The reflow temperature of installation memory component ties up to about 250 DEG C to 260 DEG C.In one example, the formation heat treatment of embodiment
The temperature of (forming thermal treatment, FTT) is lower than reflow temperature.Below with a transition metal oxide
For the variable resistance type memory of (transition metal oxide, TMO), and propose that wherein several groups of related experiments are to adjust
Look into influence of the formation heat treatment of embodiment for memory component property.It is tested as a result, it was confirmed that these have by forming heat
The memory component of processing shows preferable data and retains after the reflow inspection (reflow-examination) of a high temperature
Property (data retention properties).
<experiment 1>
Referring to figure 2., it is shown in after the reflow inspection of high temperature, by and without by forming heat treatment (FTT)
The change in resistance of memory component.In this experiment, the reflow inspection of memory component are as follows: 7 minutes at a temperature of 250 DEG C, repeat
Carry out 3 times (this inspection condition is slightly stronger than general solder reflow process).In Fig. 2, curve 1-4 represents memory component low
The resistance value of resistance state (LRS), curve 1-4 and the case where its corresponding memory component, arrange as follows in experiment:
Curve 1: before reset/setting data encoding, the legacy memory for being heat-treated (FTT) is not formed by one
The resistance value curve of element；
Curve 2: before reset/setting data encoding, the embodiment storage element for being heat-treated (FTT) is formed by one
The resistance value curve of part；
Curve 3: after reflow inspection (ex:250 DEG C of baking), the tradition for being heat-treated (FTT) is not formed by one
The resistance value curve of memory component；And
Curve 4: after reflow inspection (ex:250 DEG C of baking), the embodiment for forming heat treatment (FTT) by one is deposited
The resistance value curve of memory element.
By a baking temperature (such as be equal to such as 250 DEG C of typical reflow soldering temperature and toast about 7 minutes)
After sample to check these memory components, the drift of curve 1 and 2 to the position of curve 3 and 4, this represents these storage elements
Part low resistance state resistance value by high temperature reflow (solder reflow process either Jing Guo a normality or process for example this
The reflow inspection carried out in experiment) after can all increase.However, experimental result clearly shows that, low resistance state is observed after reflow inspection
(LRS) memory component, the resistance value of embodiment memory component (i.e has before reset/setting data encoding by FTT)
Change (from 2 drift of curve to curve 4) and is less than the resistance value change of legacy memory element (i.e does not carry out FTT) (from curve 1
Drift is to curve 3).
In Fig. 2, it is corresponding with it that curve 5-8 represents memory component curve 5-8 in the resistance value of high-impedance state (HRS), experiment
Memory component the case where arrange it is as follows:
Curve 5: before reset/setting data encoding, the legacy memory for being heat-treated (FTT) is not formed by one
The resistance value curve of element；
Curve 6: before reset/setting data encoding, the embodiment storage element for being heat-treated (FTT) is formed by one
The resistance value curve of part；
Curve 7: after reflow inspection (ex:250 DEG C of baking), the tradition for being heat-treated (FTT) is not formed by one
The resistance value curve of memory component；And
Curve 8: after reflow inspection (ex:250 DEG C of baking), the embodiment for forming heat treatment (FTT) by one is deposited
The resistance value curve of memory element.
It is similar, (such as such as 250 DEG C of typical reflow soldering temperature bakings are being equal to about by a baking temperature
7 minutes) after sample to check these memory components, the drift of curve 5 and 6 to the position of curve 7 and 8, this represents these and deposits
Memory element is passing through high temperature reflow (solder reflow process or process either Jing Guo a normality in the resistance value of high-impedance state
Such as the reflow inspection that carries out in this experiment) after can all increase.Curve 5-8's the results show that observing high resistant after reflow inspection
The resistance value of the memory component of state, embodiment memory component (i.e has before reset/setting data encoding by FTT) changes
The resistance value for becoming (from 6 drift of curve to curve 8) and legacy memory element (i.e does not carry out FTT) changes (from 5 drift of curve
To curve 7) it does not have much difference.
However, (i.e's embodiment memory component of observation low resistance state (LRS) and high-impedance state (HRS) exists after reflow inspection
Have by FTT before reset/setting data encoding) resistance value, in extremely low failure probability (a failure rate) such as 10-5
Under probability (=10ppm) between corresponding low resistance state and high-impedance state, there are still have one can recognize section (a recognized
Region it) can provide a sensing window (sensing window).Please refer to resulting curve 4 (LRS) and curve 8 after toasting
(HRS).When carrying out a read operation, the state of memory component, in particular, the configuration of the resistance value of resistance value conversion layer, is being applied
It can be sensed when adding a sensing voltage (sensing voltage)；This sensing voltage is otherwise referred to as a reading voltage
Vread.Therefore, the formation heat treatment (FTT) of embodiment can improve the retention properties of memory component to weld by high temperature reflux
It connects technique and promotes the long term data reserve capability of memory component.
<experiment 2>
Above-mentioned 1 research of experiment is heat-treated (FTT) for its low-resistance of memory component according to the formation of an embodiment
Influence caused by the resistance value of state (LRS) (its result is as shown in Figure 2), wherein these element samples are with step as shown in Figure 1
101, it 102,103,106 and 108 is handled.In addition, the present invention also proposes another experiment, research is according to another embodiment
Formation heat treatment (FTT) for the memory component in setting/reset circulate operation (SET/RESET operations)
Influence caused by the resistance value of low resistance state (LRS), wherein these element samples with step 101 as shown in Figure 1,102,103,
104, it 106 and 108 is handled.
Referring to figure 3., it is shown in after the reflow inspection of high temperature, by and without by forming heat treatment (FTT)
The change in resistance of memory component, wherein these memory components are before reflow inspection by setting/reset cycle operation
(SET/RESET operations).In this experiment, memory component repeats 3 times 7 minutes at a temperature of 250 DEG C, with
Complete reflow inspection.In Fig. 3, curve (B) (this three curves are drawn before carrying out reflow inspection), curve (B ') and curve
(B '-FTT) (this three curves are drawn after carrying out reflow inspection) represents memory component in the resistance value of low resistance state (LRS)；
And the corresponding conditions arrangement of the memory component of these tests is as follows:
Curve (B): not by forming a legacy memory element of heat treatment (FTT) and by forming heat treatment
(FTT) the resistance value curve of an embodiment memory component, passes through three kinds of different circulate operations respectively:
(i) formation operation (Forming operation)+setting operation (SET operation)；
(ii) formation operation (Forming operation)+setting operation (SET operation)+is formed and is heat-treated
(FTT)+reset operation (RESET operation)+setting operation (SET operation)；And
(iii) formation operation (Forming operation)+reset operation (RESET operation)+is formed and is heat-treated
(FTT)+setting operation (SET operation).
Curve (B '): after reflow inspection (ex:250 DEG C of baking), the biography for being heat-treated (FTT) is not formed by one
The resistance value curve of system memory component.
Curve (B '-FTT): after reflow inspection (ex:250 DEG C of baking), one by a formation heat treatment (FTT) is real
Apply the resistance value curve of a memory component.
Similar, curve (C) and (C ') are represented, before and after reflow checks, not by forming heat treatment (FTT)
Memory component high-impedance state (HRS) resistance value curve.
For curve (B) the results show that before reflow inspection, the resistance value result of three curves is closely similar.Temperature is baked one
After checking these memory component samples under degree (such as it is equal to such as 250 DEG C of typical reflow soldering temperature bakings about 7
Minute), curve (B) drift to the position of curve (B ') and curve (B '-FTT), this resistance value for representing these memory components exists
Can all it increase after high temperature reflow.However, its result clearly shows that, observation memory component is in low resistance state after reflow inspection
(LRS) when, the memory component (i.e has before reset/setting data encoding by FTT) of embodiment has less resistance value to become
Change.Please refer to curve (B) and curve (B '-FTT).
Furthermore resulting curve (B '-FTT) and curve (C ') as a result, tying up to an extremely low failure probability for example after baking
10-5Under probability (=10ppm) between corresponding low resistance state and high-impedance state, there are still have one can recognize section (a
Recognizedregion it) can provide a sensing window.Therefore, the formation heat treatment (FTT) of embodiment can improve circulation
The retention properties of the memory component of operation to pass through high temperature reflux welding procedure, and promote the long issue of memory component
According to reserve capability.
It is worth noting that, the practical feelings that the formation of embodiment is heat-treated the temperature of (FTT) and the processing time is visually applied
Condition and suitably can modify or adjust.It is made for example, semiconductor structure/memory component is all in the manufacturing process before data is written
At heat history can consider together, with adjust formed heat treatment (FTT) treatment conditions.A and Fig. 4 B referring to figure 4.,
The flow chart of semiconductor structure is manufactured for two kinds.It please also refer to Fig. 1.Step system Fig. 4 A and Fig. 4 B identical as Fig. 1 indicates phase
Same label, and details repeats no more.Fig. 4 A, Fig. 4 B process are different in, step 106 (storing data to memory component)
With the sequence of step 107 (wafer cutting and encapsulation).If the write step of data ties up to the rear progress of wafer cutting and encapsulation, such as
Shown in Fig. 4 B, then from formed heat treatment step (step 103) and wafer cut and encapsulate (step 107) (step 103 and
107 tie up between the step of formation process and data are written carry out) total heat history (total thermal
Accumulation it) can consider together, therefore, form the condition of heat treatment step (step 103), such as temperature and/or processing
Time can be reduced.
<second embodiment>
In first embodiment, in a shape of the preceding progress of reset/setting data encoding (RESET/SET data coding)
It is to stablize the resistance value of setting state (SET state at heat treatment (forming thermal treatment)
resistance).In second embodiment, in addition to the formation heat treatment that such as first embodiment is invented, processing method can further include
One resets thermal process (RESET thermal process), using resistance value (the RESET state to stablize reset state
resistance)。
According to second embodiment, it is written in the rear of (electronic type) formation operation (forming operation) but in data
Before (i.e. reset/data encoding is set), the quasi- baking (SET dummy baking) of a setting is carried out (also that is, first implements
The formation heat treatment of example) and a reset thermal process.
5th figure system is the flow chart of the processing method of the semiconductor structure of second embodiment of the invention.Such as the 5th figure, the
A kind of method of processing semiconductor structure of two embodiments includes: to provide the semiconductor structure with multiple memory components
(step 201)；A formation process (forming process) (step 202) is carried out, to initialize the behaviour of these memory components
Make；Circulation (pre-cycling) these memory component (steps 203 in advance；Such as electrically it is circulated in the low of memory component
Between resistance state and high-impedance state, such as step 104) of the 1st figure；Carry out quasi- baking (SET dummy the baking) (step of a setting
204；It can be considered the formation heat treatment such as first embodiment)；It carries out one and resets thermal process (RESET thermal process)
(step 205)；Storing data is to memory component (step 206；Such as reset/data encoding is set)；And in a reflow temperature
Spend reflow memory component (step 208 under (reflowing temperature)；When memory component is installed on external circuit
Plate or when being tested the property to check memory component, will do it reflow).
The step of second embodiment, handles details, can including temperature and the processing time etc. that quasi- baking (step 204) is arranged
Referring to the content of the formation heat treatment of first embodiment, details are not described herein.
In second embodiment, reset thermal process (RESET thermal process) (step 205) can a temperature about
The enough processing time is carried out between 150 DEG C to about 250 DEG C ranges.In one embodiment, when carrying out resetting the processing of thermal process
Between between about 5 minutes to about 10 hours ranges.In one embodiment, the processing time for resetting thermal process may be expressed as:
108800/K-16.82< treatment time < 108800/K-14.82,
Wherein, K is absolute temperature, and the unit for handling the time is the second.Similarly, it is also possible to the longer processing time, only
Will during for element cause damage and influence its function and property, can all apply, depending on application actual conditions and
Appropriate selection can be done.
In second embodiment, carrying out for the reset thermal process of step 205 includes repeatedly following the steps below n times: (1) into
Row one resets operation (a RESET operation)；(2) it carries out one and resets quasi- baking (a RESET dummy baking)；
Wherein n=1 or n >=2, and n is positive integer.Such as semiconductor structure or memory component at least one carry out resetting quasi- baking
Roasting and a kind of heat treatment (ex:150 DEG C to 250 DEG C).
In one embodiment, n is equal to 1.It carries out one group of reset operation and resets to intend toasting that reset state can be improved
Resistance value.One of process of second embodiment, (1) reset operation and (2) for carrying out one group once reset and intend baking, can letter
It is as follows to be denoted as expression formula (1):
The preparatory circulation (Pre-cycling RESET/SET process) of formation process (Forming) → reset/setting
1 (Reset of the quasi- quasi- baking of baking (SET Dummy baking) → reset → reset of (such as R/S/R/S/R/S) → setting
Dummy baking 1) → reset state coding (Reset state coding) → setting state encoding (Set state
Coding) → reflow (such as: 250 DEG C of temperature >) ... expression formula (1) ... ...
Wherein, above-mentioned " R " and " S " system are respectively the abbreviation of Reset and " setting " operation.
In other embodiments, the reset thermal process of step 205 carries out including the reset for being repeatedly performed for more than one group
Operation and the quasi- baking of reset.In one embodiment, n is equal to 3, significantly to improve the resistance value of the reset state of memory component.
One of process of second embodiment, (1) reset operation and (2) for carrying out three groups once reset and intend baking, can be abbreviated as
Expression formula (2) is as follows:
The preparatory circulation (Pre-cycling RESET/SET process) of formation process (Forming) → reset/setting
(such as R/S/R/S/R/S) → the quasi- baking (SET Dummy baking) of setting → resets the quasi- baking 1 of 1 (RESET 1) → reset
(DB1) → 3 (DB3) of the quasi- quasi- baking of baking 2 (DB2) → reset 3 (RESET 3) → reset of reset 2 (RESET 2) → reset → again
Position state encoding (Reset state coding) → setting state encoding (Set state coding) → reflow (such as: temperature
Spend 250 DEG C of >) ... expression formula (2),
It carries out related experiment again herein and thermal process (RESET thermal process) is resetted for depositing with research one
It is influenced caused by the property of memory element.Fig. 6 is please referred to, is painted and is existed with the memory component of the method processing of second embodiment
After the reflow inspection (250 DEG C of ex:>) of high temperature, the variation of resistance value.In the method for this embodiment, three groups of (1) is carried out
It resets operation and (2) and once resets quasi- baking.In Fig. 6, curve (11) and (12) represent memory component in low resistance state (LRS)
Resistance value, and curve (13) and (14) represent memory component in the resistance value of high-impedance state (HRS).Furthermore curve (11) and (13) are
Resistance value of the memory component before carrying out reflow inspection, and curve (12) and (14) they are that memory component is carrying out reflow inspection
Resistance value later.Fig. 6's as a result, it was confirmed that have by the quasi- baking (SET dummy baking) of a setting (also that is, first embodiment
Formation heat treatment) and one reset thermal process processing memory component, after the reflow of high temperature checks, with preferable data
Retention properties.This is from attached drawing, in an extremely low failure probability such as 10-5Corresponding low resistance state and height under probability (=10ppm)
There are still thering is one can recognize section (for example, about 13k ohm) to provide a sensing window between resistance state, can learn.Moreover, very
To such as 10-6There are still have one can recognize section (for example, about 7ohm) for probability (=1ppm).
The quasi- baking of the setting of embodiment makes memory to make the fixed forming of main conductive filament and wipe out its branch
Element obtains stable setting state, reduces the loss of the coded data of setting state.Furthermore there is fracture or compared with Weak link part
Conductive filament the coded data of serious reset state can caused to be lost after reflow process.Intend drying in the reset of embodiment
During roasting (RESET dummy baking), conductive filament has fracture or can again be reset compared with Weak link part, therefore
After resetting quasi- baking, it can achieve a stable reset state, reduce the loss of the coded data of reset state.
It is such as above-mentioned, multiple reset operation can be carried out to rebuild the fracture of conductive filament or compared with weak part.For example, three times
After resetting quasi- baking, reset state becomes more stable, inhibits the coded data of reset state with can dramatically after high temperature reflow
Loss.Please refer to Fig. 7 and Fig. 8 and above-mentioned expression formula (2).Fig. 7 is to reset 1 (DB1) of quasi- baking, reset quasi- baking 2
(DB2), after resetting 3 (DB3) of quasi- baking and reflow inspection (S), four resistance value curves obtained, wherein resistance value is with baking
Number and increase.Fig. 8 is painted the structure change of a memory cell in different operation steps.It is noted that its attached drawing
(a)-(g) is only shown in the structure change in a resistance conversion layer, and well known to those skilled in the art positioned at resistance conversion layer
The electrode omission of upper and lower side is not painted.As shown in figure 8, in reset state (attached drawing (a)), lacking in resistance conversion layer 80
It falls into 801 (such as oxygen vacancies) and is arranged in an at least continuous part 811.During resetting quasi- baking 1 (DB1, attached drawing (b)), defect
801 can more assemble and form a longer continuous part 812 (also that is, resistance value reduces).It is attached after resetting again (attached drawing (c))
The continuous part 812 of figure (b) can be broken into a shorter continuous part 813 (also that is, resistance value increases).Resetting quasi- baking 2
Period (DB2, attached drawing (d)), defect 801 can assemble once again and establish a continuous part 814 (also that is, resistance value reduces).It is multiple again
After position (attached drawing (e)), the continuous part of script attached drawing (d) is broken into a shorter continuous part 815 (also that is, resistance value increases
Add).During resetting quasi- baking 3 (DB3, attached drawing (f)), defect 801 can assemble once again and establish a continuous part 816 (also that is,
Resistance value reduces).During reseting data coding (reset date coding, attached drawing (g)), the continuous part of script attached drawing (f)
816 can be interrupted and form shortest part 817 (also that is, conductive filament is disintegrated), thus have highest resistance value.
Therefore, Fig. 7 and Fig. 8's the results show that it is identical failure probability such as 10-5Under probability (=10ppm), curve
(S) there is highest resistance value (after reflow checks), and curve (DB1) then has minimum resistance value.Therefore, in the quasi- baking process of embodiment
Afterwards (as quasi- baking is arranged and resets quasi- baking), it is possible to reduce the loss of coded data (SET/RESET) and provide enough deposit
Reservoir window is to be recognized.
In addition, the processing method of embodiment at least needs to carry out using two technique boards.For example, formation process is one first
Technique board (first processing machine) carry out, and as the first and second embodiment proposed data be written before
Additional formation heat treatment (the forming thermal treatment) step of one first carried out is then in one second technique board
(second processing machine) is carried out.In one embodiment, which can provide at least 150 DEG C to 250
DEG C or 200 DEG C to 250 DEG C ranges between a heating temperature.Therefore, in use, semiconductor structure can be in the first technique machine
Such as formation process and the reset recycled in advance/setting technique are carried out in platform, then pass to the second technique board to carry out reality
The quasi- baking of setting/reset for applying example, sends back the first technique board again then to carry out setting/reseting data of memory component
Coding.
According to above-mentioned, the sample of memory component is checked under a baking temperature (such as equal to a reflow soldering temperature),
Its experiment has good data retention properties the results show that applying the memory component of the method such as the first and second embodiment,
In an extremely low failure probability such as 10-5It is distinguishable there are one still between corresponding low resistance state and high-impedance state under probability (=10ppm)
Know section (a recognized region), to can provide a sensing window.(i.e. is in data for the method for first embodiment
The additional formation heat treatment of one carried out before write-in) it can be used to stablize the resistance value of setting state.And the method for second embodiment
(a setting thermal process and a reset thermal process that i.e. is carried out before data write-in), which can be used to stablize, is more than setting state
Resistance value, also stablize the resistance value of reset state.The method of embodiment provides useful and inexpensive program, is suitble in volume production
Application, furthermore the characteristic electron of the memory component of application can also be effectively improved.
It is worth noting that, if above-mentioned method is only to describe section Example or application examples of the invention, the present invention
It is not restricted to the range and embodiment of above-mentioned steps.Other different embodiments can also be applied.The step of its example, can basis
The demand of practical application and adjust and change.Therefore exemplary step is used by way of example only, rather than limitation is used.
Although however, it is not to limit the invention in conclusion the present invention is disclosed as above with embodiment.Institute of the present invention
Belong to those skilled in the art, without departing from the spirit and scope of the present invention, when can make it is various change and retouching.Cause
This, protection scope of the present invention is when being subject to the claim that claim defined.
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical scheme and beneficial effects
It describes in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in guarantor of the invention
Within the scope of shield.
Claims (10)
1. a kind of processing method of semiconductor structure, comprising:
The semiconductor structure for having multiple memory components is provided；
A formation process (forming process) is carried out to initialize the operation of these memory components；
One is carried out to the semiconductor structure and forms heat treatment (forming thermal treatment)；And
After carrying out the formation heat treatment, storing data to these memory components.
2. processing method according to claim 1, after formation heat treatment, this method further include: in storing data
To before these memory components, (electrical-cycling) these memory components are electrically recycled in a low resistance state (low
Resistance state, LRS) and a high-impedance state (high resistancestate, HRS) between.
3. processing method according to claim 1, the model that wherein formation heat treatment is 200 DEG C to 250 DEG C in a temperature
It is carried out between enclosing, wherein the processing time of formation heat treatment are as follows:
108800/K-16.82< treatment time < 108800/K-14.82,
Wherein, K is absolute temperature, and the unit of the processing time is the second.
4. processing method according to claim 1, after storing data to these memory components, this method is also wrapped
It includes: these memory components of reflow at a reflow temperature (a reflowing temperature).
5. processing method according to claim 1, wherein the formation process is carried out in one first technique board, and the formation
Heat treatment is carried out in one second technique board, and wherein the second technique board can provide between at least 200 DEG C to 250 DEG C ranges
One heating temperature.
6. processing method according to claim 1, wherein formation heat treatment is quasi- baking (the SET dummy of a setting
), and this method baking further include:
After carrying out the quasi- baking of the setting and before storing data to these memory components, at least to these memory components
One of them carries out one and resets thermal process (a RESET thermal process), and wherein the reset thermal process is in a temperature
It is carried out between 150 DEG C to 250 DEG C of range, the processing time of the reset thermal process are as follows:
108800/K-16.82< treatment time < 108800/K-14.82,
Wherein, K is absolute temperature, and the unit of the processing time is the second.
7. processing method according to claim 6, further includes: after carrying out the formation process and carry out that the setting is quasi- to dry
Before roasting, the reset/setting technique (pre-cycling RESET/SET process) recycled in advance is carried out.
8. processing method according to claim 6, wherein the reset thermal process includes repeatedly following the steps below n times:
It carries out one and resets operation (a RESET operation)；With
It carries out one and resets quasi- baking (a RESET dummy baking)；
Wherein n >=2, and n is positive integer.
9. processing method according to claim 8, wherein n is equal to 3.
10. processing method according to claim 6, wherein the formation process is carried out in one first technique board, and this sets
Quasi- baking (SET dummy baking) and the reset thermal process (RESET thermal process) are set in one second technique machine
Platform carries out, and wherein the second technique board can provide the heating temperature between at least 150 DEG C to 250 DEG C ranges.
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