CN109427800B - Nonvolatile memory device and method of manufacturing the same - Google Patents

Nonvolatile memory device and method of manufacturing the same Download PDF

Info

Publication number
CN109427800B
CN109427800B CN201810933109.9A CN201810933109A CN109427800B CN 109427800 B CN109427800 B CN 109427800B CN 201810933109 A CN201810933109 A CN 201810933109A CN 109427800 B CN109427800 B CN 109427800B
Authority
CN
China
Prior art keywords
upper substrate
layer
memory cell
memory device
cell array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810933109.9A
Other languages
Chinese (zh)
Other versions
CN109427800A (en
Inventor
尹东吉
金灿镐
郭判硕
全哄秀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN109427800A publication Critical patent/CN109427800A/en
Application granted granted Critical
Publication of CN109427800B publication Critical patent/CN109427800B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/60—Peripheral circuit regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

A non-volatile memory device may include a first semiconductor layer including a peripheral region including one or more peripheral transistors on a lower substrate. The nonvolatile memory device may further include a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate, the second semiconductor layer further including a memory cell array on the upper substrate. The upper substrate may include a first upper substrate on the first semiconductor layer, a first layer on the first upper substrate, and a second upper substrate on the first layer.

Description

Nonvolatile memory device and method of manufacturing the same
Technical Field
The present inventive concept relates to a memory device, and more particularly, to a nonvolatile memory device and a method of manufacturing the same.
Background
Recently, with the multifunctionalization of data communication apparatuses, there is a demand for increased capacity and higher integration of memory devices. As memory cell sizes decrease for high integration, operational circuitry and/or wiring in the memory devices for operation and electrical connection of the memory devices is becoming more complex. Therefore, a memory device having excellent electrical characteristics with improved integration is required.
Disclosure of Invention
Some example embodiments provide a nonvolatile memory including a top substrate.
According to some example embodiments, a nonvolatile memory device may include a first semiconductor layer and a second semiconductor layer. The first semiconductor layer may include a peripheral region. The peripheral region may include one or more peripheral transistors on the lower substrate. The second semiconductor layer may be on the peripheral region. The second semiconductor layer may include an upper substrate. The second semiconductor layer may further include a memory cell array on the upper substrate. The upper substrate may include a first upper substrate on the first semiconductor layer, a first layer on the first upper substrate, and a second upper substrate on the first layer.
According to some example embodiments, a nonvolatile memory device may include: a lower substrate; a peripheral region on the lower substrate, the peripheral region including peripheral circuitry on the lower substrate; and a memory cell region on the peripheral region. The memory cell region may include an upper substrate. The memory cell region may further include a memory cell array on the upper substrate. The upper substrate may include a first upper substrate, a second upper substrate over the first upper substrate, and a first layer between the first upper substrate and the second upper substrate.
According to some example embodiments, a nonvolatile memory device may include a memory cell region including a memory cell array and a peripheral region including peripheral circuitry. The memory cell region may be on the peripheral region. The nonvolatile memory device may include an upper substrate between the peripheral region and the memory cell array. The upper substrate may include a first upper substrate on the peripheral region, a first layer on the first upper substrate, and a second upper substrate on the first layer.
According to some example embodiments, a method of manufacturing a nonvolatile memory device may include forming one or more peripheral transistors on a portion of a lower substrate, the one or more peripheral transistors connected to a plurality of peripheral circuit wires, and a lower insulating layer covering the one or more peripheral transistors and the peripheral circuit wires. The method may include: forming a first upper substrate on the lower insulating layer; forming a first layer on a first upper substrate; forming a second upper substrate on the first layer; and forming a memory cell region on the second upper substrate, the memory cell region including a memory cell array.
Drawings
Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a block diagram illustrating a memory device according to some example embodiments;
fig. 2 is a diagram schematically illustrating a structure of the memory device of fig. 1 according to some example embodiments of the inventive concepts;
Fig. 3 is a circuit diagram illustrating an equivalent circuit of a first memory block, which is one of the plurality of memory blocks of fig. 1, according to some example embodiments of the inventive concept;
fig. 4A is a cross-sectional view of a memory device according to some example embodiments of the inventive concepts;
FIG. 4B is an enlarged cross-sectional view of area A-1 of FIG. 4A;
Fig. 5A is a cross-sectional view of a memory device according to some example embodiments of the inventive concepts;
FIG. 5B is an enlarged cross-sectional view of area A-2 of FIG. 5A;
fig. 6A is a cross-sectional view of a memory device according to some example embodiments of the inventive concepts;
FIG. 6B is an enlarged cross-sectional view of area A-3 of FIG. 6A;
fig. 7 is a cross-sectional view of a memory device according to some example embodiments of the inventive concepts;
Fig. 8 is a cross-sectional view of a memory device according to some example embodiments of the inventive concepts;
fig. 9 is a cross-sectional view of a memory device according to some example embodiments of the inventive concepts;
Fig. 10 is a cross-sectional view of a memory device according to some example embodiments of the inventive concepts;
Fig. 11A to 11I are cross-sectional views sequentially illustrating operations for describing a method of manufacturing a memory device according to some example embodiments of the inventive concepts; and
Fig. 12 is a block diagram illustrating a Solid State Drive (SSD) system including a storage device according to some example embodiments of the inventive concepts.
Detailed Description
Fig. 1 is a block diagram illustrating a memory device according to some example embodiments.
Referring to fig. 1, a memory device 10 may include a memory cell array 50 and peripheral circuits 60. Although not shown, the memory device 10 may also include data input/output circuitry and/or input/output interfaces.
The memory cell array 50 includes a plurality of memory cells, and may be connected to a string selection line SSL, a word line WL, a ground selection line GSL, and a bit line BL. Specifically, the memory cell array 50 may be connected to the row decoder 62 through a string selection line SSL, a word line WL, and a ground selection line GSL, and may be connected to the page buffer 63 through a bit line BL.
The plurality of memory cells included in the memory cell array 50 may be, for example, flash memory cells. Hereinafter, example embodiments will be described in detail with reference to a case where a plurality of memory cells are NAND flash memory cells. However, the inventive concept is not limited thereto. According to some example embodiments, the plurality of memory cells may be resistive memory cells, such as Resistive RAM (RRAM) memory cells, phase change RAM (PRAM) memory cells, or Magnetic RAM (MRAM) memory cells.
The memory cell array 50 may include a plurality of memory blocks BLK1 to BLKz, and each memory block may have a planar structure or a three-dimensional structure. The memory cell array 50 may include at least one cell block of a single-layer cell block including single-layer cells (SLC), a multi-layer cell block including multi-layer cells (MLC), a tri-layer cell block including tri-layer cells (TLC), and a four-layer cell block including four-layer cells. For example, some of the plurality of memory blocks BLK1 to BLKz may be single-layer unit blocks, and other unit blocks may be multi-layer unit blocks, three-layer unit blocks, or four-layer unit blocks.
The peripheral circuit 60 may receive an address ADDR, a command CMD, and a control signal CTRL from a device external to the memory device 10, and may exchange DATA with a device external to the memory device 10. Peripheral circuitry 60 may include control logic 61, row decoder 62, and page buffer 63. Although not shown, the peripheral circuit 60 may further include various sub-circuits such as a voltage generating circuit generating various voltages for the operation of the memory device 10 and an error correction circuit correcting errors of data read from the memory cell array 50.
The control logic 61 controls the overall operation of the memory device 10, and may control the memory device 10 so that a memory operation corresponding to a command CMD provided from a memory controller (not shown) may be performed. The control logic 61 may generate various internal control signals used in the memory device 10 in response to a control signal CTRL supplied from a memory controller (not shown). For example, the control logic 61 may adjust the voltage levels provided to the word lines WL and the bit lines BL during a storage operation such as a program operation or an erase operation.
The row decoder 62 may select at least one memory block among the plurality of memory blocks BLK1 to BLKz in response to an address ADDR supplied from a memory controller (not shown). The row decoder 62 may select at least one word line of the selected memory block in response to the address ADDR.
The row decoder 62 may transmit a voltage for performing a memory operation to a word line of the selected memory block. For example, during a programming operation, row decoder 62 may transmit a program voltage and a verify voltage to a selected word line, and a pass voltage (pass voltage) to an unselected word line. Here, the selected word line may refer to a word line connected to a memory cell in which a program operation is to be performed, and the unselected word lines may refer to word lines other than the selected word line. Further, the row decoder 62 may select some of the string select lines SSL in response to the address ADDR.
The page buffer 63 may be connected to the memory cell array 50 through a bit line BL. The page buffer 63 may operate as a write driver or a sense amplifier. The page buffer 63 may operate as a write driver and apply a voltage corresponding to DATA to be stored in the memory cell array 50 to the bit line BL. Meanwhile, during a read operation, the page buffer 63 may operate as a sense amplifier and read out the DATA stored in the memory cell array 50.
Fig. 2 is a diagram schematically illustrating a structure of the memory device 10 of fig. 1 according to some example embodiments of the inventive concepts. As described above with reference to fig. 1, the memory device 10 may include the memory cell array 50 and the peripheral circuits 60, and such components of the memory device 10 may be provided by a semiconductor manufacturing process. Hereinafter, fig. 2 will be described with reference to fig. 1.
Referring to fig. 2, the memory device 10 may include a first semiconductor layer 20 and a second semiconductor layer 30. The second semiconductor layer 30 may be stacked on the first semiconductor layer 20 in the second direction. To reiterate, the second semiconductor layer 30 may be on the first semiconductor layer 20. The second semiconductor layer 30 may be directly on the first semiconductor layer 20 such that no intervening element exists between the second semiconductor layer 30 and the first semiconductor layer 20, and the second semiconductor layer 30 is in direct contact with the first semiconductor layer 20. According to some example embodiments of the inventive concepts, the second semiconductor layer 30 may include the memory cell array 50 of fig. 1, and the first semiconductor layer 20 may include the peripheral circuit 60. In other words, the first semiconductor layer 20 may include a lower substrate, and one or more circuits, for example, one or more circuits ("at least one example of a circuit") corresponding to the control logic 61, the row decoder 62, and the page buffer 63, may be formed in the first semiconductor layer 20 based on forming semiconductor devices such as transistors and patterns for wiring the semiconductor devices on the lower substrate.
After one or more circuits are formed in the first semiconductor layer 20, the second semiconductor layer 30 including the memory cell array 50 may be formed. In other words, the second semiconductor layer 30 may include and the memory cell array 50 may be formed on and supported by the upper substrate.
According to some example embodiments, the upper substrate supporting the memory cell array 50 may include a first upper substrate, a second upper substrate over ("upper") the first upper substrate, and a first layer between the first upper substrate and the second upper substrate. In other words, the upper substrate may be divided into a first upper substrate and a second upper substrate disposed apart ("spaced apart") from the first upper substrate, and at least one layer may be disposed between the first upper substrate and the second upper substrate ("may be between the first upper substrate and the second upper substrate").
In addition, a pattern for electrically interconnecting the memory cell array 50 (i.e., the word line WL and the bit line BL) and the circuits formed in the first semiconductor layer 20 may be disposed in the second semiconductor layer 30. On the second semiconductor layer 30 in which the memory cell array 50 is disposed (e.g., "including"), the plurality of word lines WL may extend in a first direction, which is a direction perpendicular to the stacking direction (second direction), and the plurality of bit lines BL may also extend in a third direction, which is another direction perpendicular to the stacking direction (second direction). As described above, the memory cells included in the memory cell array 50 may be accessed by the plurality of word lines WL and the plurality of bit lines BL, and the plurality of word lines WL and the plurality of bit lines BL may be electrically connected to the peripheral circuit 60 disposed in the first semiconductor layer 20.
Accordingly, the memory device 10 may have a structure in which the memory cell array 50 and the peripheral circuits 60 are arranged in the stacking direction (i.e., the second direction), that is, a cell on periphery (or Cell Over Periphery) (COP) structure. By disposing a circuit other than the memory cell array 50 under the memory cell array 50, the area occupied by the COP structure on a plane perpendicular to the stacking direction can be effectively reduced, and thus the area of the structure in at least one plane can be effectively reduced, thereby increasing the number of memory cells in the memory device 10. As a result, the integration and/or density of the memory device 10 may be improved.
Although not shown in fig. 2, a plurality of pads may be provided for electrical connection with devices external to the memory device 10. For example, a plurality of pads may be provided for the command CMD, the address ADDR, and the control signal CTRL received from a device external to the memory device 10, and a plurality of pads for inputting/outputting the DATA may be provided. The plurality of pads may be disposed adjacent to the peripheral circuit 60 in a vertical direction (second direction) or a horizontal direction (first direction or third direction), and the peripheral circuit 60 processes a signal received from a device external to the memory device 10 or a signal to be transmitted to a device external to the memory device 10.
Fig. 3 is a circuit diagram illustrating an equivalent circuit of a first memory block BLK1, which is one of the plurality of memory blocks BLK1 to BLKz of fig. 1, according to some example embodiments of the inventive concept.
Referring to fig. 3, the first memory block BLK1 may be a vertical NAND flash memory, and each of the plurality of memory blocks BLK1 to BLKz shown in fig. 1 may be implemented as shown in fig. 3. The first memory block BLK1 may include a plurality of NAND strings NS11 to NS33, a plurality of word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8, a plurality of bit lines BL1 to BL3, a plurality of ground selection lines GSL1, GSL2, and GSL3, a plurality of string selection lines SSL1 to SSL3, and a common source line CSL. Here, the number of NAND strings, the number of word lines, the number of bit lines, the number of ground select lines, and the number of string select lines may vary according to embodiments.
NAND strings NS11, NS21 and NS31 are provided between the first bit line BL1 and the common source line CSL, NAND strings NS12, NS22 and NS32 are provided between the second bit line BL2 and the common source line CSL, and NAND strings NS13, NS23 and NS33 are provided between the third bit line BL3 and the common source line CSL. Each NAND string (e.g., NAND string NS 11) may include a string select transistor SST, a plurality of memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8, and a ground select transistor GST connected in series with each other.
NAND strings commonly connected to a bit line may form a column. For example, NAND strings NS11, NS21, and NS31, which are commonly connected to a first bit line BL1, can correspond to a first column, NAND strings NS12, NS22, and NS32, which are commonly connected to a second bit line BL2, can correspond to a second column, and NAND strings NS13, NS23, and NS33, which are commonly connected to a third bit line BL3, can correspond to a third column.
NAND strings that are commonly connected to a single string select line may form a row. For example, NAND strings NS11, NS12, and NS13 commonly connected to a first string selection line SSL1 may correspond to a first row, NAND strings NS21, NS22, and NS23 commonly connected to a second string selection line SSL2 may correspond to a second row, and NAND strings NS31, NS32, and NS33 commonly connected to a third string selection line SSL3 may correspond to a third row.
Each string selection transistor SST may be connected to a corresponding one of a plurality of string selection lines SSL1 to SSL 3. The plurality of memory cells MC1 to MC8 may be connected to corresponding word lines WL1 to WL8, respectively. The ground selection transistor GST may be connected to a corresponding one of the plurality of ground selection lines GSL1 to GSL3, and each string selection transistor SST may be connected to a corresponding one of the plurality of bit lines BL1 to BL 3. The ground selection transistor GST may be connected to the common source line CSL.
According to some example embodiments, word lines (e.g., first word line WL 1) at the same height are connected to each other, a plurality of string selection lines SSL1 to SSL3 are separated from each other, and a plurality of ground selection lines GSL1 to GSL3 are also separated from each other. For example, in the case of programming a memory cell connected to the first word line WL1 and included in the NAND strings NS11, NS12, and NS13, the first word line WL1 and the first string select line SSL1 are selected. However, the inventive concept is not limited thereto. According to some example embodiments, a plurality of ground selection lines GSL1 to GSL3 may be connected to each other.
Fig. 4A is a cross-sectional view of a memory device according to some example embodiments of the inventive concepts. Fig. 4B is an enlarged cross-sectional view of area a-1 of fig. 4A. As described herein, the memory device including the memory device 10 may be a nonvolatile memory device.
Referring to fig. 4A and 4B, the memory device 10 may include a first semiconductor layer 20 including a peripheral region PERI and a second semiconductor layer 30 including a memory cell region MCA. To reiterate, at least a portion of the first semiconductor layer 20 including one or more peripheral circuits may be referred to as a peripheral region PERI based on the portion of the first semiconductor layer 20 including one or more peripheral circuits, and at least a portion of the second semiconductor layer 30 including one or more memory cell arrays may be referred to as a memory cell region MCA based on the portion of the second semiconductor layer 30 including one or more memory cell arrays. The memory device 10 may have a structure in which the second semiconductor layer 30 is stacked on the first semiconductor layer 20. At least a portion of the peripheral region PERI and at least a portion of the memory cell region MCA may overlap each other in a vertical direction, but the inventive concept is not limited thereto.
The first semiconductor layer 20 may include a lower substrate l_sub, one or more peripheral transistors 22 disposed on the lower substrate l_sub, peripheral circuit wiring electrically connected to the one or more peripheral transistors 22, and a lower insulating layer 24 covering the peripheral circuit wiring. The one or more peripheral transistors 22 and/or the one or more peripheral circuit wirings may include, at least in part, one or more peripheral circuits. To reiterate, the first semiconductor layer 20 may include a peripheral region PERI including one or more peripheral transistors 22 on the lower substrate l_sub. As shown in fig. 4A, one or more peripheral circuits may be on the lower substrate l_sub. To reiterate, the memory device 10 may include a peripheral region PERI on the lower substrate l_sub, wherein the peripheral region PERI includes peripheral circuitry (e.g., one or more peripheral transistors 22) on the lower substrate l_sub.
The lower substrate l_sub may include a semiconductor substrate including a semiconductor material such as monocrystalline silicon or monocrystalline germanium, and may be fabricated from (e.g., may include, at least in part, a silicon wafer). The peripheral region PERI may be formed in a region on the lower substrate l_sub. One or more peripheral transistors 22 may be included in the peripheral region PERI. One or more peripheral transistors 22 may include, at least in part, peripheral circuitry 60 of fig. 1, for example.
The peripheral circuit wiring may include, for example, a first peripheral conductive line PM1, a second peripheral conductive line PM2, and a third peripheral conductive line PM3 sequentially stacked on the lower substrate l_sub. In addition, the peripheral circuit wiring may further include a first peripheral contact PMC1 electrically interconnecting the one or more peripheral transistors 22 and the first peripheral conductive line PM1, a second peripheral contact PMC2 electrically interconnecting the first peripheral conductive line PM1 and the second peripheral conductive line PM2, and a third peripheral contact PMC3 electrically interconnecting the second peripheral conductive line PM2 and the third peripheral conductive line PM3.
The peripheral circuit wiring may further include a fourth peripheral contact PMC4 electrically interconnecting at least one of the third peripheral conductive lines PM3 and the first upper substrate 42. To reiterate, the fourth peripheral contact PMC4 may be a contact electrically connected to the first upper substrate. As shown in fig. 4A and 4B, the contact (PMC 4) may be electrically connected to the bottom surface of the first upper substrate 42. In some example embodiments, the contact (PMC 4) may be configured to transmit a voltage to the first upper substrate 42 based on the operation signal being applied to the memory cell array 50. For example, according to some example embodiments, the first upper substrate 42 may receive a power supply voltage through the fourth peripheral contact PMC4 based on an operation signal related to the memory cell array 50 being applied to the memory cell region MCA. The power supply voltage may be, for example, a power supply voltage supplied to the peripheral circuit 60 of fig. 1 included in the peripheral region PERI. The supply voltage may be referred to herein as a supply voltage associated with peripheral circuitry 60. Further, a ground voltage may be applied to the second upper substrate 46. To reiterate, the memory device 10 may be configured to apply the power supply voltage associated with the peripheral circuit 60 to the first upper substrate 42 based on the operation signal associated with the operation of the memory cell array 50 being applied to the memory cell region MCA.
According to some example embodiments, the first upper substrate 42 may be configured to receive the ground voltage through the fourth peripheral contact PMC4 based on an operation signal related to the memory cell array 50 being applied to the memory cell region MCA. According to some example embodiments, the presence of three types of peripheral conductive lines and four types of peripheral contacts is described, but the inventive concepts are not limited thereto.
The second semiconductor layer 30 may include an upper substrate u_sub, a memory cell array 50 on the upper substrate u_sub, and an upper insulating layer 34 that may cover the memory cell array 50 and the upper substrate u_sub. As referred to herein, an element "covering" another element is to be understood as enclosing the other element from exposure to the external environment. In addition, the second semiconductor layer 30 may further include an upper wiring electrically interconnecting the memory cell array 50 and the peripheral circuit wiring.
The upper substrate u_sub may be between the peripheral region PERI and the memory cell array 50. The upper substrate u_sub may be a support layer supporting the memory cell array 50. For example, the upper substrate u_sub may also be referred to as a base substrate.
As shown in fig. 4A, in some example embodiments, the memory device 10 includes a memory cell region MCA on the peripheral region PERI, wherein the memory cell region MCA includes an upper substrate u_sub, and the memory cell region MCA further includes a memory cell array 50 on the upper substrate u_sub.
The upper substrate u_sub may be divided into ("may include") a plurality of layers. According to some example embodiments, the upper substrate u_sub may include a first upper substrate 42 (e.g., the first upper substrate 42 on the peripheral region PERI), a first layer 44 on the first upper substrate 42, and a second upper substrate 46 on the first layer 44. In other words, the upper substrate u_sub may include the first upper substrate 42 and the second upper substrate 46 separated from each other, and the first layer 44 is between the first upper substrate 42 and the second upper substrate 46.
For example, the first upper substrate 42 may be a polysilicon layer doped with a first conductive type (e.g., p-type) impurity (e.g., a first conductive type impurity). In addition, the second upper substrate 46 may be a polysilicon layer doped with impurities of the same first conductive type as the first upper substrate 42. The impurities of the first conductivity type doped into the first and second upper substrates 42 and 46 may be the same impurities. The first layer 44 may be doped with a second conductivity type (e.g., n-type) impurity, wherein the second conductivity type is opposite to the first conductivity type.
The first and second upper substrates 42 and 46 may include a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or an epitaxial thin film substrate obtained by performing Selective Epitaxial Growth (SEG). The first and second upper substrates 42 and 46 may include a semiconductor material. For example, the first and second upper substrates 42 and 46 may include at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and combinations thereof.
The first layer 44 may be between the first upper substrate 42 and the second upper substrate 46. First layer 44 may include silicon oxide, silicon nitride, silicon oxynitride, gallium oxide, germanium oxide, a high-k dielectric material, or a combination thereof.
According to some example embodiments, the first layer 44 may be between the first upper substrate 42 and the second upper substrate 46 and constitute a dielectric layer. In this case, the first and second upper substrates 42 and 46 and the first layer 44 may constitute a capacitor. In other words, the first upper substrate 42 may constitute a lower electrode of the capacitor, the first layer 44 may constitute a dielectric layer of the capacitor, and the second upper substrate 46 may constitute an upper electrode of the capacitor. Further reiterating, the first layer 44 may include a dielectric layer, the memory device 10 may further include a capacitor, and the capacitor may include the first upper substrate 42, the second upper substrate 46, and the first layer 44.
The well region 48 may be formed in the second upper substrate 46. The well region 48 may be an n-type well formed by doping a portion of the second upper substrate 46 with a second conductivity type (e.g., n-type) impurity (e.g., a second conductivity type impurity). However, the inventive concept is not limited thereto, and the well region 48 may be a p-type well doped with the first conductive-type impurity. Further, the well region 48 may be formed by overlapping the first conductivity type well and the second conductivity type well with each other.
According to some example embodiments, the memory cell region MCA may be defined as a region ("limited portion" or "entire portion") of the well region 48. The memory cell region MCA may be a region of the well region 48 on which the memory cell array 50 including vertically stacked memory cells is disposed. In other words, a plurality of channel layers and gate conductive layers GS may be disposed on the well region 48 and constitute the memory cell array 50. As shown in fig. 4A, a plurality of gate conductive layers GS may be on the second upper substrate 46.
The memory cell array 50 may include a gate conductive layer GS stacked on the well region 48. The gate conductive layer GS may include a ground selection line GSL, word lines WL1 to WL4, and a string selection line SSL. The ground selection line GSL, the word lines WL1 to WL4, and the string selection line SSL may be sequentially stacked on the well region 48, and the insulating layer 52 may be disposed under or over each of the gate conductive layers GS. The gate conductive layer GS may decrease in area with increasing distance from the well region 48.
According to some example embodiments, four word lines are schematically illustrated as being formed. In some example embodiments, a different number of word lines may be stacked between the ground selection line GSL and the string selection line SSL in the vertical direction and the insulating layer 52 between adjacent word lines. In addition, two or more ground selection lines GSL and two or more string selection lines SSL may also be stacked in the vertical direction.
Meanwhile, the gate conductive layer GS may be separated by a word line cutting region WLC. A common source plug 54 extending in the vertical direction from the main surface of the well region 48 may be formed in the word line cutting region WLC. The common source plug 54 may be electrically connected to the well region 48. For example, the common source plug 54 may include at least one metal selected from tungsten (W), aluminum (Al), and copper (Cu).
Spacers 56 comprising an insulating material may be provided on two opposite sidewalls of the common source plug 54, thereby preventing an electrical connection between the common source plug 54 and the gate conductive layer GS. For example, the spacers 56 may include silicon oxide, silicon nitride, or silicon oxynitride.
The channel layer 57 may penetrate the gate conductive layer GS and the insulating layer 52, and may extend in a direction perpendicular to the top surface of the well region 48, and a bottom surface of the channel layer 57 may contact the top surface of the well region 48. The channel layers 57 may be disposed at a distance from each other between the word line cutting regions WLC. The channel layer 57 may be understood to extend in a direction perpendicular to the top surface of the second upper substrate 46, for example, as shown in fig. 4A.
The channel layer 57 may include impurity-doped polysilicon or polysilicon undoped with impurities. The channel layer 57 may have a vertically extending cup-like shape (or a bottom cylindrical shape), and a buried insulating layer 58 may be provided on an inner sidewall of the channel layer 57 to fill the channel layer 57. Buried insulating layer 58 may comprise an insulating material such as silicon oxide, or an air gap. In another example, the channel layer 57 may have a columnar shape, in which case the buried insulating layer 58 may not be formed.
The ground selection line GSL and a portion of the channel layer 57 adjacent to the ground selection line GSL may constitute a ground selection transistor (fig. 3). In addition, the word lines WL1 to WL4 and the portions of the channel layer 57 adjacent to the word lines WL1 to WL4 may constitute memory cells MC1 to MC8 (fig. 3). Further, the string selection line SSL and a portion of the channel layer 57 adjacent to the string selection line SSL may constitute a string selection transistor SST (fig. 3).
The drain region DR may be formed on the channel layer 57 and the buried insulating layer 58. For example, the drain region DR may include impurity-doped polysilicon. The drain region DR may also be referred to as a channel pad. The drain region DR may be electrically connected to the bit line BL through the second contact UMC2, the first conductive line UM1, and the third contact UMC 3.
An etch stop layer 53 may be disposed on sidewalls of the drain region DR. The top surface of the etch stop layer 53 may be disposed on the same level as the top surface of the drain region DR. The etch stop layer 53 may include an insulating material such as silicon nitride or silicon oxide.
The upper wiring may include, for example, a first conductive line UM1 and a second conductive line UM2 sequentially stacked in a vertical direction above the top surface of the memory cell array 50. The second conductive line UM2 may include a bit line BL. In addition, the upper wiring may further include a first contact UMC1 electrically interconnecting the third peripheral conductive line PM3 and the first conductive line UM1, a second contact UMC2 electrically interconnecting the memory cell array 50 and the first conductive line UM1, and a third contact UMC3 electrically interconnecting the first conductive line UM1 and the second conductive line UM2. According to some example embodiments, the presence of two types of conductive lines and three types of contacts is described, but the inventive concepts are not limited thereto.
For example, a power voltage may be applied to the first upper substrate 42 based on an operation signal applied to the memory cell array 50. To reiterate, the memory device 10 may be configured to apply the power supply voltage associated with the peripheral circuit 60 to the first upper substrate 42 based on the operation signal associated with the operation of the memory cell array 50 being applied to the memory cell region MCA. The power supply voltage may be, for example, a power supply voltage supplied to the peripheral circuit 60 (fig. 1) included in the peripheral region PERI. The first upper substrate 42 may receive a power supply voltage through, for example, the fourth peripheral contact PMC 4. Further, a ground voltage may be applied to the second upper substrate 46. Although not shown, the second upper substrate 46 may receive a ground voltage through a contact connected to the top surface of the second upper substrate 46. In some example embodiments, the memory device 10 may be configured to apply a ground voltage to the first upper substrate 42 (e.g., via the fourth peripheral contact PMC 4) based on an operation signal associated with operation of the memory cell array 50 being applied to the second upper substrate 46. In some example embodiments, the memory device 10 may be configured to apply a voltage to the first layer 44 based on an operation signal associated with an operation of the memory cell array 50 being applied to the second upper substrate 46, wherein the voltage has a magnitude greater than or equal to a magnitude of a ground voltage.
When the first layer 44 constitutes a dielectric layer, the first and second upper substrates 42 and 46 and the first layer 44 may constitute a capacitor to which a power supply voltage is supplied, suppress noise and/or ripple voltage of the power supply voltage, and attenuate voltage fluctuation due to instantaneous current. In other words, in addition to functioning as a support layer for the memory cell array 50, the upper substrate u_sub may function as a power capacitor (power-capacitor), thereby improving the integration of the memory device 10 and enabling an improvement in the performance of the memory device 10 based at least in part on the improved integration and/or the improved operating efficiency. Further, based at least in part on the increased integration of memory device 10, manufacturing efficiency and/or costs associated with manufacturing memory device 10 may be improved.
Fig. 5A is a cross-sectional view of a memory device 10a according to some example embodiments of the inventive concepts. Fig. 5B is an enlarged cross-sectional view of area a-2 of fig. 5A. The description of the components shown in fig. 5A, which is the same as that given above with reference to fig. 4A, will be omitted.
Referring to fig. 5A and 5B, the upper substrate u_sub may include a first upper substrate 42a, a first layer 44a, and a second upper substrate 46a, and the first upper substrate 42a may include one or more insulating layers IL. The insulating layer IL may include an insulating material such as silicon oxide.
According to some example embodiments, the first upper substrate 42a may be divided into a plurality of sections by one or more insulating layers IL. The plurality of sections separated by the insulating layer IL may include, for example, a first section 42a_1, a second section 42a_2, and a third section 42a_3.
According to some example embodiments, different types of power voltages may be applied to the first to third sections 42a_1 to 42a_3. Different types of supply voltages may refer to supply voltages having different levels ("magnitudes"), for example. Each of the different types of power supply voltages may be, for example, a power supply voltage supplied to the peripheral circuit 60 (fig. 1) included in the peripheral region PERI. As shown in fig. 5A, for example, different contacts (e.g., fourth peripheral contact PMC4, fifth peripheral contact PMC5A, and sixth peripheral contact PMC5 b) may be electrically connected to the first section 42a_1, the second section 42a_2, and the third section 42a_3, respectively.
For example, when the memory cell array 50 performs first to third operations different from each other ("performing the first to third operations different from each other based on the memory cell array 50"), a first level of power supply voltage may be applied to the first section 42a_1 during the first operation. The second level of power voltage may be applied to the second section 42a_2 during the second operation, and the third level of power voltage may be applied to the third section 42a_3 during the third operation. For example, the first to third sections 42a_1 to 42a_3 may receive different types of power supply voltages through different contacts (e.g., fourth, fifth and sixth peripheral contacts PMC4, PMC5a and PMC5 b) respectively. According to some example embodiments, only three sections including the first to third sections 42a_1 to 42a_3 have been described for convenience of explanation, but the inventive concept is not limited thereto.
For example, the fourth peripheral contact PMC4 may be configured to transmit a first voltage to the first section 42a_1 based on a first operation signal associated with a first operation of the memory cell array 50, and the fifth peripheral contact PMC5a may be configured to transmit a second voltage to the second section 42a_2 based on a second operation signal associated with a second operation of the memory cell array 50, wherein the second voltage has a different magnitude than the first voltage.
Fig. 6A is a cross-sectional view of a memory device 10b according to some example embodiments of the inventive concepts. Fig. 6B is an enlarged cross-sectional view of area a-3 of fig. 6A. The description of the components shown in fig. 6A, which is the same as the description given above with reference to fig. 4A, will be omitted.
Referring to fig. 6A and 6B, the upper substrate u_sub may include a first upper substrate 42B, a second upper substrate 46B, a third upper substrate 47B, a first layer 44B, and a second layer 45B. According to some example embodiments, the first layer 44b may be on the first upper substrate 42b, the second upper substrate 46b may be on the first layer 44b, the second layer 45b may be on the second upper substrate 46b, and the third upper substrate 47b may be on the second layer 45b. In other words, a plurality of layers, i.e., the first layer 44b and the second layer 45b, and the second upper substrate 46b may be between the first upper substrate 42b and the third upper substrate 47 b. According to some example embodiments, the well region 48b may be formed on the third upper substrate 47 b.
For example, the first to third upper substrates 42b, 46b and 47b may be polysilicon layers doped with one or more impurities of the same conductivity type (e.g., the first conductivity type). The first layer 44b may be between the first upper substrate 42b and the second upper substrate 46b and constitute a dielectric layer. In addition, the second layer 45b may be between the second upper substrate 46b and the third upper substrate 47b and constitute a dielectric layer. Accordingly, the first upper substrate 42b, the first layer 44b, and the second upper substrate 46b may constitute a capacitor (e.g., the memory device 10b may include a capacitor, wherein the capacitor includes the first upper substrate 42b, the second upper substrate 46b, and the first layer 44 b). In other words, the first upper substrate 42b may constitute a lower electrode of the capacitor, the first layer 44b may constitute a dielectric layer of the capacitor, and the second upper substrate 46b may constitute an upper electrode of the capacitor. The second layer 45b may include polysilicon doped with impurities of a second conductivity type opposite to the first conductivity type doped with one or more impurities of the first to third upper substrates 42b, 46b and 47 b.
In addition, the second upper substrate 46b, the second layer 45b, and the third upper substrate 47b may constitute a capacitor. In other words, the second upper substrate 46b may constitute a lower electrode of the capacitor, the second layer 45b may constitute a dielectric layer of the capacitor, and the third upper substrate 47b may constitute an upper electrode of the capacitor.
Fig. 7 is a cross-sectional view of a memory device 10c according to some example embodiments of the inventive concepts. The description of the components shown in fig. 7, which is the same as that given above with reference to fig. 4A, will be omitted.
Referring to fig. 7, the upper substrate u_sub may include a first upper substrate 42c, a first layer 44c on the first upper substrate 42c, and a second upper substrate 46c on the first layer 44c. In other words, the upper substrate u_sub may include the first and second upper substrates 42c and 46c separated from each other and the first layer 44c between the first and second upper substrates 42c and 46c.
According to some example embodiments, the first and second upper substrates 42c and 46c may be polysilicon layers doped with first conductivity type (e.g., p-type) impurities, and the first layer 44c may be polysilicon layers doped with second conductivity type (e.g., n-type) impurities. In another example, the first and second upper substrates 42c and 46c may be doped with a second conductivity type (e.g., n-type) impurity, and the first layer 44c may be doped with a first conductivity type (e.g., p-type) impurity.
The first layer 44c may include a semiconductor material, such as at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and combinations thereof. The first layer 44c may be provided by using, for example, polysilicon doped with a second conductivity type (e.g., n-type) impurity via a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, or the like. During the process of disposing the first layer 44c, the first layer 44c may be in situ doped with the second conductive type impurity. In some example embodiments, after the first layer 44c is disposed, the first layer 44c may be doped with the second conductive type impurity through an ion implantation operation.
The common source region 49c may be disposed on the second upper substrate 46 c. For example, the common source region 49c may be an impurity region densely doped with a second conductive type (e.g., n-type) impurity. The common source region 49c may be electrically connected to the common source plug 54. The second upper substrate 46c and the common source region 49c may constitute a p-n junction diode. The common source region 49c may serve as a source region for supplying current to memory cells included in the memory cell array 50.
According to some example embodiments, the memory cell region MCA may be a region on the second upper substrate 46c in which a memory cell array 50c including vertically stacked memory cells is disposed. According to some example embodiments, the first contact UMC1 in the upper wiring may electrically interconnect the first conductive line UM1 and the third peripheral conductive line PM3, electrically interconnect the first conductive line UM1 and the first layer 44c, or electrically interconnect the first conductive line UM1 and the second upper substrate 46 c.
According to some example embodiments, when an operation signal is applied to the memory cell array 50, a ground voltage may be applied to the first upper substrate 42c, and a first voltage having a level higher than or equal to that of the ground voltage may be applied to the first layer 44c. To reiterate, in some example embodiments, the memory device 10c may be configured to apply a ground voltage to the first upper substrate 42c (e.g., via the fourth peripheral contact PMC 4) based on an operation signal associated with operation of the memory cell array 50 being applied to the second upper substrate 46c, and the memory device 10c may be configured to apply a voltage to the first layer 44c (e.g., via the first contact UMC1 electrically connected to the first layer 44c as shown in fig. 7) having a magnitude greater than or equal to a magnitude of the ground voltage. Further, various operation signals having various levels ("magnitudes") may be applied to the second upper substrate 46c. According to some example embodiments, the first voltage may have the same level as the operation signal applied to the second upper substrate 46c.
The first upper substrate 42c may receive the ground voltage through the fourth peripheral contact PMC 4. Further, the first layer 44c may receive the first voltage through the first contact UMC1 connected to the top surface of the first layer 44 c. Further, the second upper substrate 46c may receive various operation signals having various levels through the first contact UMC1 connected to the top surface of the second upper substrate 46 c.
For example, an erase voltage may be applied to the first layer 44c and the second upper substrate 46c through the first contact UMC1 connected to the top surfaces of the first layer 44c and the second upper substrate 46c, respectively, and a ground voltage or a voltage close to the ground voltage may be applied to the gate conductive layer GS, thereby performing a block-by-block erase operation on blocks included in the memory cell array 50. In this case, the first upper substrate 42c may receive the ground voltage through the fourth peripheral contact PMC 4.
According to some example embodiments, when an operation signal is applied to the second upper substrate 46c, the first upper substrate 42c may be in a grounded state, and the first upper substrate 42c and the first layer 44c may constitute a p-n junction diode having a reverse bias. Accordingly, the first upper substrate 42c and the first layer 44c can prevent electrical interference such as crosstalk generated by the third peripheral conductive line PM3 in the second upper substrate 46 c. As a result, by reducing degradation of electrical properties due to unnecessary coupling, electrical stability of the memory device and thus performance of the memory device can be improved.
Fig. 8 is a cross-sectional view of a memory device 10d according to some example embodiments of the inventive concepts. The description of the components shown in fig. 8, which is the same as that given above with reference to fig. 4A and 7, will be omitted.
Referring to fig. 8, the upper substrate u_sub may include a first upper substrate 42d, a first layer 44d stacked on the first upper substrate 42d, and a second upper substrate 46d stacked on the first layer 44 d. According to some example embodiments, the first and second upper substrates 42d and 46d may be polysilicon layers doped with first conductivity type (e.g., p-type) impurities, and the first layer 44d may be polysilicon layers doped with second conductivity type (e.g., n-type) impurities.
The first and second well regions 48d_1 and 48d_2 may be formed on the second upper substrate 46 d. According to some example embodiments, the first well region 48d_1 may be formed by doping a portion of the second upper substrate 46d with a second conductive-type (e.g., n-type) impurity, and the second well region 48d_2 may be formed by doping a portion of the first well region 48d_1 with a first conductive-type (e.g., p-type) impurity. The first well region 48d_1 may have a well structure surrounding the second well region 48d_2 such that the first well region 48d_1 occupies a portion of the second upper substrate 46d and the second well region 48d_2 occupies a portion of the first well region 48d_1. For example, the second well region 48d_2 may be referred to as a pocket well (pocket well), and the first well region 48d_1 may be referred to as a deep well surrounding the pocket well. According to some example embodiments, the memory cell region MCA may be defined as a region of the second well region 48d_2.
The first well region 48d_1 may electrically and spatially separate the second well region 48d_2 from the second upper substrate 46 d. For example, when an operation signal is applied to the second well region 48d_2, a ground voltage may be applied to the second upper substrate 46d, and a first voltage having a level higher than or equal to the ground voltage may be applied to the first well region 48d_1. According to some example embodiments, the first voltage may have the same level ("magnitude") as the operation signal applied to the second well region 48d_2.
For example, the first well region 48d_1 may receive the first voltage through a first contact UMC1 connected to a top surface of the first well region 48d_1. Further, the second well region 48d_2 may receive an operation signal through the first contact UMC1 connected to the top surface of the second well region 48d_2. Although not shown, the first and second well regions 48d_1 and 48d_2 may each include a junction region for electrical connection with the first contact UMC 1. For example, the junction regions may have a higher doping concentration than the doping concentration of each well region.
Fig. 9 is a cross-sectional view of a memory device 10e according to some example embodiments of the inventive concepts. The description of the components shown in fig. 9, which is the same as that given above with reference to fig. 4A and 6A, will be omitted.
Referring to fig. 9, the upper substrate u_sub may include a first upper substrate 42e, a second upper substrate 46e, a third upper substrate 47e, a first layer 44e, and a second layer 45e. According to some example embodiments, a first layer 44e may be stacked on the first upper substrate 42e, a second upper substrate 46e may be on the first layer 44e, a second layer 45e may be on the second upper substrate 46e, and a third upper substrate 47e may be on the second layer 45e. According to some example embodiments, the memory cell region MCA may be a region on the third upper substrate 47e in which the memory cell array 50 including vertically stacked memory cells is disposed.
According to some example embodiments, the first to third upper substrates 42e, 46e and 47e may be polysilicon layers doped with a first conductive type (e.g., p-type) impurity, and the first layer 44e may be between the first upper substrate 42e and the second upper substrate 46e and may constitute a dielectric layer. In addition, the second layer 45e may be a polysilicon layer doped with a second conductive type (e.g., n-type) impurity.
Accordingly, the first upper substrate 42e, the first layer 44e, and the second upper substrate 46e may constitute a capacitor. In other words, the first upper substrate 42e may constitute a lower electrode of the capacitor, the first layer 44e may constitute a dielectric layer of the capacitor, and the second upper substrate 46e may constitute an upper electrode of the capacitor.
According to some example embodiments, various power voltages may be applied to the first upper substrate 42e through the fourth peripheral contact PMC 4. Further, the ground voltage may be applied to the second upper substrate 46e through the first contact UMC1 connected to the top surface of the second upper substrate 46e. A first voltage having a level higher than or equal to the ground voltage may be applied to the second layer 45e through the first contact UMC1 connected to the top surface of the second layer 45e. Further, various operation signals having various levels may be applied to the third upper substrate 47e through the first contact UMC1 connected to the top surface of the third upper substrate 47e. According to some example embodiments, the first voltage may have the same level as various operation signals applied to the third upper substrate 47e.
To reiterate, in some example embodiments, the memory device 10e includes a first contact UMC1, the first contact UMC1 penetrating the second layer 45e and the third upper substrate 47e and extending in a direction perpendicular to a top surface of the second upper substrate 46e, wherein the memory device 10e is configured to apply a ground voltage to the second upper substrate 46e through the first contact UMC1 based on an operation signal applied to the memory cell array 50.
Fig. 10 is a cross-sectional view of a memory device 10f according to some example embodiments of the inventive concepts. The description of the components shown in fig. 9, which is the same as the description given above with reference to fig. 4A, will be omitted.
Referring to fig. 10, the memory cell array 50f may include a gate conductive layer GS stacked on the well region 48 f. The gate conductive layer GS may include a back gate BG, first to eighth word lines WL1 to WL8, a string selection line SSL, and a ground selection line GSL.
The memory cell array 50f may further include a channel layer 57f penetrating the gate conductive layer GS in a U shape and a buried insulating layer 58f. The first end of the channel layer 57f and the buried insulating layer 58f having a U shape may be electrically connected to the bit line BL through the drain region DR, the second contact UMC2, the first conductive line UM1 and the third contact UMC3, and the second end of the channel layer 57f and the buried insulating layer 58f having a U shape may be electrically connected to the common source line CSL through the drain region DR and the second contact UMC 2.
Specifically, the back gate BG may be on the well region 48 f. An insulating layer 52f may be between the back gate BG and the well region 48 f. The fifth to eighth word lines WL5 to WL8 and the ground selection line GSL may be sequentially stacked between the back gate BG and the drain region DR connected to the common source line CSL. The first to fourth word lines WL1 to WL4 and the string selection line SSL may be sequentially stacked between the back gate BG and the drain region DR connected to the bit line BL. For example, one U-shaped channel layer 57f and a "U" shaped gate conductive layer GS along the "U" shaped channel layer 57f may constitute a single memory cell string.
Fig. 11A to 11I are cross-sectional views sequentially illustrating operations for describing a method of manufacturing a memory device according to some example embodiments of the inventive concepts. The method of manufacturing a memory device according to some example embodiments may be, for example, a method of manufacturing the memory device 10 described above with reference to fig. 4A.
Referring to fig. 11A, a peripheral region PERI may be formed in a portion of the lower substrate l_sub. For example, in peripheral region PERI, one or more peripheral transistors 22 may be formed. Although not shown, a p-type well for a peripheral circuit and/or an n-type well for a peripheral circuit may be formed in the lower substrate l_sub through a plurality of ion implantation operations. For example, the p-type well for the peripheral circuit may be an NMOS transistor forming region, and the n-type well for the peripheral circuit may be a PMOS transistor forming region.
After the one or more peripheral transistors 22 are formed, peripheral circuit wirings including the first to fourth peripheral contacts PMC1 to PMC4 and the first to third peripheral conductive lines PM1 to PM3 may be formed, and a lower insulating layer 24 capable of insulating the peripheral circuit wirings from each other may be formed. According to some example embodiments, the lower insulating layer 24 may include a plurality of interlayer insulating layers, and may further include one or more etch stop layers. According to the operation described with reference to fig. 11A, the first semiconductor layer 20 may be formed.
Referring to fig. 11B, a first upper substrate 42 may be formed on the first semiconductor layer 20. The first upper substrate 42 may be formed through a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, or the like by using polysilicon doped with a first conductive type (e.g., p-type) impurity. During the operation for forming the first upper substrate 42, the first upper substrate 42 may be in-situ doped with the first conductive type impurity. In some example embodiments, after the first upper substrate 42 is formed, the first upper substrate 42 may be doped with the first conductive type impurity through an ion implantation operation.
Referring to fig. 11C, a first layer 44 may be formed on the first upper substrate 42. First layer 44 may include silicon oxide, silicon nitride, silicon oxynitride, gallium oxide, germanium oxide, a high-k dielectric material, or a combination thereof. According to some example embodiments, the first layer 44 may be a polysilicon layer doped with a second conductivity type (e.g., n-type) impurity (e.g., a conductivity type opposite the first conductivity type). Doping of first layer 44 may be performed as part of forming first layer 44.
Referring to fig. 11D, a second upper substrate 46 may be formed on the first layer 44. The second upper substrate 46 may be, for example, a polysilicon layer doped with the first conductive type impurity. The second upper substrate 46 may be formed by the same operation as that for forming the first upper substrate 42.
Referring to fig. 11E, a memory cell region MCA may be formed on the second upper substrate 46. The memory cell region MCA may be formed by forming a well region 48 in a portion of the second upper substrate 46. For example, the well region 48 may be formed by doping a portion of the second upper substrate 46 with the second conductive-type impurity. The second upper substrate 46 may be doped with impurities through an ion implantation operation.
Referring to fig. 11F, a preliminary gate stack structure 70 may be formed by alternately stacking the insulating layer 52 and the first to sixth preliminary gate layers 71 to 76 (the first, second, third, fourth, fifth and sixth preliminary gate layers 71, 72, 73, 74, 75 and 76) on the second upper substrate 46. For example, the insulating layer 52 may be formed to a certain height by using silicon oxide, silicon nitride, or silicon oxynitride.
The first to sixth preliminary gate layers 71 to 76 may be formed to a certain height by using silicon nitride, silicon carbide, or polysilicon. The first to sixth preliminary gate layers 71 to 76 may be preliminary layers or sacrificial layers for forming the ground selection line GSL (fig. 4A), the plurality of word lines WL1 to WL4 (fig. 4A), and the string selection line SSL (fig. 4A) in a subsequent operation. The number of preliminary gate layers may be appropriately selected according to the number of ground selection lines, word lines, and string selection lines.
Referring to fig. 11G, a channel layer 57 and a buried insulating layer 58 penetrating the preliminary gate stack structure 70 above the well region 48 and extending in a direction perpendicular to the main surface of the second upper substrate 46 may be formed. For example, the channel layer 57 may be formed in a channel hole penetrating the preliminary gate stack structure 70 through a chemical vapor deposition process, an atomic layer deposition process, or a physical vapor deposition process by using impurity-doped polysilicon. In some example embodiments, the channel layer 57 may be formed by using polysilicon that is not doped with impurities. The buried insulating layer 58 may be formed in the channel hole in which the channel layer 57 is formed through a chemical vapor deposition process, an atomic layer deposition process, or a physical vapor deposition process by using an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.
Next, an etch stop layer 53 covering the channel layer 57 and the top surface of the buried insulating layer 58 may be formed on the preliminary gate stack structure 70. The etch stop layer 53 may be formed by using silicon nitride, silicon oxide, or silicon oxynitride.
After a drain hole is formed in the etch stop layer 53 to expose the channel layer 57 and the top surface of the buried insulating layer 58, a conductive layer (not shown) filling the drain hole may be formed, and the top surface of the conductive layer may be planarized, thereby forming the drain region DR. For example, the top surface of the drain region DR may be formed on the same level as the top surface of the etch stop layer 53.
Referring to fig. 11H, a word line cut region WLC penetrating the plurality of insulating layers 52 and the preliminary gate stack structure 70 and exposing the well region 48 may be formed. The first to sixth preliminary gate layers 71 to 76 may be replaced with a plurality of gate conductive layers GS, for example, ground selection lines GSL, first to fourth word lines WL1 to WL4, and string selection lines SSL.
According to some embodiments for replacing the first to sixth preliminary gate layers 71 to 76 with the ground selection line GSL, the first to fourth word lines WL1 to WL4, and the string selection line SSL, when the first to sixth preliminary gate layers 71 to 76 include polysilicon, a silicidation operation may be performed with respect to the first to sixth preliminary gate layers 71 to 76. In this case, the ground selection line GSL, the first to fourth word lines WL1 to WL4, and the string selection line SSL may include tungsten silicide, tantalum silicide, cobalt silicide, or nickel silicide. However, the inventive concept is not limited thereto.
According to some further embodiments, after the first to sixth preliminary gate layers 71 to 76 exposed through the word line cutting region WLC are selectively removed, a conductive material may be buried in the space formed between the insulating layers 52, thereby forming the ground selection line GSL, the first to fourth word lines WL1 to WL4, and the string selection line SSL. In this case, the ground selection line GSL, the first to fourth word lines WL1 to WL4, and the string selection line SSL may be formed by using metals such as tungsten, tantalum, cobalt, and nickel.
Referring to fig. 11I, a common source plug 54 and a spacer 56 may be formed in each of the plurality of word line cutting regions WLC. The spacers 56 may comprise silicon oxide, silicon nitride, or silicon oxynitride. The common source plug 54 may include a conductive material. For example, the common source plug 54 may include at least one metal selected from tungsten (W), aluminum (Al), and copper (Cu). According to some embodiments, a metal silicide layer for reducing contact resistance may be present between the common source plug 54 and the well region 48. For example, the metal silicide layer may include cobalt silicide.
Thereafter, a plurality of patterning processes using a mask (not shown) may be performed to patternwise select the line GSL, the first to fourth word lines WL1 to WL4, and the string select line SSL. Each of the insulating layers 52 may be patterned to align with an adjacent gate conductive layer GS. Thus, the memory cell array 50 may be formed.
Next, an upper wiring including the first to third contacts UMC1 to UMC3 and the first and second conductive lines UM1 and UM2, and an upper insulating layer 34 may be formed. The second conductive line UM2 may include a bit line BL. The upper insulating layer 34 may cover the upper wiring, the memory cell array 50, and the upper substrate u_sub. According to the operations described above with reference to fig. 11B to 11I, the second semiconductor layer 30 may be formed.
Fig. 12 is a block diagram illustrating a Solid State Drive (SSD) system 1000 including a storage device according to some example embodiments of the inventive concepts.
Referring to fig. 12, SSD system 1000 may include a host 1100 and an SSD 1200.SSD 1200 may send/receive signals to/from host 1100 through a signal connector and may receive power through a power connector.
SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1220, and a plurality of storage devices 1230, 1240, and 1250. Each of the plurality of memory devices 1230, 1240, and 1250 may be a vertically stacked NAND flash memory device and may be implemented according to the embodiments described above with reference to fig. 1 through 11I. Accordingly, each of the plurality of memory devices 1230, 1240, and 1250 may exhibit high integration and have improved electrical stability.
While the present inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.
The present application claims the benefit of korean patent application No. 10-2017-0107407 filed in the korean intellectual property office on 24 th month of 2017, the disclosure of which is incorporated herein by reference in its entirety.

Claims (21)

1.A non-volatile memory device, comprising:
a first semiconductor layer including a peripheral region including one or more peripheral transistors on a lower substrate;
a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate, the second semiconductor layer further including a memory cell array on the upper substrate, the upper substrate including:
a first upper substrate on the first semiconductor layer,
A first layer on the first upper substrate, and
A second upper substrate on the first layer, and
A contact extending through a portion of the first semiconductor layer to contact a bottom surface of the first upper substrate to be electrically connected to the first upper substrate, the contact configured to transmit a voltage to the first upper substrate but not to the memory cell array based on an operation signal applied to the memory cell array.
2. The non-volatile memory device of claim 1, wherein
The first layer includes a dielectric layer, and
The nonvolatile memory device further includes a capacitor including the first upper substrate, the second upper substrate, and the first layer.
3. The non-volatile memory device of claim 1, wherein
The first upper substrate includes one or more insulating layers, and
The first upper substrate includes a first section and a second section separated by the one or more insulating layers.
4. The non-volatile memory device of claim 3, further comprising:
A first contact electrically connected to the first section, the first contact being applied to the memory cell array based on a first operation signal associated with a first operation of the memory cell array, the first contact being configured to transmit a first voltage to the first section; and
A second contact electrically connected to the second section, the second contact being applied to the memory cell array based on a second operation signal associated with a second operation of the memory cell array, the second contact being configured to transmit a second voltage to the second section, the second voltage having a magnitude different from a magnitude of the first voltage,
Wherein the contact is one of the first contact and the second contact.
5. The non-volatile memory device of claim 1, wherein
The first upper substrate and the second upper substrate are doped with impurities of a first conductivity type, and
The first layer is doped with impurities of a second conductivity type, and
The second conductivity type is opposite the first conductivity type.
6. The nonvolatile memory device according to claim 1, wherein the nonvolatile memory device is configured to apply a ground voltage to the first upper substrate based on an operation signal associated with an operation of the memory cell array being applied to the second upper substrate.
7. The nonvolatile memory device according to claim 6, wherein, based on the operation signal associated with the operation of the memory cell array being applied to the second upper substrate, the nonvolatile memory device is configured to apply a voltage to the first layer, the voltage having a magnitude greater than or equal to a magnitude of the ground voltage.
8. The non-volatile memory device of claim 1, wherein
The second upper substrate is doped with impurities of the first conductivity type, and
The second upper substrate includes a first well region occupying a portion of the second upper substrate, the first well region being doped with impurities of a second conductivity type opposite to the first conductivity type, and a second well region occupying a portion of the first well region, the second well region being doped with impurities of the first conductivity type.
9. The nonvolatile memory device according to claim 1, wherein the memory cell array comprises:
a plurality of gate conductive layers on the second upper substrate, and
And a plurality of channel layers penetrating the plurality of gate conductive layers, the plurality of channel layers extending in a direction perpendicular to a top surface of the second upper substrate.
10. A non-volatile memory device, comprising:
a lower substrate;
a peripheral region on the lower substrate, the peripheral region including peripheral circuitry on the lower substrate;
a memory cell region on the peripheral region, the memory cell region including an upper substrate, the memory cell region further including a memory cell array on the upper substrate, the upper substrate including:
a first upper substrate, on which a first upper substrate is disposed,
A second upper substrate above the first upper substrate, and
A first layer between the first upper substrate and the second upper substrate, and
A first contact extending through a portion of the lower insulating layer between the upper substrate and the lower substrate to contact a bottom surface of the first upper substrate to be electrically connected to the first upper substrate, the first contact configured to transmit a voltage to the first upper substrate but not to the memory cell array based on an operation signal applied to the memory cell array.
11. The non-volatile memory device of claim 10, wherein the upper substrate further comprises:
a second layer on the second upper substrate, and
And a third upper substrate on the second layer.
12. The non-volatile memory device of claim 11, wherein
The first layer includes a dielectric layer, and
The nonvolatile memory device further includes a capacitor including the first upper substrate, the second upper substrate, and the first layer.
13. The non-volatile memory device of claim 11, further comprising:
a second contact penetrating the second layer and the third upper substrate and extending in a direction perpendicular to a top surface of the second upper substrate,
Wherein the nonvolatile memory device is configured to apply a ground voltage to the second upper substrate through the second contact based on the operation signal being applied to the memory cell array.
14. The non-volatile memory device of claim 11, wherein
The first upper substrate, the second upper substrate, and the third upper substrate include polysilicon doped with impurities of a first conductivity type, and
The second layer includes polysilicon doped with impurities of a second conductivity type, the second conductivity type being opposite the first conductivity type.
15. The nonvolatile memory device according to claim 10, wherein the nonvolatile memory device is configured to apply a power supply voltage associated with the peripheral circuit to the first upper substrate based on an operation signal associated with an operation of the memory cell array being applied to the memory cell region.
16. A non-volatile memory device, comprising:
A memory cell region including a memory cell array;
a peripheral region including a peripheral circuit, the memory cell region being on the peripheral region; and
An upper substrate between the peripheral region and the memory cell array, the upper substrate comprising:
a first upper substrate on the peripheral region,
A first layer on the first upper substrate, and
A second upper substrate on the first layer, and
A contact extending through a portion of the lower insulating layer under the upper substrate to contact a bottom surface of the first upper substrate to be electrically connected to the first upper substrate, the contact configured to transmit a voltage to the first upper substrate but not to the memory cell array based on an operation signal applied to the memory cell array.
17. The non-volatile memory device of claim 16, wherein
The first layer includes a dielectric layer, and
The nonvolatile memory device is configured to apply a power supply voltage associated with the peripheral circuit to the first upper substrate based on an operation signal associated with an operation of the memory cell array being applied to the memory cell region.
18. The non-volatile memory device of claim 16, wherein the peripheral circuitry comprises at least one instance of circuitry corresponding to a row decoder, a page buffer, and control logic.
19. A method of manufacturing a non-volatile memory device, the method comprising:
forming one or more peripheral transistors on a portion of a lower substrate, the one or more peripheral transistors being connected to a plurality of peripheral circuit wirings, a lower insulating layer covering the one or more peripheral transistors and the peripheral circuit wirings;
forming a first upper substrate on the lower insulating layer;
forming a first layer on the first upper substrate;
forming a second upper substrate on the first layer;
Forming a memory cell region on the second upper substrate, the memory cell region including a memory cell array; and
A contact is formed extending through a portion of the lower insulating layer to contact a bottom surface of the first upper substrate to be electrically connected to the first upper substrate, the contact being configured to transmit a voltage to the first upper substrate but not to the memory cell array based on an operation signal being applied to the memory cell array.
20. The method of claim 19, wherein
The forming of the first upper substrate includes doping the first upper substrate with an impurity having a first conductivity type, and
The forming of the first layer includes doping the first layer with an impurity having a second conductivity type, the second conductivity type being opposite the first conductivity type.
21. The method of claim 19, wherein the forming of the memory cell region comprises forming a plurality of gate conductive layers on the second upper substrate and a plurality of channel layers penetrating the plurality of gate conductive layers, the plurality of channel layers extending in a direction perpendicular to a top surface of the second upper substrate.
CN201810933109.9A 2017-08-24 2018-08-16 Nonvolatile memory device and method of manufacturing the same Active CN109427800B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2017-0107407 2017-08-24
KR1020170107407A KR102308776B1 (en) 2017-08-24 2017-08-24 Non volatile memory devices and method of fabricating the same

Publications (2)

Publication Number Publication Date
CN109427800A CN109427800A (en) 2019-03-05
CN109427800B true CN109427800B (en) 2024-05-24

Family

ID=65437849

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810933109.9A Active CN109427800B (en) 2017-08-24 2018-08-16 Nonvolatile memory device and method of manufacturing the same

Country Status (4)

Country Link
US (2) US10559577B2 (en)
KR (1) KR102308776B1 (en)
CN (1) CN109427800B (en)
SG (1) SG10201804119SA (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG11201802573UA (en) * 2016-01-13 2018-04-27 Toshiba Memory Corp Semiconductor memory device
US10374092B2 (en) * 2017-04-17 2019-08-06 Globalfoundries Inc. Power amplifier ramping and power control with forward and reverse back-gate bias
JP2020038911A (en) * 2018-09-05 2020-03-12 キオクシア株式会社 Semiconductor memory device and method for manufacturing semiconductor memory device
CN110896669B (en) * 2018-12-18 2021-01-26 长江存储科技有限责任公司 Multi-stack three-dimensional memory device and method of forming the same
CN110896668B (en) 2018-12-18 2021-07-20 长江存储科技有限责任公司 Multi-stack three-dimensional memory device and method of forming the same
JP2020150147A (en) * 2019-03-14 2020-09-17 キオクシア株式会社 Semiconductor storage device
KR20200115804A (en) * 2019-03-26 2020-10-08 삼성전자주식회사 Semiconductor memory device including parallel structure
KR20210095293A (en) 2020-01-22 2021-08-02 삼성전자주식회사 Three dimensional semiconductor memory device and method for manufacturing the same
JP7451567B2 (en) 2020-01-28 2024-03-18 長江存儲科技有限責任公司 Three-dimensional memory device and method for forming a three-dimensional memory device
KR20220002575A (en) * 2020-01-28 2022-01-06 양쯔 메모리 테크놀로지스 씨오., 엘티디. Three-dimensional memory devices and method of forming the same
KR20210115524A (en) 2020-03-13 2021-09-27 삼성전자주식회사 Semiconductor memory device and method of fabricating the same
KR20220057834A (en) 2020-10-30 2022-05-09 삼성전자주식회사 Semiconductor device and massive data storage system including the same
KR20220138906A (en) * 2021-04-06 2022-10-14 삼성전자주식회사 Three-dimensional semiconductor memory device and electronic system including the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120131682A (en) * 2011-05-26 2012-12-05 에스케이하이닉스 주식회사 Nonvolatile memory device and method for fabricating the same
CN106469729A (en) * 2015-08-19 2017-03-01 三星电子株式会社 Nonvolatile memory devices and its Nonvolatile memory system of inclusion
US9691782B1 (en) * 2016-04-29 2017-06-27 Samsung Electronics Co., Ltd. Non-volatile memory device

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003309192A (en) 2002-04-17 2003-10-31 Fujitsu Ltd Nonvolatile semiconductor memory and method of manufacturing the same
KR100629265B1 (en) 2004-08-04 2006-09-29 삼성전자주식회사 method of forming a conductive layer including a local high resistivity region and semiconductor device fabricated using the same
DE102005023122A1 (en) 2005-05-19 2006-11-23 Infineon Technologies Ag Integrated circuit arrangement with layer stack and method
US7704832B2 (en) 2007-04-02 2010-04-27 Sandisk Corporation Integrated non-volatile memory and peripheral circuitry fabrication
JP2009266944A (en) 2008-04-23 2009-11-12 Toshiba Corp Three-dimensional stacked nonvolatile semiconductor memory
JP5297342B2 (en) 2009-11-02 2013-09-25 株式会社東芝 Nonvolatile semiconductor memory device
JP5603834B2 (en) 2011-06-22 2014-10-08 株式会社東芝 Semiconductor memory device and manufacturing method thereof
KR102128469B1 (en) * 2013-11-08 2020-06-30 삼성전자주식회사 Semiconductor devices
KR102179284B1 (en) * 2014-05-12 2020-11-18 삼성전자주식회사 Nonvolatile memory device and erasing method thereof
KR102307487B1 (en) 2014-06-23 2021-10-05 삼성전자주식회사 Three-dimensional semiconductor memory device and method of fabricating the same
KR102259943B1 (en) * 2014-12-08 2021-06-04 삼성전자주식회사 Nonvolatile memory device including multi-plane
KR102264675B1 (en) 2014-12-09 2021-06-15 삼성전자주식회사 Semiconductor device
US10134750B2 (en) 2014-12-30 2018-11-20 Toshiba Memory Corporation Stacked type semiconductor memory device and method for manufacturing the same
US20160240547A1 (en) 2015-02-18 2016-08-18 Kabushiki Kaisha Toshiba Semiconductor memory device
KR20160124294A (en) 2015-04-16 2016-10-27 삼성전자주식회사 Semiconductor device including cell region stacked on periperal region and methods for fabricating the same
KR102398665B1 (en) * 2015-05-07 2022-05-16 삼성전자주식회사 Non volatile memory devices and method of fabricating the same
KR102415401B1 (en) 2015-05-21 2022-07-01 삼성전자주식회사 3-dimsional semiconductor memory device and operation method thereof
KR102437779B1 (en) 2015-08-11 2022-08-30 삼성전자주식회사 Three dimensional semiconductor device
US9455271B1 (en) 2015-08-13 2016-09-27 Kabushiki Kaisha Toshiba Semiconductor memory device and method of manufacturing semiconductor memory device and method of layouting auxiliary pattern
KR102452826B1 (en) * 2015-11-10 2022-10-12 삼성전자주식회사 Memory device
US9853047B2 (en) 2016-01-26 2017-12-26 SK Hynix Inc. Semiconductor device and method of manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120131682A (en) * 2011-05-26 2012-12-05 에스케이하이닉스 주식회사 Nonvolatile memory device and method for fabricating the same
CN106469729A (en) * 2015-08-19 2017-03-01 三星电子株式会社 Nonvolatile memory devices and its Nonvolatile memory system of inclusion
US9691782B1 (en) * 2016-04-29 2017-06-27 Samsung Electronics Co., Ltd. Non-volatile memory device

Also Published As

Publication number Publication date
KR20190021934A (en) 2019-03-06
US20200168620A1 (en) 2020-05-28
SG10201804119SA (en) 2019-03-28
US10559577B2 (en) 2020-02-11
US20190067308A1 (en) 2019-02-28
KR102308776B1 (en) 2021-10-05
CN109427800A (en) 2019-03-05
US10964710B2 (en) 2021-03-30

Similar Documents

Publication Publication Date Title
CN109427800B (en) Nonvolatile memory device and method of manufacturing the same
US11515413B2 (en) 3D semiconductor device and structure with memory
KR102400100B1 (en) Non volatile memory devices and method of fabricating the same
CN106469729B (en) Nonvolatile memory device and nonvolatile memory system including the same
US11706923B2 (en) Semiconductor memory device and a method of manufacturing the same
US20220165749A1 (en) Semiconductor devices and manufacturing methods of the same
CN107464816B (en) Memory device and method of manufacturing the same
US20190319038A1 (en) Semiconductor devices
US11177273B2 (en) Nonvolatile memory device including row decoder
KR102398665B1 (en) Non volatile memory devices and method of fabricating the same
US8923057B2 (en) Three-dimensional semiconductor memory device with active patterns and electrodes arranged above a substrate
KR102282139B1 (en) Semiconductor devices
US8115259B2 (en) Three-dimensional memory device
CN109087919B (en) Semiconductor device with a semiconductor layer having a plurality of semiconductor layers
CN111739889B (en) Semiconductor memory device with a memory cell having a memory cell with a memory cell having a memory cell
JP2019186349A (en) Flash memory and method of fabricating the same
CN110504272B (en) Semiconductor device with a semiconductor device having a plurality of semiconductor chips
KR102686101B1 (en) Three dimensional semiconductor memory device and method for manufacturing the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant