CN109427614B - Wafer, manufacturing method thereof and electronic device - Google Patents
Wafer, manufacturing method thereof and electronic device Download PDFInfo
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- CN109427614B CN109427614B CN201710780544.8A CN201710780544A CN109427614B CN 109427614 B CN109427614 B CN 109427614B CN 201710780544 A CN201710780544 A CN 201710780544A CN 109427614 B CN109427614 B CN 109427614B
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67282—Marking devices
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Abstract
The invention provides a wafer, a manufacturing method thereof and an electronic device. The method comprises the following steps: providing a silicon ingot; forming a linear film layer mark for marking the crystal direction of the silicon crystal ingot on the side surface of the silicon crystal ingot; slicing the silicon ingot to form a silicon wafer; forming a laser mark for marking the crystal orientation of the silicon crystal ingot on any one of the lower bottom surfaces of the silicon crystal wafer with the linear film layer mark as a reference; and removing the linear film layer mark. The method can accurately form the mark on the surface of the wafer, and can avoid the problems of the fragmentation of the wafer in the process of making the mark or after making the mark, the pollution to the wafer in the mark making process and the like because no etching step is carried out in the whole making process, thereby further improving the performance and the yield of the wafer.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a wafer, a manufacturing method thereof and an electronic device.
Background
As integrated circuit technology continues to advance, more devices will be integrated on a chip, and the chip will also adopt faster speeds. With these demands, the geometric size of the device will be reduced, and new materials, new technologies and new manufacturing processes are adopted in the chip manufacturing process. Among them, silicon is a semiconductor material with excellent properties and is widely used in infrared spectrum frequency optical elements, infrared and r-ray detectors, integrated circuits, solar cells, and the like.
Although various marking methods exist at present, various problems exist, such as the wafer is easy to break during or after the marking process, or the wafer is easy to be polluted by particles during the marking process, and the performance and yield of the wafer are severely limited.
Therefore, there is a need for improvements in the current methods of wafer fabrication to eliminate the various problems that exist today.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In view of the deficiencies of the prior art, the present invention provides a method for manufacturing a wafer, the method comprising:
providing a silicon ingot;
forming a linear film layer mark for marking the crystal direction of the silicon crystal ingot on the side surface of the silicon crystal ingot;
slicing the silicon ingot to form a silicon wafer;
forming a laser mark for marking the crystal orientation of the silicon crystal ingot on any one of the lower bottom surfaces of the silicon crystal wafer with the linear film layer mark as a reference;
and removing the linear film layer mark.
Optionally, the linear film marks penetrate through the upper and lower bottom surfaces of the silicon wafer.
Optionally, the linear film layer mark comprises a diamond-like film.
Optionally, the method for forming the linear film mark comprises a nano-pulse plasma chemical vapor deposition method.
Optionally, the gas for forming the linear film mark comprises He and CH4。
Optionally, the laser mark is formed on the edge of any one of the lower bottom surface of the silicon wafer, and the laser mark is aligned with the linear film mark.
Optionally, before forming the linear film layer mark, the method further comprises determining an orientation of a (110) plane of the silicon ingot by X-ray.
Optionally, the diameter of the silicon ingot is at least 450 mm.
Optionally, after removing the linear film mark, the method further includes a step of performing oxidation and/or annealing to remove impurities on the silicon wafer.
Optionally, the linear film mark is removed by a wafer chamfering process.
The invention also provides a wafer, which is prepared by the method.
The invention also provides an electronic device which comprises the wafer.
According to the wafer manufacturing method, in order to mark the crystal orientation of the wafer, the removable linear film layer mark is formed firstly, the linear film layer mark is used as a reference to form the laser mark on the bottom surface of the wafer, and then the linear film layer mark is removed.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
fig. 1A to 1D are schematic structural diagrams of devices obtained in the relevant steps of the method for manufacturing a wafer according to an embodiment of the present invention;
FIG. 2 illustrates a process flow diagram of a method of fabricating a wafer in accordance with one embodiment of the present invention;
fig. 3 shows a schematic diagram of an electronic device in an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In order to provide a thorough understanding of the present invention, detailed steps will be set forth in the following description in order to explain the technical solutions proposed by the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
In the apparatus and method for manufacturing a wafer, a portion of the periphery of a semiconductor wafer is often cut into a V-shape, a square shape, or a circular arc shape to form a groove so that the crystal orientation of the semiconductor wafer can be easily aligned, such as a wafer Notch (Notch). The V-shaped groove is widely used because it can efficiently use a limited area of a wafer and has excellent positioning accuracy.
In the method of manufacturing the wafer, the periphery of the semiconductor wafer is sometimes brought into contact with a part of an apparatus used for the process. Such contact can result in dust and cracking. To prevent such contact, the periphery of the semiconductor wafer is typically chamfered.
For example, a notch chamfering (wafer chamfering) is performed to form a mark on a wafer, but the method causes a particle defect on the wafer and is difficult to remove.
In order to solve the above problem, the present invention provides a method for manufacturing a wafer, the method comprising:
providing a silicon ingot;
forming a linear film layer mark for marking the crystal direction of the silicon crystal ingot on the side surface of the silicon crystal ingot;
slicing the silicon ingot to form a silicon wafer;
forming a laser mark for marking the crystal orientation of the silicon crystal ingot on any one of the upper bottom surface and the lower bottom surface of the silicon wafer by using the linear film layer mark as a reference;
and removing the linear film layer mark.
According to the wafer manufacturing method, in order to mark the crystal orientation of the wafer, the removable linear film layer mark is formed firstly, the linear film layer mark is used as a reference to form the laser mark on the bottom surface of the wafer, and then the linear film layer mark is removed.
Example one
In order to solve the foregoing technical problem and improve the performance of the device, an embodiment of the present invention provides a method for manufacturing a semiconductor device, which, as shown in fig. 2, mainly includes:
step S1: providing a silicon ingot;
step S2: forming a linear film layer mark for marking the crystal direction of the silicon crystal ingot on the side surface of the silicon crystal ingot;
step S3: slicing the silicon ingot to form a silicon wafer;
step S4: forming a laser mark for marking the crystal orientation of the silicon crystal ingot on any one of the lower bottom surfaces of the silicon crystal wafer with the linear film layer mark as a reference;
step S5: and removing the linear film layer mark.
According to the wafer manufacturing method, in order to mark the crystal orientation of the wafer, the removable linear film layer mark is formed firstly, the linear film layer mark is used as a reference to form the laser mark on the bottom surface of the wafer, and then the linear film layer mark is removed.
Specifically, the method for manufacturing a wafer according to the present invention is described in detail below with reference to fig. 1A to 1D, in which fig. 1A to 1D show schematic structural views of a wafer obtained in relevant steps of the method for manufacturing a semiconductor device according to an embodiment of the present invention.
First, step one is executed to provide a silicon ingot.
Specifically, as shown in fig. 1A, a silicon ingot 101 is provided, wherein the silicon ingot 101 is a cylindrical or rectangular solid-state silicon polycrystal or silicon single crystal, not limited to one.
In which molten elemental silicon, when solidified, has silicon atoms arranged in a diamond lattice as a plurality of crystal nuclei, and if these crystal nuclei grow into crystal grains having the same crystal plane orientation, these crystal grains are combined in parallel to crystallize into single crystal silicon.
Single crystal silicon has the physical properties of metalloids, has weak conductivity, increases conductivity with increasing temperature, and has remarkable semiconductivity. Ultra-pure single crystal silicon is an intrinsic semiconductor. Doping a trace amount of IIIA group elements, such as boron, into the ultra-pure monocrystalline silicon to improve the conductivity of the ultra-pure monocrystalline silicon so as to form a p-type silicon semiconductor; for example, the conductivity can be improved by doping trace amount of VA element such as phosphorus or arsenic to form n-type silicon semiconductor.
Single crystal silicon is typically produced by first producing polycrystalline silicon or amorphous silicon and then growing rod-shaped single crystal silicon from the melt by the Czochralski or suspension float zone method. Single crystal silicon is mainly used for manufacturing semiconductor elements.
In one embodiment of the invention, a single crystal silicon pulling process is exemplified, specifically comprising the steps of,
polysilicon charging preparation: checking the purity index and the size of the polycrystalline silicon material, wherein the purity of the dopant is 6N, and then selecting seed crystals with good crystal orientation and without mechanical damage to be loaded into a cleaned hearth;
vacuumizing: vacuumizing the furnace body, keeping the vacuum degree at 4Pa, and introducing argon for 10 min;
melting the silicon material: heating and melting the silicon material, keeping a heater, melting the silicon material completely, and cooling to a crystallization temperature;
the following steps: determining the crystallization temperature, contacting the seed crystal with the surface of the melt, and rotating to ensure good wetting;
neck collection: neck contraction is carried out according to the neck contraction diameter of 3mm and the pulling speed of 1 mm/min;
shouldering: pulling speed is 0.2mm/min, shoulder expanding speed is 1mm/min, and when the shoulder-laying diameter approaches to the required crystal diameter, lifting is carried out
Raising the pulling speed to 2mm/min, and enabling the crystal to enter an equal-diameter growth stage;
ending: increasing the crystal pulling speed, gradually reducing the diameter of the crystal until the crystal is separated from the liquid level, then reducing the temperature, and ending the crystal pulling process.
It should be noted that the method for producing the silicon ingot 101 is not limited to a specific method, and the production may be performed according to actual needs.
Wherein the diameter of the silicon ingot is at least 450 mm.
And step two, forming a linear film layer mark for marking the crystal direction of the silicon crystal ingot on the side surface of the silicon crystal ingot.
Specifically, as shown in fig. 1A, a cylindrical silicon ingot is exemplified in the present embodiment, wherein the side surface refers to a curved side surface of the cylinder, i.e., a portion that is rectangular after being expanded, and the bottom surface refers to 2 circular bottom surfaces that are the same in size and parallel to each other, and the side surface and the bottom surface are referred to for explanation unless otherwise specified.
Wherein a linear film layer mark 102 for marking the crystal direction of the silicon ingot is formed on the side surface of the silicon ingot, wherein the linear film layer mark 102 is parallel to the height of the cylinder, i.e. perpendicular to the 2 circular bottom surfaces with the same size and parallel to each other.
Further, the linear film marks penetrate through the upper and lower bottom surfaces of the silicon wafer, that is, the linear film marks extend from one bottom surface to the other bottom surface along the side surface, so that the linear film marks are formed on any wafer after slicing.
Further, the linear film mark comprises a Diamond Like Carbon film (DLC).
Wherein, the forming method of the Diamond Like Carbon film (DLC) comprises nanometer pulse plasma atmosphere chemical vapor deposition (atomic nano-pulse plasma CVD).
The flow of the nanometer pulse plasma atmosphere chemical vapor deposition method (atmospherical nano-pulse plasma CVD) in the invention is as follows: firstly, the surface is pretreated by grinding, polishing, cleaning and drying, etc., the surface to be treated is bombarded and cleaned by low-energy large-beam He ion beam, CH is introduced4The gas is directly used for chemical vapor deposition of the diamond-like carbon film layer.
Wherein the diamond-like film layer has a thickness of 5-50mm to protrude from the side of the silicon ingot to form a protruded line for marking.
Wherein the vacuum pressure in the nanometer pulse plasma atmosphere chemical vapor deposition (atmospherical nano-pulse plasma CVD) is 5 × 10-5Pa, working pressure (1-2) x 10-2Pa, low energy ion source using high purity CH4As a gas source to produce low energy CHn+Ion beam, medium energy ion source using high-purity He as gas source to generate medium energy He+An ion beam.
Specifically, the method further comprises determining the crystal orientation of the silicon ingot by an X-Ray Diffraction (XRD) technique before forming the linear film layer mark.
For example, the method further comprises orienting the (110) plane of the silicon ingot by an X-Ray Diffraction (XRD) technique before forming the linear film layer marks.
And step three, slicing the silicon crystal ingot to form a silicon wafer.
Specifically, as shown in fig. 1B, the silicon ingot is sliced using a slicing machine in this step to obtain a silicon wafer 103 of a target thickness.
After the silicon wafer 103 is obtained, a part of the side surface of the silicon wafer 103 having the linear film mark can still be used for marking the crystal orientation.
And then forming laser marks 104 for marking the crystal orientation of the silicon crystal ingot on the upper bottom surface or/and the lower bottom surface of the silicon wafer with the linear film layer marks as reference, as shown in fig. 1C.
Wherein the laser mark 104 is formed at an edge position of the wafer, and the laser mark 104 is aligned with the linear film mark.
Wherein the laser mark 104 is formed in a predetermined formed region by a laser irradiation method.
Wherein a pulsed laser with a frequency of 10MHz or greater may be used to act on the surface of the wafer to form the laser mark 104.
The shape of the laser mark 104 may be a circle, a square, a polygon, and the like, and is not limited to a specific one.
In this embodiment, the laser mark 104 is circular and has a diameter of 0.5-5mm, but is not limited to this range.
And step four, removing the linear film layer mark.
Specifically, as shown in fig. 1D, the linear film mark is removed by a wafer Chamfering process (chamferring).
Wherein the linear film mark is removed in the wafer chamfering process by using a grinding stone, and the grinding stone is a part which is substantially subjected to a grinding operation with the wafer.
The linear film layer mark can be removed through the wafer chamfering process so as to form a side face with a flat surface.
And executing a fifth step, wherein after the linear film mark is removed, the method further comprises the step of oxidizing and/or annealing to remove impurities on the silicon wafer.
The annealing treatment adopts a slow spike annealing process and the like.
The detailed description of the manufacturing method of the wafer according to the present invention is completed so far, and further process steps may be required for manufacturing a complete device, which is not described herein again.
According to the wafer manufacturing method, in order to mark the crystal orientation of the wafer, the removable linear film layer mark is formed firstly, the linear film layer mark is used as a reference to form the laser mark on the bottom surface of the wafer, and then the linear film layer mark is removed.
Example two
The invention also provides a wafer prepared by the method of the first embodiment.
Wherein, the wafer is provided with a laser mark instead of a wafer gap or a wafer surface-taking mark.
The wafer is a polycrystalline silicon wafer or a single crystal silicon wafer, but not limited to a single wafer.
Wherein the laser mark 104 is formed in a predetermined formed region by a laser irradiation method.
Wherein a pulsed laser with a frequency of 10MHz or greater may be used to act on the surface of the wafer to form the laser mark 104.
The shape of the laser mark 104 may be a circle, a square, a polygon, and the like, and is not limited to a specific one.
In this embodiment, the laser mark 104 is circular and has a diameter of 0.5-5mm, but is not limited to this range.
The wafer and the laser mark have no etching step in the preparation process, so that the problems of fragmentation of the wafer in the mark preparation process or after the mark preparation, pollution to the wafer in the mark preparation process and the like can be avoided, and the performance and yield of the wafer are further improved.
EXAMPLE III
Another embodiment of the present invention provides an electronic device, which includes a wafer, where the wafer is the wafer in the second embodiment or the wafer manufactured by the method according to the first embodiment.
The electronic device may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, and a PSP, or may be an intermediate product having the semiconductor, for example: a mobile phone mainboard with the integrated circuit, and the like.
Wherein figure 3 shows an example of a mobile telephone handset. The mobile phone handset 300 is provided with a display portion 302, operation buttons 303, an external connection port 304, a speaker 305, a microphone 306, and the like, which are included in a housing 301.
Wherein the mobile phone handset comprises the wafer as described above,
the wafer and the laser mark have no etching step in the preparation process, so that the problems of fragmentation of the wafer in the mark preparation process or after the mark preparation, pollution to the wafer in the mark preparation process and the like can be avoided, and the performance and yield of the wafer are further improved.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (12)
1. A method for manufacturing a wafer, the method comprising:
providing a silicon ingot;
forming a linear film layer mark for marking the crystal direction of the silicon crystal ingot on the side surface of the silicon crystal ingot;
slicing the silicon ingot to form a silicon wafer;
forming a laser mark for marking the crystal orientation of the silicon crystal ingot on any one of the lower bottom surfaces of the silicon crystal wafer with the linear film layer mark as a reference;
and removing the linear film mark, wherein the manufacturing method has no etching step so as to avoid the fragmentation of the wafer and the pollution of the wafer.
2. The method of claim 1, wherein the linear film marks extend through the top and bottom surfaces of the silicon wafer.
3. The manufacturing method according to claim 1, wherein the linear film layer mark comprises a diamond-like film.
4. The method of manufacturing according to claim 1, wherein the method of forming the linear film mark comprises a nano-pulsed plasma chemical vapor deposition method.
5. The manufacturing method according to claim 1, wherein the gas for forming the linear film mark comprises He and CH4。
6. The manufacturing method according to claim 1, wherein the laser mark is formed on an edge portion of any one of the lower bottom surfaces of the silicon wafer, and the laser mark is aligned with the linear film layer mark.
7. The manufacturing method according to claim 1, wherein before forming the linear film layer mark, the method further comprises orienting a (110) plane of the silicon ingot by X-ray.
8. A method of manufacture as set forth in claim 1 wherein the silicon ingot has a diameter of at least 450 mm.
9. The manufacturing method according to claim 1, wherein after removing the linear film marks, the method further comprises a step of performing oxidation and/or annealing to remove impurities on the silicon wafer.
10. The method of manufacturing according to claim 1, wherein the linear film marks are removed by a wafer chamfering process.
11. A wafer prepared by the manufacturing method of any one of claims 1 to 10.
12. An electronic device, characterized in that the electronic device comprises the wafer of claim 11.
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| CN201710780544.8A CN109427614B (en) | 2017-09-01 | 2017-09-01 | Wafer, manufacturing method thereof and electronic device |
| TW107103145A TWI664330B (en) | 2017-09-01 | 2018-01-30 | Wafer manufacturing method |
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| CN201710780544.8A CN109427614B (en) | 2017-09-01 | 2017-09-01 | Wafer, manufacturing method thereof and electronic device |
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