CN109412563B - Two-way wheel patrol pulse width frequency variable trigger signal generation controller - Google Patents

Two-way wheel patrol pulse width frequency variable trigger signal generation controller Download PDF

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Publication number
CN109412563B
CN109412563B CN201811472634.1A CN201811472634A CN109412563B CN 109412563 B CN109412563 B CN 109412563B CN 201811472634 A CN201811472634 A CN 201811472634A CN 109412563 B CN109412563 B CN 109412563B
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resistor
capacitor
signal
output
trigger
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CN109412563A (en
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何通
王胜
万泽清
顾善忠
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Jiangsu Aerospace Dawei Technology Co Ltd
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Jiangsu Aerospace Dawei Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/37—Converter circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/50—Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDs; responsive to LED life; Protective circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)

Abstract

The invention provides a two-way wheel patrol pulse width frequency variable trigger signal generation controller, which comprises: the device comprises a power circuit, a clock signal generating circuit, an adjustable pulse width limiting circuit, an adjustable pulse frequency limiting circuit, a trigger signal and enabling signal generating circuit and a double-path driving output circuit; the adjustable pulse frequency limiting circuit generates a frequency limiting signal TEN with adjustable frequency according to the input clock signal CLK and the adjustment setting; the input of the trigger signal and enabling signal generating circuit is a front-stage output trigger signal, and is used for generating a trigger pulse signal TRP corresponding to the front-stage output trigger signal and a round-robin enabling signal FPW; the adjustable pulse width limiting circuit generates a pulse width limited trigger signal DRV with settable and adjustable pulse width according to the input trigger pulse signal TRP and the adjustment setting; the two-way driving output circuit outputs two-way frequency and pulse width adjustable later-stage equipment trigger signals. The controller works reliably.

Description

Two-way wheel patrol pulse width frequency variable trigger signal generation controller
Technical Field
The invention relates to an intelligent traffic signal controller, which is particularly suitable for being used in the aspect of light supplementing lamp control, such as a bayonet light supplementing lamp, an electronic police light supplementing lamp and the like, in particular to a two-way wheel inspection pulse width frequency variable trigger signal generation controller.
Background
At present, the domestic intelligent traffic is developed at a high speed for several years, and the method has great progress in application range and application depth. From the single command vehicle crossing function development to the public security control aspect, a powerful means is brought to the ordered development and harmony stability of society. For example, in the aspect of red light running management at an intersection, a camera is used for taking a snapshot, and a important road section bayonet is also used for taking a snapshot, so that an effective light supplementing device is required for identifying people or automobile license plates in order to clear out the snapshot, and generally one camera is required to monitor more than two lanes or take a plurality of photos at some time, so that two light supplementing devices are required to be connected; the common camera only has one output port which cannot correspond to more than two light supplementing devices, and the light supplementing devices of different manufacturers have requirements on the width of the trigger signal, and the light supplementing devices have strict requirements on the interference on the trigger signal and the lightning protection and static prevention, so that an effective controller is needed between the camera and the light supplementing devices to fulfill the requirements, and the requirements of various different scenes are met. The connection mode in the field is that the camera is firstly connected with the controller, and then the controller is connected with one to two light supplementing devices. Such a controller is basically provided with one snapshot camera, and the number of cameras used in electronic police and bayonet snapshots in China is extremely large at present, so that the market demand of products of this type in China is also very large.
Disclosure of Invention
The invention aims to solve the problem of the existing camera and light supplementing device in field use, and provides a two-way wheel inspection pulse width frequency variable trigger signal generation controller which is low in cost, convenient to use, safe and reliable. The technical scheme adopted by the invention is as follows:
a two-way round robin pulse width frequency variable trigger signal generation controller, comprising:
the device comprises a power circuit, a clock signal generating circuit, an adjustable pulse width limiting circuit, an adjustable pulse frequency limiting circuit, a trigger signal and enabling signal generating circuit and a double-path driving output circuit;
the power supply circuit provides respective required direct current voltages for the clock signal generating circuit, the adjustable pulse width limiting circuit, the adjustable pulse frequency limiting circuit, the trigger signal generating circuit, the enabling signal generating circuit and the double-path driving output circuit;
the clock signal generating circuit is used for generating a clock signal CLK and is used as a clock input of the adjustable pulse frequency limiting circuit;
the adjustable pulse frequency limiting circuit is used for generating a frequency limiting signal TEN with a settable and adjustable frequency according to an input clock signal CLK and adjustment setting, and the frequency limiting signal TEN is used as a signal input of the two-way driving output circuit;
the input of the trigger signal and the enabling signal generating circuit is a front-stage output trigger signal and is used for generating a trigger pulse signal TRP corresponding to the front-stage output trigger signal and a round-robin enabling signal FPW; the trigger pulse signal TRP is used as a signal input of the adjustable pulse width limiting circuit, and the round trip enabling signal FPW is used as a round trip control input of the double-path driving output circuit;
the adjustable pulse width limiting circuit generates a pulse width limited trigger signal DRV with a settable and adjustable pulse width according to the input trigger pulse signal TRP and the adjustment setting, and the pulse width limited trigger signal DRV is used as the other signal input of the two-way driving output circuit;
the two-way driving output circuit outputs two-way frequency and pulse width adjustable later-stage equipment trigger signals according to the input frequency limit signal TEN, the pulse width limited trigger signal DRV and the round-robin enabling signal FPW.
Further, the power supply circuit comprises a rectifier bridge, a fuse F1, an inductor L1, a transient suppression diode TV1, capacitors C1, C2, C3 and C4, a DC/DC chip U1, a light emitting diode LED1 and a resistor R1; the two input ends of the rectifier bridge are respectively connected with the two terminals of the connecting seat J1, the positive output end of the rectifier bridge is connected with one end of the fuse F1, the other end of the fuse F1 is connected with one end of the inductor L1 and the cathode of the transient suppression diode TV1, and the negative output end of the rectifier bridge and the anode of the transient suppression diode TV1 are grounded; the other end of the inductor L1 is connected with the anode of the capacitor C1, one end of the capacitor C2 and the input end of the DC/DC chip U1, and the cathode of the capacitor C1, the other end of the capacitor C2 and the grounding end of the DC/DC chip U1 are grounded; the output end of the DC/DC chip U1 is connected with the anode of the capacitor C3, one end of the capacitor C4 and the anode of the light-emitting diode LED1, and outputs voltage VCC; the cathode of the capacitor C3 and the other end of the capacitor C4 are grounded, and the cathode of the light emitting diode LED1 is grounded through a resistor R1.
Further, the clock signal generating circuit comprises resistors R21, R22, R23, R24, a timer chip U21, an and gate U22, and capacitors C21, C22, C23; wherein the timer chip U21 adopts ICM7555; the seventh pin of the timer chip U21 is connected with one end of a resistor R21 and one end of a resistor R22, the other end of the resistor R22 is connected with one end of a resistor R23, and the other end of the resistor R23 is connected with the second pin and the sixth pin of the timer chip U21 and is grounded through a capacitor C22; the other end of the resistor R21, the fourth pin and the eighth pin of the timer chip U21, one end of the capacitor C21 and one end of the resistor R24 are connected with the voltage VCC; the other end of the capacitor C21 is grounded; the first pin of the timer chip U21 is grounded, and the fifth pin is grounded through a capacitor C23; the third pin of the timer chip U21 is connected to the other end of the resistor R24, and to both inputs of the and gate U22, and the output of the and gate U22 outputs the clock signal CLK.
Further, the adjustable pulse frequency limiting circuit comprises a four-bit binary counter U41, NAND gates U42 and U43, an AND gate U44, jumpers JP5, JP6, JP7, JP8 and a capacitor C41;
the first pin of the four-bit binary counter U41 is connected with the output end of the AND gate U44, and the two input ends of the AND gate U44 are connected with a clear signal CLR; the second pin of the counter U41 is connected with a clock signal CLK, the third pin is connected with a voltage VCC through a resistor R42, the fourth pin is connected with the voltage VCC through a resistor R43, the fifth pin is connected with the voltage VCC through a resistor R44, the sixth pin is connected with the voltage VCC through a resistor R45, and the seventh pin of the counter U41 is connected with the output end of the NAND gate U42 and two input ends of the NAND gate U43; the ninth pin and the tenth pin of the counter U41 are connected with the voltage VCC through a resistor R41, and the eighth pin of the counter U41 is grounded; a tenth pin of the counter U41 is connected with one end of a jumper JP8, a twelfth pin is connected with one end of a jumper JP7, a thirteenth pin is connected with one end of a jumper JP6, and a fourteenth pin is connected with one end of a jumper JP 5; one end of the other termination resistor R47 of the jumper JP5 and one input end of the NAND gate U42, and one end of the other termination resistor R46 of the jumpers JP6, JP7, JP8 and the other input end of the NAND gate U42; the other ends of the resistors R46 and R47 are connected with voltage VCC, the positive electrode of the capacitor C41 is connected with voltage VCC, and the negative electrode is grounded; the output of the nand gate U43 generates a frequency-limited signal TEN with a frequency that can be set and adjusted.
Further, the frequency of the frequency-limited signal TEN is several hertz.
Further, the trigger signal and enable signal generating circuit comprises a voltage comparator U51, a NAND gate U52, a D trigger U53, resistors R51, R52, R53, R54, R55, capacitors C51, C52, C53, a transient suppression diode TV51, magnetic beads FB1, FB2;
the output trigger signals TR+ and TR-of the front stage are respectively connected with the cathode and the anode of the transient suppression diode TV 51; one end of the magnetic bead FB1 and one end of the capacitor C51 are connected with the cathode of the transient suppression diode TV51, and one end of the magnetic bead FB2 and the other end of the capacitor C8 are connected with the anode of the transient suppression diode TV 51; the other end of the magnetic bead FB1 is connected with one end of a resistor R51, one end of a capacitor C52 and the non-inverting input end of a voltage comparator U51, and the other end of the magnetic bead FB2 and the other end of the capacitor C52 are grounded; the other end of the resistor R51 is connected with the voltage VCC and one end of the resistor R52, the other end of the resistor R52 is connected with one end of the resistor R53, one end of the capacitor C53 and the inverting input end of the voltage comparator U51, and the other end of the resistor R53 and the other end of the capacitor C53 are grounded; the output end of the voltage comparator U51 is connected with two input ends of the NAND gate U52 and the clock end of the D trigger U53; the output end of the NAND gate U52 outputs a trigger pulse signal TRP; the Q non-output end of the D trigger U53 is connected with the D end, the R end of the D trigger U53 is connected with the voltage VCC through a resistor R55, the S end of the D trigger U53 is connected with the voltage VCC through a resistor R54, and the Q output end of the D trigger U53 outputs a round trip enabling signal FPW.
Further, the adjustable pulse width limiting circuit comprises a voltage comparator U31, a NAND gate U32, an AND gate U33, resistors R31, R32 and R33, capacitors C31, C32, C33, C34 and C35;
one end of the resistor R31 is connected with the voltage VCC, and the other end of the resistor R32, one end of the capacitor C31 and the inverting input end of the voltage comparator U31; the other end of the resistor R32 and the other end of the capacitor C31 are grounded; one end of the resistor R33 contacts the pulse signal TRP, and one end of the and gate U33; the other end of the resistor R33 is connected with one ends of the capacitors C32, C33, C34 and C35 and the non-inverting input end of the voltage comparator U31; the other end of the capacitor C32 is connected with one end of a jumper wire JP4, and the other end of the jumper wire JP4 is grounded; the other end of the capacitor C33 is connected with one end of a jumper wire JP3, and the other end of the jumper wire JP3 is grounded; the other end of the capacitor C34 is connected with one end of a jumper wire JP2, and the other end of the jumper wire JP2 is grounded; the other end of the capacitor C35 is connected with one end of a jumper wire JP1, and the other end of the jumper wire JP1 is grounded; the output end of the voltage comparator U31 is connected with two input ends of the NAND gate U32, and the output end of the NAND gate U32 generates a clear signal CLR; the output end of the nand gate U32 is connected to the other input end of the and gate U33, and the output end of the and gate U33 generates the pulse width limited trigger signal DRV.
Further, the two-way driving output circuit comprises an AND gate U61 and two-way isolation driving output circuits; the round-robin enabling signal FPW enables the two paths of isolation driving output circuits to conduct alternately; the two input ends of the AND gate U61 are respectively connected with the frequency limiting signal TEN and the pulse width limited trigger signal DRV, and the output end of the AND gate U61 is connected with the respective input ends of the two paths of isolation driving output circuits.
Further, the first path of isolation driving output circuit includes resistors R61, R62, R63, R64, R65, R66, NPN transistors Q61, Q62, an optocoupler OP1, a light emitting diode LED61, a capacitor C61, a transient suppression diode TV61, and a fuse F61;
one ends of the resistors R63 and R64 are connected with a round robin enabling signal FPW, the other end of the resistor R63 is connected with a voltage VCC and a collector electrode of the triode Q61, the other end of the resistor R64 is connected with a base electrode of the triode Q61, and an emitter electrode of the triode Q61 is connected with an anode of an input end of the optocoupler OP 1; the cathode of the input end of the optocoupler OP1 is connected with the anode of the light emitting diode LED61, the cathode of the light emitting diode LED61 is connected with the collector of the triode Q62 through the resistor R65, the emitter of the triode Q62 is grounded, the base of the triode Q62 is connected with one end of the resistor R62, the other end of the resistor R62 is connected with the output end of the AND gate U61, and the other end of the resistor R62 is connected with the voltage VCC through the resistor R61; the collector of the output end of the optical coupler OP1 is connected with one end of a resistor R66, the cathode of a transient suppression diode TV61 and one end of a fuse F61, the other end of the resistor R66 is connected with one end of a capacitor C61, and the other end of the capacitor C61 and the anode of the transient suppression diode TV61 are connected with the emitter of the output end of the optical coupler OP 1; two output ends of the optical coupler OP1 output a first path of later-stage equipment trigger signal;
the second path of isolation driving output circuit comprises resistors R71, R72, R73, R74, R75 and R76, a PNP triode Q71, an NPN triode Q72, an optocoupler OP2, a light emitting diode LED71, a capacitor C71, a transient suppression diode TV71 and a fuse F71;
one end of the resistor R73 and one end of the resistor R74 are connected with the round trip enable signal FPW, the other end of the resistor R73 is connected with the voltage VCC and the emitting electrode of the triode Q71, the other end of the resistor R74 is connected with the base electrode of the triode Q71, and the collecting electrode of the triode Q71 is connected with the anode of the input end of the optocoupler OP 2; the cathode of the input end of the optocoupler OP2 is connected with the anode of the light emitting diode LED71, the cathode of the light emitting diode LED71 is connected with the collector of the triode Q72 through the resistor R75, the emitter of the triode Q72 is grounded, the base of the triode Q72 is connected with one end of the resistor R72, the other end of the resistor R72 is connected with the output end of the AND gate U61, and the other end of the resistor R72 is connected with the voltage VCC through the resistor R71; the collector of the output end of the optical coupler OP2 is connected with one end of a resistor R76, the cathode of a transient suppression diode TV71 and one end of a fuse F71, the other end of the resistor R76 is connected with one end of a capacitor C71, and the other end of the capacitor C71 and the anode of the transient suppression diode TV71 are connected with the emitter of the output end of the optical coupler OP 2; two output ends of the optical coupler OP2 output a second-path post-stage device trigger signal.
The invention has the advantages that: the flexible arrangement can meet the requirements of various different sites, the complete hardware of the circuit can not be halted, the operation is stable and reliable, and the environment application range is wide. The circuit device has low cost and easy maintenance. The product has multiple functions and can meet the defects of field use, the product has ingenious principle and conception, and the product flexibly and completely meets the field requirement. The circuit is provided with a plurality of filter circuits and a protection circuit, and can meet various complex electromagnetic environments.
Drawings
Fig. 1 is a functional block diagram of the present invention.
Fig. 2 is a schematic diagram of a power circuit of the present invention.
Fig. 3 is a schematic diagram of a clock signal generation circuit according to the present invention.
Fig. 4 is a schematic diagram of an adjustable pulse width limiting circuit of the present invention.
Fig. 5 is a schematic diagram of an adjustable pulse frequency limiting circuit of the present invention.
Fig. 6 is a schematic diagram of a trigger signal and enable signal generating circuit according to the present invention.
Fig. 7 is a schematic diagram of a dual drive output circuit of the present invention.
Detailed Description
The invention will be further described with reference to the following specific drawings and examples.
As shown in fig. 1, the invention provides a two-way round inspection pulse width frequency variable trigger signal generation controller, which comprises: a power supply circuit 10, a clock signal generating circuit 20, an adjustable pulse width limiting circuit 30, an adjustable pulse frequency limiting circuit 40, a trigger signal and enable signal generating circuit 50, and a two-way driving output circuit 60;
the power supply circuit 10 provides respective required direct current voltages for the clock signal generating circuit 20, the adjustable pulse width limiting circuit 30, the adjustable pulse frequency limiting circuit 40, the trigger signal generating circuit 50, the enabling signal generating circuit 50 and the two-way driving output circuit 60;
as shown in fig. 2, the power supply circuit 10 includes a rectifier bridge composed of diodes D1 to D4, a fuse F1, an inductance L1, a transient suppression diode TV1, capacitances C1, C2, C3, C4, a DC/DC chip U1, a light emitting diode LED1, and a resistor R1; the two input ends of the rectifier bridge are respectively connected with the two terminals of the connecting seat J1, the positive output end of the rectifier bridge is connected with one end of the fuse F1, the other end of the fuse F1 is connected with one end of the inductor L1 and the cathode of the transient suppression diode TV1, and the negative output end of the rectifier bridge and the anode of the transient suppression diode TV1 are grounded; the other end of the inductor L1 is connected with the anode of the capacitor C1, one end of the capacitor C2 and the input end of the DC/DC chip U1, and the cathode of the capacitor C1, the other end of the capacitor C2 and the grounding end of the DC/DC chip U1 are grounded; the output end of the DC/DC chip U1 is connected with the anode of the capacitor C3, one end of the capacitor C4 and the anode of the light-emitting diode LED1, and outputs voltage VCC; the cathode of the capacitor C3 and the other end of the capacitor C4 are grounded, and the cathode of the light-emitting diode LED1 is grounded through a resistor R1; the capacitors C1 and C3 are electrolytic capacitors, and the capacitors C2 and C4 are monolithic capacitors; VCC is +5v in this example;
the clock signal generating circuit 20 is configured to generate a clock signal CLK as a clock input to the adjustable pulse frequency limiting circuit 40; the frequency of the clock signal CLK is 20Hz;
as shown in fig. 3, the clock signal generating circuit 20 includes resistors R21, R22, R23, R24, a timer chip U21, an and gate U22, and capacitors C21, C22, C23; wherein the timer chip U21 adopts ICM7555; the seventh pin of the timer chip U21 is connected with one end of a resistor R21 and one end of a resistor R22, the other end of the resistor R22 is connected with one end of a resistor R23, and the other end of the resistor R23 is connected with the second pin and the sixth pin of the timer chip U21 and is grounded through a capacitor C22; the other end of the resistor R21, the fourth pin and the eighth pin of the timer chip U21, one end of the capacitor C21 and one end of the resistor R24 are connected with the voltage VCC; the other end of the capacitor C21 is grounded; the first pin of the timer chip U21 is grounded, and the fifth pin is grounded through a capacitor C23; the third pin of the timer chip U21 is connected with the other end of the resistor R24, two input ends of the AND gate U22, and the output end of the AND gate U22 outputs a clock signal CLK;
the adjustable pulse frequency limiting circuit 40 is configured to generate a frequency-settable and adjustable frequency limiting signal TEN according to the input clock signal CLK and the adjustment setting, and the frequency limiting signal TEN is used as a signal input of the two-way driving output circuit 60; the frequency of the frequency limit signal TEN is typically set to be several hertz;
as shown in fig. 5, the adjustable pulse frequency limiting circuit 40 includes a four-bit binary counter U41, nand gates U42, U43, and gate U44, jumpers JP5, JP6, JP7, JP8, and a capacitor C41; the limited frequency is selected by jumpers JP5, JP6, JP7 and JP8, 15 choices are available;
the first pin of the four-bit binary counter U41 is connected with the output end of the AND gate U44, and the two input ends of the AND gate U44 are connected with a clear signal CLR; the second pin of the counter U41 is connected with a clock signal CLK, the third pin is connected with a voltage VCC through a resistor R42, the fourth pin is connected with the voltage VCC through a resistor R43, the fifth pin is connected with the voltage VCC through a resistor R44, the sixth pin is connected with the voltage VCC through a resistor R45, and the seventh pin of the counter U41 is connected with the output end of the NAND gate U42 and two input ends of the NAND gate U43; the ninth pin and the tenth pin of the counter U41 are connected with the voltage VCC through a resistor R41, and the eighth pin of the counter U41 is grounded; a tenth pin of the counter U41 is connected with one end of a jumper JP8, a twelfth pin is connected with one end of a jumper JP7, a thirteenth pin is connected with one end of a jumper JP6, and a fourteenth pin is connected with one end of a jumper JP 5; one end of the other termination resistor R47 of the jumper JP5 and one input end of the NAND gate U42, and one end of the other termination resistor R46 of the jumpers JP6, JP7, JP8 and the other input end of the NAND gate U42; the other ends of the resistors R46 and R47 are connected with voltage VCC, the positive electrode of the capacitor C41 is connected with voltage VCC, and the negative electrode is grounded; the output end of the NAND gate U43 generates a frequency limiting signal TEN with a frequency capable of being set and adjusted;
the input of the trigger signal and enable signal generating circuit 50 is a pre-stage output trigger signal, and is used for generating a trigger pulse signal TRP corresponding to the pre-stage output trigger signal and a round-robin enable signal FPW; the trigger pulse signal TRP is used as a signal input of the adjustable pulse width limiting circuit 30, and the round trip enable signal FPW is used as a round trip control input of the two-way driving output circuit 60; the front stage output trigger signal is from the output trigger signal of the camera;
as shown in fig. 6, the trigger signal and enable signal generating circuit 50 includes a voltage comparator U51, a nand gate U52, a D flip-flop U53, resistors R51, R52, R53, R54, R55, capacitors C51, C52, C53, a transient suppression diode TV51, and beads FB1, FB2;
the output trigger signals TR+ and TR-of the front stage are respectively connected with the cathode and the anode of the transient suppression diode TV 51; one end of the magnetic bead FB1 and one end of the capacitor C51 are connected with the cathode of the transient suppression diode TV51, and one end of the magnetic bead FB2 and the other end of the capacitor C8 are connected with the anode of the transient suppression diode TV 51; the other end of the magnetic bead FB1 is connected with one end of a resistor R51, one end of a capacitor C52 and the non-inverting input end of a voltage comparator U51, and the other end of the magnetic bead FB2 and the other end of the capacitor C52 are grounded; the other end of the resistor R51 is connected with the voltage VCC and one end of the resistor R52, the other end of the resistor R52 is connected with one end of the resistor R53, one end of the capacitor C53 and the inverting input end of the voltage comparator U51, and the other end of the resistor R53 and the other end of the capacitor C53 are grounded; the output end of the voltage comparator U51 is connected with two input ends of the NAND gate U52 and the clock end of the D trigger U53; the output end of the NAND gate U52 outputs a trigger pulse signal TRP; the Q non-output end of the D trigger U53 is connected with the D end, the R end of the D trigger U53 is connected with the voltage VCC through a resistor R55, the S end of the D trigger U53 is connected with the voltage VCC through a resistor R54, and the Q output end of the D trigger U53 outputs a round robin enabling signal FPW; the round enable signal FPW is a square wave signal with 1 and 0 alternately, and can control the alternate conduction operation of two output circuits in the two-way driving output circuit 60;
the adjustable pulse width limiting circuit 30 generates a pulse width limited trigger signal DRV with a pulse width which can be set and adjusted according to the input trigger pulse signal TRP and the adjustment setting, and the pulse width limited trigger signal DRV is used as another signal input of the two-way driving output circuit 60;
as shown in fig. 4, the adjustable pulse width limiting circuit 30 includes a voltage comparator U31, a nand gate U32, an and gate U33, resistors R31, R32, R33, and capacitors C31, C32, C33, C34, C35;
one end of the resistor R31 is connected with the voltage VCC, and the other end of the resistor R32, one end of the capacitor C31 and the inverting input end of the voltage comparator U31; the other end of the resistor R32 and the other end of the capacitor C31 are grounded; one end of the resistor R33 contacts the pulse signal TRP, and one end of the and gate U33; the other end of the resistor R33 is connected with one ends of the capacitors C32, C33, C34 and C35 and the non-inverting input end of the voltage comparator U31; the other end of the capacitor C32 is connected with one end of a jumper wire JP4, and the other end of the jumper wire JP4 is grounded; the other end of the capacitor C33 is connected with one end of a jumper wire JP3, and the other end of the jumper wire JP3 is grounded; the other end of the capacitor C34 is connected with one end of a jumper wire JP2, and the other end of the jumper wire JP2 is grounded; the other end of the capacitor C35 is connected with one end of a jumper wire JP1, and the other end of the jumper wire JP1 is grounded; the output end of the voltage comparator U31 is connected with two input ends of the NAND gate U32, the output end of the NAND gate U32 is connected with the other input end of the AND gate U33, and the output end of the NAND gate U32 generates a clear signal CLR; the output end of the AND gate U33 generates a pulse width limited trigger signal DRV; the DRV pulse width needing to be limited can be selected through jumpers JP1, JP2, JP3 and JP4, and 15 pulse widths can be selected; the pulse width of the finally output trigger signal of the later-stage equipment is limited in the range required by the light supplementing device;
the two-way driving output circuit 60 outputs two-way frequency and pulse width adjustable post-stage equipment trigger signals according to the input frequency limit signal TEN, the pulse width limited trigger signal DRV and the round-robin enabling signal FPW; in this example, the two paths of later-stage equipment trigger signals are trigger signals for triggering two light supplementing devices;
as shown in fig. 7, the two-way drive output circuit 60 includes an and gate U61, and two-way isolation drive output circuits; the round-robin enabling signal FPW enables the two paths of isolation driving output circuits to conduct alternately; the two input ends of the AND gate U61 are respectively connected with the frequency limiting signal TEN and the pulse width limited trigger signal DRV, and the output end of the AND gate U61 is connected with the respective input ends of the two paths of isolation driving output circuits;
the first path of isolation driving output circuit comprises resistors R61, R62, R63, R64, R65 and R66, NPN triodes Q61 and Q62, an optocoupler OP1, a light emitting diode LED61, a capacitor C61, a transient suppression diode TV61 and a fuse F61;
one ends of the resistors R63 and R64 are connected with a round robin enabling signal FPW, the other end of the resistor R63 is connected with a voltage VCC and a collector electrode of the triode Q61, the other end of the resistor R64 is connected with a base electrode of the triode Q61, and an emitter electrode of the triode Q61 is connected with an anode of an input end of the optocoupler OP 1; the cathode of the input end of the optocoupler OP1 is connected with the anode of the light emitting diode LED61, the cathode of the light emitting diode LED61 is connected with the collector of the triode Q62 through the resistor R65, the emitter of the triode Q62 is grounded, the base of the triode Q62 is connected with one end of the resistor R62, the other end of the resistor R62 is connected with the output end of the AND gate U61, and the other end of the resistor R62 is connected with the voltage VCC through the resistor R61; the collector of the output end of the optical coupler OP1 is connected with one end of a resistor R66, the cathode of a transient suppression diode TV61 and one end of a fuse F61, the other end of the resistor R66 is connected with one end of a capacitor C61, and the other end of the capacitor C61 and the anode of the transient suppression diode TV61 are connected with the emitter of the output end of the optical coupler OP 1; two output ends of the optical coupler OP1 output a first path of later-stage equipment trigger signal;
the second path of isolation driving output circuit comprises resistors R71, R72, R73, R74, R75 and R76, a PNP triode Q71, an NPN triode Q72, an optocoupler OP2, a light emitting diode LED71, a capacitor C71, a transient suppression diode TV71 and a fuse F71;
one end of the resistor R73 and one end of the resistor R74 are connected with the round trip enable signal FPW, the other end of the resistor R73 is connected with the voltage VCC and the emitting electrode of the triode Q71, the other end of the resistor R74 is connected with the base electrode of the triode Q71, and the collecting electrode of the triode Q71 is connected with the anode of the input end of the optocoupler OP 2; the cathode of the input end of the optocoupler OP2 is connected with the anode of the light emitting diode LED71, the cathode of the light emitting diode LED71 is connected with the collector of the triode Q72 through the resistor R75, the emitter of the triode Q72 is grounded, the base of the triode Q72 is connected with one end of the resistor R72, the other end of the resistor R72 is connected with the output end of the AND gate U61, and the other end of the resistor R72 is connected with the voltage VCC through the resistor R71; the collector of the output end of the optical coupler OP2 is connected with one end of a resistor R76, the cathode of a transient suppression diode TV71 and one end of a fuse F71, the other end of the resistor R76 is connected with one end of a capacitor C71, and the other end of the capacitor C71 and the anode of the transient suppression diode TV71 are connected with the emitter of the output end of the optical coupler OP 2; two output ends of the optical coupler OP2 output a second-path post-stage device trigger signal.
Finally, it should be noted that the above-mentioned embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same, and although the present invention has been described in detail with reference to examples, it should be understood by those skilled in the art that modifications and equivalents may be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention, and all such modifications and equivalents are intended to be encompassed in the scope of the claims of the present invention.

Claims (7)

1. The utility model provides a two way round patrol pulse width frequency variable trigger signal generation controller which characterized in that includes:
a power supply circuit (10), a clock signal generating circuit (20), an adjustable pulse width limiting circuit (30), an adjustable pulse frequency limiting circuit (40), a trigger signal and enable signal generating circuit (50) and a two-way driving output circuit (60);
the power supply circuit (10) provides respective required direct current voltages for the clock signal generating circuit (20), the adjustable pulse width limiting circuit (30), the adjustable pulse frequency limiting circuit (40), the trigger signal and enabling signal generating circuit (50) and the two-way driving output circuit (60);
the clock signal generation circuit (20) is used for generating a clock signal CLK and is used as a clock input of the adjustable pulse frequency limiting circuit (40);
the adjustable pulse frequency limiting circuit (40) is used for generating a frequency limiting signal TEN with a frequency capable of being set and adjusted according to an input clock signal CLK and adjustment setting, and the frequency limiting signal TEN is used as a signal input of the two-way driving output circuit (60);
the input of the trigger signal and enabling signal generating circuit (50) is a front-stage output trigger signal and is used for generating a trigger pulse signal TRP corresponding to the front-stage output trigger signal and a round-robin enabling signal FPW; the trigger pulse signal TRP is used as a signal input of the adjustable pulse width limiting circuit (30), and the round trip enable signal FPW is used as a round trip control input of the two-way driving output circuit (60);
the adjustable pulse width limiting circuit (30) generates a pulse width limited trigger signal DRV with a settable and adjustable pulse width according to the inputted trigger pulse signal TRP and the adjustment setting, and the pulse width limited trigger signal DRV is used as the other signal input of the two-way driving output circuit (60);
the double-path driving output circuit (60) outputs two paths of rear-stage equipment trigger signals with adjustable frequency and pulse width in a round-robin manner according to the input frequency limit signal TEN, the pulse width limit rear trigger signal DRV and the round-robin enabling signal FPW;
the trigger signal and enable signal generating circuit (50) comprises a voltage comparator U51, a NAND gate U52, a D trigger U53, resistors R51, R52, R53, R54, R55, capacitors C51, C52, C53, a transient suppression diode TV51, magnetic beads FB1 and FB2;
the output trigger signals TR+ and TR-of the front stage are respectively connected with the cathode and the anode of the transient suppression diode TV 51; one end of the magnetic bead FB1 and one end of the capacitor C51 are connected with the cathode of the transient suppression diode TV51, and one end of the magnetic bead FB2 and the other end of the capacitor C8 are connected with the anode of the transient suppression diode TV 51; the other end of the magnetic bead FB1 is connected with one end of a resistor R51, one end of a capacitor C52 and the non-inverting input end of a voltage comparator U51, and the other end of the magnetic bead FB2 and the other end of the capacitor C52 are grounded; the other end of the resistor R51 is connected with the voltage VCC and one end of the resistor R52, the other end of the resistor R52 is connected with one end of the resistor R53, one end of the capacitor C53 and the inverting input end of the voltage comparator U51, and the other end of the resistor R53 and the other end of the capacitor C53 are grounded; the output end of the voltage comparator U51 is connected with two input ends of the NAND gate U52 and the clock end of the D trigger U53; the output end of the NAND gate U52 outputs a trigger pulse signal TRP; the Q non-output end of the D trigger U53 is connected with the D end, the R end of the D trigger U53 is connected with the voltage VCC through a resistor R55, the S end of the D trigger U53 is connected with the voltage VCC through a resistor R54, and the Q output end of the D trigger U53 outputs a round robin enabling signal FPW;
the two-way drive output circuit (60) comprises an AND gate U61 and two-way isolation drive output circuits; the round-robin enabling signal FPW enables the two paths of isolation driving output circuits to conduct alternately; the two input ends of the AND gate U61 are respectively connected with the frequency limiting signal TEN and the pulse width limited trigger signal DRV, and the output end of the AND gate U61 is connected with the respective input ends of the two paths of isolation driving output circuits.
2. The two-way round trip pulse width frequency variable trigger signal generation controller of claim 1, wherein,
the power supply circuit (10) comprises a rectifier bridge, a fuse F1, an inductor L1, a transient suppression diode (TV 1), capacitors C1, C2, C3 and C4, a DC/DC chip U1, a light-emitting diode (LED 1) and a resistor R1; the two input ends of the rectifier bridge are respectively connected with the two terminals of the connecting seat J1, the positive output end of the rectifier bridge is connected with one end of the fuse F1, the other end of the fuse F1 is connected with one end of the inductor L1 and the cathode of the transient suppression diode TV1, and the negative output end of the rectifier bridge and the anode of the transient suppression diode TV1 are grounded; the other end of the inductor L1 is connected with the anode of the capacitor C1, one end of the capacitor C2 and the input end of the DC/DC chip U1, and the cathode of the capacitor C1, the other end of the capacitor C2 and the grounding end of the DC/DC chip U1 are grounded; the output end of the DC/DC chip U1 is connected with the anode of the capacitor C3, one end of the capacitor C4 and the anode of the light-emitting diode LED1, and outputs voltage VCC; the cathode of the capacitor C3 and the other end of the capacitor C4 are grounded, and the cathode of the light emitting diode LED1 is grounded through a resistor R1.
3. The two-way round trip pulse width frequency variable trigger signal generation controller of claim 1, wherein,
the clock signal generating circuit (20) comprises resistors R21, R22, R23 and R24, a timer chip U21, an AND gate U22, capacitors C21, C22 and C23; wherein the timer chip U21 adopts ICM7555; the seventh pin of the timer chip U21 is connected with one end of a resistor R21 and one end of a resistor R22, the other end of the resistor R22 is connected with one end of a resistor R23, and the other end of the resistor R23 is connected with the second pin and the sixth pin of the timer chip U21 and is grounded through a capacitor C22; the other end of the resistor R21, the fourth pin and the eighth pin of the timer chip U21, one end of the capacitor C21 and one end of the resistor R24 are connected with the voltage VCC; the other end of the capacitor C21 is grounded; the first pin of the timer chip U21 is grounded, and the fifth pin is grounded through a capacitor C23; the third pin of the timer chip U21 is connected to the other end of the resistor R24, and to both inputs of the and gate U22, and the output of the and gate U22 outputs the clock signal CLK.
4. The two-way round trip pulse width frequency variable trigger signal generation controller of claim 1, wherein,
the adjustable pulse frequency limiting circuit (40) comprises a four-bit binary counter U41, NAND gates U42 and U43, an AND gate U44, jumpers JP5, JP6, JP7, JP8 and a capacitor C41;
the first pin of the four-bit binary counter U41 is connected with the output end of the AND gate U44, and the two input ends of the AND gate U44 are connected with a clear signal CLR; the second pin of the counter U41 is connected with a clock signal CLK, the third pin is connected with a voltage VCC through a resistor R42, the fourth pin is connected with the voltage VCC through a resistor R43, the fifth pin is connected with the voltage VCC through a resistor R44, the sixth pin is connected with the voltage VCC through a resistor R45, and the seventh pin of the counter U41 is connected with the output end of the NAND gate U42 and two input ends of the NAND gate U43; the ninth pin and the tenth pin of the counter U41 are connected with the voltage VCC through a resistor R41, and the eighth pin of the counter U41 is grounded; a tenth pin of the counter U41 is connected with one end of a jumper JP8, a twelfth pin is connected with one end of a jumper JP7, a thirteenth pin is connected with one end of a jumper JP6, and a fourteenth pin is connected with one end of a jumper JP 5; one end of the other termination resistor R47 of the jumper JP5 and one input end of the NAND gate U42, and one end of the other termination resistor R46 of the jumpers JP6, JP7, JP8 and the other input end of the NAND gate U42; the other ends of the resistors R46 and R47 are connected with voltage VCC, the positive electrode of the capacitor C41 is connected with voltage VCC, and the negative electrode is grounded; the output of the nand gate U43 generates a frequency-limited signal TEN with a frequency that can be set and adjusted.
5. The two-way round trip pulse width frequency variable trigger signal generation controller of claim 1, wherein,
the frequency of the frequency-limited signal TEN is several hertz.
6. The two-way round trip pulse width frequency variable trigger signal generation controller of claim 1, wherein,
the adjustable pulse width limiting circuit (30) comprises a voltage comparator U31, a NAND gate U32, an AND gate U33, resistors R31, R32 and R33, capacitors C31, C32, C33, C34 and C35;
one end of the resistor R31 is connected with the voltage VCC, and the other end of the resistor R32, one end of the capacitor C31 and the inverting input end of the voltage comparator U31; the other end of the resistor R32 and the other end of the capacitor C31 are grounded; one end of the resistor R33 contacts the pulse signal TRP, and one end of the and gate U33; the other end of the resistor R33 is connected with one ends of the capacitors C32, C33, C34 and C35 and the non-inverting input end of the voltage comparator U31; the other end of the capacitor C32 is connected with one end of a jumper wire JP4, and the other end of the jumper wire JP4 is grounded; the other end of the capacitor C33 is connected with one end of a jumper wire JP3, and the other end of the jumper wire JP3 is grounded; the other end of the capacitor C34 is connected with one end of a jumper wire JP2, and the other end of the jumper wire JP2 is grounded; the other end of the capacitor C35 is connected with one end of a jumper wire JP1, and the other end of the jumper wire JP1 is grounded; the output end of the voltage comparator U31 is connected with two input ends of the NAND gate U32, the output end of the NAND gate U32 is connected with the other input end of the AND gate U33, the output end of the NAND gate U32 generates a clear signal CLR, and the output end of the AND gate U33 generates a pulse width limited trigger signal DRV.
7. The two-way round trip pulse width frequency variable trigger signal generation controller of claim 1, wherein,
the first path of isolation driving output circuit comprises resistors R61, R62, R63, R64, R65 and R66, NPN triodes Q61 and Q62, an optocoupler OP1, a light emitting diode LED61, a capacitor C61, a transient suppression diode TV61 and a fuse F61;
one ends of the resistors R63 and R64 are connected with a round robin enabling signal FPW, the other end of the resistor R63 is connected with a voltage VCC and a collector electrode of the triode Q61, the other end of the resistor R64 is connected with a base electrode of the triode Q61, and an emitter electrode of the triode Q61 is connected with an anode of an input end of the optocoupler OP 1; the cathode of the input end of the optocoupler OP1 is connected with the anode of the light emitting diode LED61, the cathode of the light emitting diode LED61 is connected with the collector of the triode Q62 through the resistor R65, the emitter of the triode Q62 is grounded, the base of the triode Q62 is connected with one end of the resistor R62, the other end of the resistor R62 is connected with the output end of the AND gate U61, and the other end of the resistor R62 is connected with the voltage VCC through the resistor R61; the collector of the output end of the optical coupler OP1 is connected with one end of a resistor R66, the cathode of a transient suppression diode TV61 and one end of a fuse F61, the other end of the resistor R66 is connected with one end of a capacitor C61, and the other end of the capacitor C61 and the anode of the transient suppression diode TV61 are connected with the emitter of the output end of the optical coupler OP 1; two output ends of the optical coupler OP1 output a first path of later-stage equipment trigger signal;
the second path of isolation driving output circuit comprises resistors R71, R72, R73, R74, R75 and R76, a PNP triode Q71, an NPN triode Q72, an optocoupler OP2, a light emitting diode LED71, a capacitor C71, a transient suppression diode TV71 and a fuse F71;
one end of the resistor R73 and one end of the resistor R74 are connected with the round trip enable signal FPW, the other end of the resistor R73 is connected with the voltage VCC and the emitting electrode of the triode Q71, the other end of the resistor R74 is connected with the base electrode of the triode Q71, and the collecting electrode of the triode Q71 is connected with the anode of the input end of the optocoupler OP 2; the cathode of the input end of the optocoupler OP2 is connected with the anode of the light emitting diode LED71, the cathode of the light emitting diode LED71 is connected with the collector of the triode Q72 through the resistor R75, the emitter of the triode Q72 is grounded, the base of the triode Q72 is connected with one end of the resistor R72, the other end of the resistor R72 is connected with the output end of the AND gate U61, and the other end of the resistor R72 is connected with the voltage VCC through the resistor R71; the collector of the output end of the optical coupler OP2 is connected with one end of a resistor R76, the cathode of a transient suppression diode TV71 and one end of a fuse F71, the other end of the resistor R76 is connected with one end of a capacitor C71, and the other end of the capacitor C71 and the anode of the transient suppression diode TV71 are connected with the emitter of the output end of the optical coupler OP 2; two output ends of the optical coupler OP2 output a second-path post-stage device trigger signal.
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