CN109411468B - SCR electrostatic protection device - Google Patents

Abstract

The invention provides a silicon controlled electrostatic protection device which comprises a substrate, a buried oxide layer, an N well and a P well, wherein a first P + injection region, a first polysilicon gate, a second P + injection region and a fourth N + injection region are arranged in the N well, a first N + injection region, a second polysilicon gate, a second N + injection region and a fourth P + injection region are arranged in the P well, the third P + injection region and the third N + injection region are bridged at the junction between the N well and the P well, the first P + injection region is connected with an anode, the first N + injection region is connected with a cathode, the first P + injection region, the first polysilicon gate, the second P + injection region and the N well form a PMOS (P-channel metal oxide semiconductor) tube, and the first N + injection region, the second polysilicon gate, the second N + injection region and the P well form an NMOS (N-channel metal oxide semiconductor) tube. The invention has the advantages of low trigger voltage, high maintenance voltage, simple structure, easy integration, high robustness and the like, and is suitable for electrostatic protection of devices and circuits.

Description

SCR electrostatic protection device

technical field

The invention relates to the technical field of integrated circuit electrostatic protection, in particular to a thyristor electrostatic protection device.

Background technique

With the development of Moore's Law, the integration of chips has been continuously improved, and the power consumption and performance have been greatly improved. However, after the development of bulk silicon technology to 28nm, the technical complexity and manufacturing cost have greatly increased, and fully depleted silicon-on-insulator (FDSOI) has emerged as the times require. Under the same technology node, FDSOI technology can effectively reduce the manufacturing process, reduce chip power consumption, improve product yield, and has strong radiation resistance performance. Due to its advantages in price, power consumption and performance, FDSOI has gradually become a mainstream technology in applications such as the Internet of Things.

Electrostatic discharge (Electro Static Discharge, ESD) is the main reason for the failure of integrated circuits. Because FDSOI has the characteristics of full dielectric isolation, when electrostatic bombards the device, the electrostatic current cannot be discharged to the ground through the buried oxide layer, so the electrostatic protection capability of FDSOI device is much worse than that of bulk silicon device. Generally speaking, the SCR path is realized by implanting N+ impurities in the P well and P+ impurities in the N well, using the lateral parasitic PNP and the lateral parasitic NPN structure.

However, the thickness of the bulk silicon of the FDSOI device is very thin, and both the N+ implantation region and the P+ implantation region are deep into the surface of the buried oxide layer, and the formed positive feedback structure has a small current magnification. The trigger point of the traditional FDSOI electrostatic protection device is located at the junction of the P well and the N well, and has a high trigger voltage. When the trigger voltage exceeds the source-drain breakdown voltage of the device, the device will be burned and the current cannot be effectively discharged.

SUMMARY OF THE INVENTION

In view of the above situation, the purpose of the present invention is to solve the problem that the device is burnt due to the high trigger voltage of the existing electrostatic protection device.

The present invention provides a thyristor electrostatic protection device, which includes a substrate, a buried oxide layer arranged in the substrate, an N well and a P well arranged in the buried oxide layer, and the N well is located in the N well. A first P+ implantation region, a first polysilicon gate, a second P+ implantation region and a fourth N+ implantation region are arranged therein, and a first N+ implantation region, a second polysilicon gate, a first N+ implantation region, a second polysilicon gate, a fourth N+ implantation region are arranged in the P well Two N+ implanted regions and a fourth P+ implanted region, the third P+ implanted region and the third N+ implanted region are bridged at the junction between the N well and the P well, and the first P+ implanted region is connected to the anode , the first N+ implantation region is connected to the cathode, the first P+ implantation region, the first polysilicon gate, the second P+ implantation region and the N well form a PMOS tube, the first N+ implantation region The implantation region, the second polysilicon gate, the second N+ implantation region and the P well constitute an NMOS transistor.

In the thyristor electrostatic protection device proposed by the invention, when a positive pulse occurs at the anode, avalanche breakdown occurs at the junction of the N-well-P+ injection region and the N+ injection region-P-well junction, and the generated holes go to the cathode with a lower potential. At the same time, when the embedded NMOS tube is triggered, it will inject hole current into the P well, effectively increasing the potential of the P well; when the embedded PMOS tube is triggered, it will inject electron current into the N well, Thereby, the N-well potential is effectively reduced. Since three current discharge paths from anode to cathode are provided, the discharge current intensity is greatly increased, and the secondary failure current is improved, that is, good ESD robustness can be maintained. Compared with the conventional FDSOI thyristor device structure, the NMOS tube and PMOS tube are embedded in the SCR path, thereby improving its electrostatic discharge efficiency, and at the same time adding multiple SCR paths, improving the current discharge speed, and has low triggering voltage, high sustain voltage, ease of integration, and high robustness.

In addition, the thyristor electrostatic protection device proposed by the present invention may also have the following additional technical features:

The thyristor electrostatic protection device, wherein the first P+ injection region, the N well and the second P+ injection region constitute a first PNP transistor, the N well and the second P+ injection region , the third P+ implantation region, the fourth P+ implantation region, the P well and the first N+ implantation region constitute a first NPN transistor.

The thyristor electrostatic protection device, wherein the first N+ injection region and the N well form a first forward diode, the parasitic resistance in the N well forms the first N well parasitic resistance, the second The P+ injection region, the third P+ injection region, the fourth P+ injection region, and the parasitic resistance in the P well constitute the first P well parasitic resistance.

The thyristor electrostatic protection device, wherein the first P+ implantation region, the N well, the fourth N+ implantation region, the third N+ implantation region, the second N+ implantation region, and the The P well constitutes a second PNP transistor, and the second N+ implantation region, the P well, and the first N+ implantation region constitute a second NPN transistor.

The thyristor electrostatic protection device, wherein the first N+ implantation region and the P well constitute a second forward diode, the N well, the fourth N+ implantation region, and the third N+ implantation region , and the parasitic resistance in the second N+ injection region constitutes a second N-well parasitic resistance, and the parasitic resistance in the P-well constitutes a second P-well parasitic resistance.

The thyristor electrostatic protection device, wherein the first P+ injection region, the N well and the P well constitute a third PNP transistor, the N well, the P well and the first The N+ injection region constitutes a third NPN transistor.

In the thyristor electrostatic protection device, the parasitic resistance in the N-well constitutes a third N-well parasitic resistance, and the parasitic resistance in the P-well constitutes a third P-well parasitic resistance.

The thyristor electrostatic protection device, wherein the thyristor electrostatic protection device has three electrostatic discharge paths from the anode to the cathode, and the first path is the first P+ injection region, the N well, the the second P+ implantation region, the third P+ implantation region, the fourth P implantation region, the P well and the first N+ implantation region, and the second path is the first P+ implantation region, the the N well, the fourth N+ implantation region, the third N+ implantation region, the second N+ implantation region, the P well and the first N+ implantation region, and the third path is the first A P+ implantation region, the N well, the P well, and the first N+ implantation region.

The SCR ESD protection device, wherein the first P+ implantation region, the N well, the second P+ implantation region, the third P+ implantation region, the fourth P+ implantation region and the The P well constitutes the first PNPN thyristor structure, the first P+ implantation region, the N well, the fourth N+ implantation region, the third N+ implantation region, the second N+ implantation region, the The P well and the first N+ implantation region constitute a second PNPN thyristor structure.

In the thyristor electrostatic protection device, the first P+ injection region, the N well, the P well and the first N+ injection region constitute a third PNPN type thyristor structure.

Description of drawings

Figure 1 is a cross-sectional view of a common FDSOI thyristor electrostatic protection device;

Fig. 2 is the layout of the FDSOI thyristor electrostatic protection device shown in the present invention;

Fig. 3 is the sectional view of the middle thyristor electrostatic protection device shown in Fig. 2 of the present invention along A-A' tangent;

Fig. 4 is the cross-sectional view of the middle thyristor electrostatic protection device shown in Fig. 2 of the present invention along B-B' tangent;

Fig. 5 is the sectional view of the middle thyristor electrostatic protection device shown in Fig. 2 of the present invention along the C-C' tangent;

Fig. 6 is the equivalent circuit diagram of the first relief passage of the present invention;

Fig. 7 is the equivalent circuit diagram of the second relief passage of the present invention;

FIG. 8 is an equivalent circuit diagram of the third relief passage of the present invention.

Detailed ways

In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Several embodiments of the invention are presented in the accompanying drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It should be noted that when an element is referred to as being "fixed to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical", "horizontal", "left", "right", "upper", "lower" and similar expressions used herein are for the purpose of illustration only and do not indicate or imply the referred device or Elements must have a particular orientation, be constructed and operate in a particular orientation and are therefore not to be construed as limitations of the invention.

In the present invention, unless otherwise expressly specified and limited, the terms "installed", "connected", "connected", "fixed" and other terms should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection , or integrally connected; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or the internal communication between the two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

In the prior art, the bulk silicon thickness of the FDSOI device is very thin, the N+ implantation region and the P+ implantation region are both deep into the surface of the buried oxide layer, and the formed positive feedback structure has a small current magnification. The trigger point of the traditional FDSOI electrostatic protection device is located at the junction of the P well and the N well, and has a high trigger voltage. When the trigger voltage exceeds the source-drain breakdown voltage of the device, the device will be burned and the current cannot be effectively discharged.

In order to solve this technical problem, the present invention proposes a thyristor electrostatic protection device, a thyristor electrostatic protection device, please refer to FIG. 1 to FIG. 8 , the thyristor electrostatic protection device proposed by the present invention includes a substrate 01. The buried oxide layer 02 provided in the substrate 01, the N well 11 and the P well 12 provided in the buried oxide layer 02. It should be pointed out here that the above-mentioned substrate 01 is a P-type silicon substrate.

Please refer to FIGS. 2 to 5 . Specifically, the N well 11 is provided with, from left to right, a first P+ implantation region 13 , a first polysilicon gate 14 , a second P+ implantation region 15 and a fourth N+ implantation region 13 . Implantation region 22 . The above-mentioned P well 12 is provided with, from left to right, a second N+ implantation region 20 , a second polysilicon gate 19 , a first N+ implantation region 18 and a fourth P+ implantation region 17 . Wherein, the third P+ injection region 16 and the third N+ injection region 21 are bridged at the boundary position between the P well 12 and the N well 11 , the above-mentioned first P+ injection region 13 is connected to the anode, and the above-mentioned first N+ injection region Region 18 is connected to the cathode.

For the thyristor electrostatic protection device proposed by the present invention, there are three electrostatic discharge paths, which are a cross-sectional view along the AA' tangent, a cross-sectional view along the BB' tangent, and a cross-sectional view along the CC' tangent. sectional view shown. FIG. 6 , FIG. 7 and FIG. 8 are corresponding equivalent circuit diagrams, respectively.

Specifically, FIG. 6 is an equivalent circuit of the first bleed path. The first P+ injection region 13 , the N well 11 and the second P+ injection region 15 constitute the first PNP transistor Qp ₁ , the N well 11 and the second P+ The implantation region 15 , the third P+ implantation region 16 , the fourth P+ implantation region 17 , the P well 12 and the first N+ implantation region 18 constitute the first NPN transistor Qn1 . The above-mentioned first P+ implantation region 13 , N well 11 , second P+ implantation region 15 and first polysilicon gate 14 constitute a PMOS transistor Mp.

At the same time, the above-mentioned P well 12 and the first N+ implantation region 18 form a forward diode D2. The parasitic resistance in the above-mentioned N-well constitutes the first N-well parasitic resistance Rnw ₁ ; the above-mentioned parasitic resistances of the second P+ injection region 15 , the third P+ injection region 16 , the fourth P+ injection region 17 and the P-well 12 constitute the first P Well parasitic resistance Rpw ₁ .

For the first venting path, the corresponding paths are: first P+ implantation region 13, N well 11, second P+ implantation region 15, third P+ implantation region 16, fourth P implantation region 17, P well 12 and the first N+ implantation region 18 .

Please refer to FIG. 7. FIG. 7 is an equivalent circuit of the second bleeder path. The above-mentioned first P+ implantation region 13, N well 11, fourth N+ implantation region 22, third N+ implantation region 21, and second N+ implantation region The region 20 and the P well 12 constitute the second PNP transistor Qp2, and the above-mentioned second N+ implantation region 20, the P well 12 and the first N+ implantation region 18 constitute the second NPN transistor Qn2. The first N+ implantation region 18 , the second polysilicon gate 19 , the second N+ implantation region 20 and the P well 12 constitute the NMOS transistor Mn. The first P+ implantation region 13 and the N well 11 form a forward diode D1. The parasitic resistances in the N well 11 , the fourth N+ injection region 22 , the third N+ injection region 21 and the second N+ injection region 20 constitute the second N well parasitic resistance Rnw2 , and the parasitic resistance of the P well 12 constitutes the second P well parasitic resistance Rpw2.

For the second discharge path, the corresponding paths are: the first P+ implantation region 13, the N well 11, the fourth N+ implantation region 22, the third N+ implantation region 21, the The second N+ implantation region 20 , the P well 12 and the first N+ implantation region 18 .

Please refer to FIG. 8 . FIG. 8 is an equivalent circuit of the third drain path. The above-mentioned first P+ implantation region 13 , N well 11 and P well 12 constitute a third PNP transistor Qp3 . The above-mentioned N well 11 , P well 12 and first N+ implantation region 18 constitute a third NPN transistor Qn3 . The parasitic resistance in the N-well 11 constitutes a third N-type parasitic resistance Rnw3, and the parasitic resistance of the P-well 12 constitutes a third P-type parasitic resistance Rpw3.

For the third drain path, the corresponding paths are: the first P+ implantation region 13 , the N well 11 , the P well 12 , and the first N+ implantation region 18 .

In practical applications, when a positive pulse occurs at the anode, avalanche breakdown occurs at the N-well-P+ junction and the N+-P well junction, the generated holes move to the cathode with a lower potential, and electrons move to the anode with a higher potential , At the same time, the embedded NMOS tube will trigger, which will inject hole current into the P well 12, effectively increasing the potential of the P well; the embedded PMOS tube will also trigger, and will inject electron current into the N well 11, Effectively reduce the N-well potential.

Taking the first discharge path as an example, the holes generated by the avalanche breakdown generate a voltage drop on the first P-type parasitic resistance Rpw1, which also causes the potential in the P-well 12 to increase. When the potential rises above the turn-on voltage, the first NPN transistor Qn1 is induced to be turned on. The electrons generated by the avalanche breakdown cause the potential of the N well 11 to decrease, and induce the first PNP transistor Qp1 to be turned on. Qn1 and Qp1 form a positive feedback loop, which makes the discharge current increase continuously. Since three current discharge paths from anode to cathode are provided, the discharge current intensity is greatly increased, and the secondary failure current is improved, that is, good ESD robustness can be maintained. Compared with the conventional FDSOI thyristor device structure, NMOS and PMOS are embedded in the SCR path to improve the electrostatic discharge efficiency, and at the same time, multiple SCR paths are added to improve the current discharge speed, and it has low trigger voltage, high It has the advantages of maintaining voltage, easy integration, high robustness, simple structure, and no need to increase the mask, so it is general.

The first P+ implantation region 13, the N well 11, the second P+ implantation region 15, the third P+ implantation region 16, the fourth P+ implantation region 17 and the P well 12 constitute the first PNPN type SCR structure, and the first P+ implantation region 13. The N well 11 , the fourth N+ implantation region 22 , the third N+ implantation region 21 , the second N+ implantation region 20 , the P well 12 and the first N+ implantation region 18 constitute a second PNPN thyristor structure. The first P+ implantation region 13 , the N well 11 , the P well 12 and the first N+ implantation region 18 constitute a third PNPN thyristor structure.

In the thyristor electrostatic protection device proposed by the invention, when a positive pulse occurs at the anode, avalanche breakdown occurs at the junction of the N-well-P+ injection region and the N+ injection region-P-well junction, and the generated holes go to the cathode with a lower potential. At the same time, when the embedded NMOS tube is triggered, it will inject hole current into the P well, effectively increasing the potential of the P well; when the embedded PMOS tube is triggered, it will inject electron current into the N well, Thereby, the N-well potential is effectively reduced. Since three current discharge paths from anode to cathode are provided, the discharge current intensity is greatly increased, and the secondary failure current is improved, that is, good ESD robustness can be maintained. Compared with the conventional FDSOI thyristor device structure, the NMOS tube and PMOS tube are embedded in the SCR path, thereby improving its electrostatic discharge efficiency, and at the same time adding multiple SCR paths, improving the current discharge speed, and has low triggering voltage, high sustain voltage, ease of integration, and high robustness.

The above-mentioned embodiments only represent the preferred embodiments of the present invention, and the descriptions thereof are specific and detailed, but should not be construed as limiting the scope of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can also be made, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention should be subject to the appended claims.

Claims (10)

1. The silicon controlled electrostatic protection device is characterized by comprising a substrate, a buried oxide layer arranged in the substrate, an N well and a P well which are arranged in the buried oxide layer, a first P + injection region, a first polysilicon gate, a second P + injection region and a fourth N + injection region are arranged in the N well, a first N + injection region, a second polysilicon gate, a second N + injection region and a fourth P + injection region are arranged in the P well, the third P + injection region and the third N + injection region are bridged at the junction between the N well and the P well, the first P + injection region is connected with an anode, the first N + injection region is connected with a cathode, the first P + injection region, the first polysilicon gate, the second P + injection region and the N well form a PMOS tube, the first N + injection region, the second polysilicon gate, the second N + injection region and the P well form an NMOS tube.

2. The scr electrostatic protection device of claim 1, wherein the first P + implant region, the N-well, and the second P + implant region form a first PNP type transistor, and the N-well, the second P + implant region, the third P + implant region, the fourth P + implant region, the P-well, and the first N + implant region form a first NPN type transistor.

3. The scr electrostatic protection device of claim 2, wherein the first P + implant region and the N-well form a first forward diode, wherein a parasitic resistance in the N-well forms a first N-well parasitic resistance, and wherein the second P + implant region, the third P + implant region, the fourth P + implant region, and a parasitic resistance in the P-well form a first P-well parasitic resistance.

4. The scr electrostatic protection device of claim 1, wherein the first P + implant region, the N-well, the fourth N + implant region, the third N + implant region, the second N + implant region, and the P-well form a second PNP transistor, and the second N + implant region, the P-well, and the first N + implant region form a second NPN transistor.

5. The SCR electrostatic protection device of claim 4, wherein said first N + implant region and said P-well constitute a second forward diode, and wherein parasitic resistances in said N-well, said fourth N + implant region, said third N + implant region, and said second N + implant region constitute a second N-well parasitic resistance, and wherein parasitic resistances in said P-well constitute a second P-well parasitic resistance.

6. The scr electrostatic protection device of claim 1, wherein the first P + implant region, the N-well, and the P-well form a third PNP transistor, and the N-well, the P-well, and the first N + implant region form a third NPN transistor.

7. The SCR electrostatic protection device of claim 6, wherein said parasitic resistance in said N-well constitutes a third N-well parasitic resistance and said parasitic resistance in said P-well constitutes a third P-well parasitic resistance.

8. The scr electrostatic protection device of claim 1, wherein three electrostatic discharge paths exist from an anode to a cathode, a first path being the first P + implant region, the N-well, the second P + implant region, the third P + implant region, the fourth P implant region, the P-well, and the first N + implant region, a second path being the first P + implant region, the N-well, the fourth N + implant region, the third N + implant region, the second N + implant region, the P-well, and the first N + implant region, and a third path being the first P + implant region, the N-well, the P-well, and the first N + implant region.

9. The silicon controlled electrostatic protection device according to claim 1, wherein the first P + implantation region, the N well, the second P + implantation region, the third P + implantation region, the fourth P + implantation region, the P well, and the first N + implantation region constitute a first PNPN type silicon controlled structure, and the first P + implantation region, the N well, the fourth N + implantation region, the third N + implantation region, the second N + implantation region, the P well, and the first N + implantation region constitute a second PNPN type silicon controlled structure.

10. The scr electrostatic protection device of claim 1, wherein the first P + implant region, the N-well, the P-well, and the first N + implant region form a third PNPN type scr structure.

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