CN109408916A - A kind of recognition methods of graphics logic configuration - Google Patents
A kind of recognition methods of graphics logic configuration Download PDFInfo
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Abstract
The invention discloses a kind of recognition methods of graphics logic configuration, specially, rendering logic figure, the logic chart drawn are made of logical node and connecting line, and the logic chart drawn is taken pictures or scanned, generate an image file, median filtering and binary conversion treatment are carried out to image file generated, identify logical node and connecting line in image file, traverses logical node, output logical node is found, the logical expression of the output logical node is found out using recursive algorithm.The present invention is significantly reduced again the time cost of configuration, and can reduce the generation of mistake.
Description
Technical field
The present invention relates to a kind of recognition methods of graphics logic configuration, belong to technical field of electric automation.
Background technique
Logical Configuration is a kind of existing technology relative to programming in logic, and programming in logic passes through the logic that will be fixed with height
The form of grade language control statement is compiled into executable program, and then realizes logic control.Such as the latching logic of the substation AVC
(PLC, DCS, relay protection), if calculating block signal using hard coded mode, once latching logic changes (such as
Introduce new barring condition), then program will be rewritten.This control program by hard coded form, once exploitation
It finishes, will be unable to change, if it is desired to being adjusted to logic, must just rewrite code, and imported into equipment.Again it compiles
Code can bring new bug, and development cost is high.There is one kind and is matched by editor in the problem of bringing in face of programming in logic
File mode is set come the method for carrying out logic configuration, the initially Logical Configuration of form, by preset it is a series of can
The parameter of editor is opened to the editor of being customized of engineering staff.By taking power plant rated active power as an example, the volume of power plant A
Determining active power is 600MW, and the rated active power of power plant B is 300MW, all can be by editing in this configuration form
Parameter, to realize the customization configuration of each power plant.Sheet format configures compared with hard coded, reduces time of program code compiling
Number, if program test is abundant, this code can keep stable within some time.Which reduce equipment manufacturer's
Development cost and maintenance cost.But there is also many deficiencies for tabular configuration method, such as not intuitive enough, some logic configurations
There are many parameter, and a screen sees incomplete, Yao Qianhou page turning.Also the incidence relation being difficult to understand between parameters, can not be in a screen
The upper content for checking multiple Logical Configurations.Therefore there is graphics logic configuration again, graphics logic configuration compares sheet format logical groups
State, it is more intuitive, it edits more flexible.Pass through the elements such as addition input node, output node, operator, so that it may generate complicated
Logical expression.By taking AVC latching logic as an example, the barring condition caused extremely if necessary to which a communications status is added, only
This abnormal input signal of communications status and original block signal need to be carried out one<or>operation can be realized as.It is existing
Graphics logic configuration is all to carry out node selection by control mouse and draw line, and entire configuration work must counted all
It is carried out under calculation machine running environment.
Summary of the invention
The technical problem to be solved by the present invention is to overcome the deficiencies of existing technologies, a kind of knowledge of graphics logic configuration is provided
Other method,
In order to solve the above technical problems, the present invention provides a kind of recognition methods of graphics logic configuration, comprising the following steps:
1) rendering logic figure, the logic chart drawn are made of logical node and connecting line, pass through connecting line between logical node
Connection；The logical node is a closed rectangle, signal type identifier is marked in closed rectangle inside, in rectangle
Underface marks signal name；
2) logic chart drawn is taken pictures or is scanned, generate an image file；
3) median filtering and binary conversion treatment are carried out to image file generated；
4) logical node in image file, and the information preservation for each logical node that will acquire, the logic section are identified
The information of point includes: the signal type identifier of logical node, signal name and logical node ID；
5) it identifies connecting line, and the logical node information at connecting line both ends is preserved；
6) logical node is traversed, output logical node is found, finds out the logical expression of the output logical node.
In step 1) above-mentioned, the signal type includes: remote signalling, telemetering, output and operator, wherein remote signalling mark
Symbol uses D, and telemetering identifier uses A, and output identification symbol uses O, and the identifier of operator uses usual mathematic sign；The letter
The string representation that number name is surrounded using a pair of of bracket.
In step 4) above-mentioned, detailed process is as follows for the logical node in identification image file:
41) pictorial symbolization is carried out to font used in logic chart using KNN algorithm；
42) Canny edge detection is carried out to binary image, then carries out statistical probability Hough transformation, identify all complete lines
Section；
43) line segment is traversed, identifies all rectangles；
44) using the identifier in KNN algorithm recognition logic node rectangle, and to logical node one unique ID number；
45) identification signal name；
46) the rectangle bottom edge midpoint of each logical node is calculated at a distance from each signal name top center, it will be apart from most
That small associates to combination, as logical node and its corresponding signal name.
Aforementioned step 45) identification signal name process is as follows:
It 44a) identifies all characters, the character recognized is traversed, all [characters are recorded；
44b) using it is each [character as starting point, find y-coordinate and differed in 2 pixels therewith, x coordinate be greater than should [character x coordinate,
And x coordinate differs that the smallest character, and is to be completed by the character marking found；
44c) continue character late, find y-coordinate with [differ in 2 pixels, x coordinate is greater than step 44b) character that finds
X coordinate, and x coordinate differs the smallest that character, and is to be completed by the character marking found；Until having found one
] character, then the signal name is searched and is terminated；
44d) return step 44b), all signal names are all found.
Step 5) connecting line identification process above-mentioned is as follows:
51) line segment is taken out from the line segment of identification, is completed if the line segment is not marked with, by the line segment and remaining
Line segment carries out intersection detection；
52) it when any one endpoint of the line segment of selection is equal with the coordinate of any one endpoint of another line segment, will select
The intersection counter for the line segment selected adds one；
53) it loops through after terminating, if the counter of line segment is equal to 0 or 1, which is labeled as end line section；
54) the end line section that traversal intersection counter is 0, creates a connection line object, detects each endpoint and logical node
Intersect situation, if the coordinate of endpoint on the vertical segment of logical node, saves the logical node in connection line object
Information；
55) the end line section that traversal counter is 1, detects the intersection situation of endpoint and remaining line segment, if having found a line segment
With end line segment intersection, then the line segment is labeled as being completed, and another endpoint of the line segment and remaining line segment are subjected to phase
Detection is handed over, as soon as until finding an end line section, in this way, a connecting line is constituted, after traversal, by all connected line segments
It is collectively labeled as being completed；
56) detecting step 55) connecting line endpoint and logical node intersection situation, if the coordinate of endpoint is in logical node
Vertical segment on, then connection line object in save the logical node information.
The logical expression solution procedure of step 6) output logical node above-mentioned is as follows:
61) logical node is traversed, output node is found；
62) according to the connection line object where output node, input signal operator logic corresponding with the output node is found out
Node；
63) recursive function is called to the operator logical node, and a pair will be added to include outside the return expression of the recursive function
Number, the expression formula as output node；
64) all connection line objects are traversed, all input signal logic sections corresponding with the operator logical node are found out
Point, and recursive function is called to these input signal logical nodes；If logical node is signal node, it is transferred to step 65)；
If the node is operator logical node, return step 64)；
65) signal name of the logical node is returned；
66) add a pair of of bracket outside the expression formula for returning to each recursive function；
67) these parenthesized expression formulas are connected using the operator of step 63), i.e. logic chart logical table to be expressed
Up to formula.
Advantageous effects of the invention:
Logic chart of the invention can be not only restricted to specific Graphics Configuration System Used, and word, Photoshop, CAD etc. can be used
The software of graphing makes logic chart.The present invention is significantly reduced again the time cost of configuration, and can reduce mistake
Generation.
Detailed description of the invention
Fig. 1 is the method for the present invention flow chart；
Fig. 2 is logical node example；
Fig. 3 is four kinds of identification methods of the rectangle of logical node；
Fig. 4 is connection line object schematic diagram；
Fig. 5 is the logic chart drawn in embodiment.
Specific embodiment
The invention will be further described below.Following embodiment is only used for clearly illustrating technical side of the invention
Case, and not intended to limit the protection scope of the present invention.
As shown in Figure 1, the recognition methods of graphics logic configuration of the invention, comprising the following steps:
Step 1: rendering logic figure, the logic chart drawn are made of logical node and connecting line, pass through company between logical node
Wiring connection.Referring to fig. 2, logical node is a closed rectangle, marks signal type identifier in closed rectangle inside,
Remote signals name or telemetered signal name are marked in the underface of rectangle.
Signal type includes: remote signalling, telemetering, output and operator, and wherein remote signalling identifier uses D, and telemetering identifier is adopted
With A, output identification symbol uses O, operator include with or addition subtraction multiplication and division, be greater than, be less than, etc., identifier is using respective
Usual mathematic sign, such as :+(addition) ,-(subtracting each other), * (multiplication) ,/(being divided by), %(remainder), logical AND), | (logic or), >
(being greater than), < (being less than) etc..
The string representation that remote signals name or telemetered signal name are surrounded using a pair of of bracket, such as: [yx1].
Step 2: the logic chart drawn being taken pictures or scanned, an image file is generated.
Step 3: median filtering and binary conversion treatment are carried out to image file generated.
Step 4: recognition logic node, and the information preservation for each logical node that will acquire, the information of logical node
Include: the signal type identifier and logical node ID of logical node, remote signalling letter is also saved for remote signals and telemetered signal
Number name or telemetered signal name.
The identification process of the rectangle of logical node are as follows:
41) pictorial symbolization is carried out to font used in logic chart using KNN algorithm；
42) Canny edge detection is carried out to binary image, then carries out statistical probability Hough transformation, identify all complete lines
Section.
43) according to the combined situation of line segment, all rectangles are identified, referring to Fig. 3, one shares 4 kinds of identification process.
431) from the line segment detected, a line segment (unmarked is to be completed) is taken out in order, if the line segment
The x coordinate of two endpoints is equal, then the line segment is just vertical segment, if the y-coordinate of two endpoints of the line segment is equal, that
The line segment is just parallel segment.Recording the line segment is line segment 1.
432) line segment 2 is then looked for,
The case where being vertical segment for line segment 1, there are two ways to find line segment 2:
A, by the top coordinate x and y of line segment 1 and all unmarked left side extreme coordinates x and y for completed horizontal line section into
Row comparison, if extreme coordinates x and y on the left of some horizontal line section, with the top coordinate x of line segment 1 compared with y, coordinate x difference exists
In 2 pixels, coordinate y is differed in 2 pixels, then the horizontal line section is exactly line segment 2 to be detected, this step terminates, under
One step；If can't detect the horizontal line section of the condition of satisfaction, found in the way of situation b.
B, by the bottom coordinate x and y of line segment 1 and all unmarked right side extreme coordinates x for completed horizontal line section
It is compared with y, if extreme coordinates x and y on the right side of some horizontal line section, with the bottom coordinate x of line segment 1 compared with y, coordinate x
Difference is in 2 pixels, and coordinate y is differed in 2 pixels, then the horizontal line section is exactly line segment 2 to be detected, this step terminates,
Into next step；If can't detect the horizontal line section of the condition of satisfaction, the line segment 1, return step 431 are skipped) it opens again
Begin to find, until finding line segment 2 or having traversed all line segments.
The case where being horizontal line section for line segment 1, equally exists two ways and finds line segment 2:
C, by the right side coordinate x and y of line segment 1 and remaining unmarked top end coordinate x and y for completed vertical segment into
Row comparison, if top end the coordinate x and y of some vertical segment, with the right side extreme coordinates x of line segment 1 compared with y, x difference
In 2 pixels, y is differed in 2 pixels, then the vertical segment is exactly line segment 2 to be detected, this step terminates, and entrance is next
Step；If can't detect the horizontal line section of the condition of satisfaction, found in the way of situation d.
D, by the left side coordinate x and y of line segment 1 and remaining unmarked bottom extreme coordinates x for completed vertical segment
It is compared with y, if bottom the extreme coordinates x and y of some vertical segment, with the left side extreme coordinates x of line segment 1 compared with y,
X is differed in 2 pixels, and y is differed in 2 pixels, then the vertical segment is exactly line segment 2 to be detected, this step terminates, into
Enter next step；If can't detect the horizontal line section of the condition of satisfaction, the line segment 1, return step 431 are skipped) restart
It finds, until finding line segment 2 or having traversed all line segments.
433) according to the four of step 432) kinds of situations, line segment 3 is continually looked for.
A, the right side extreme coordinates of line segment 2 and remaining all unmarked top end for completed vertical segment are sat
Mark is compared, if top end the coordinate x and y of some vertical segment, with the right side extreme coordinates x of line segment 2 compared with y, and x
Difference is in 2 pixels, and y is differed in 2 pixels, then the vertical segment is exactly line segment 3 to be detected, this step terminates, and enters
Next step；If can't detect the vertical segment of the condition of satisfaction, found in the way of situation b.
B, the left side extreme coordinates of line segment 2 and remaining all unmarked bottom endpoint for completed vertical segment are sat
Mark is compared, if bottom the extreme coordinates x and y of some vertical segment, with the left side extreme coordinates x of line segment 2 compared with y, and x
Difference is in 2 pixels, and y is differed in 2 pixels, then the vertical segment is exactly line segment 3 to be detected, this step terminates, and enters
Next step；If can't detect the vertical segment of the condition of satisfaction, the line segment 2, return step 431 are skipped) restart to seek
It looks for, until finding line segment 3 or having traversed all line segments.
C, the bottom extreme coordinates of line segment 2 and remaining all unmarked right side endpoint for completed horizontal line section are sat
Mark is compared, if right side the extreme coordinates x and y of some horizontal line section, with the bottom extreme coordinates x of line segment 2 compared with y, and x
Difference is in 2 pixels, and y is differed in 2 pixels, then the horizontal line section is exactly line segment 3 to be detected, this step terminates, and enters
Next step；If can't detect the horizontal line section of the condition of satisfaction, found in the way of situation d.
D, the top end coordinate of line segment 2 and remaining all unmarked left side endpoint for completed horizontal line section are sat
Mark is compared, if left side the extreme coordinates x and y of some horizontal line section, with the top end coordinate x of line segment 2 compared with y, and x
Difference is in 2 pixels, and y is differed in 2 pixels, then the horizontal line section is exactly line segment 3 to be detected, this step terminates, and enters
Next step；If can't detect the horizontal line section of the condition of satisfaction, the line segment 2, return step 431 are skipped) restart to seek
It looks for, until finding line segment 3 or having traversed all line segments.
434) according to the four of step 432) kinds of situations, line segment 4 is continually looked for.
A, the bottom extreme coordinates of line segment 3 and remaining all unmarked right side endpoint for completed horizontal line section are sat
Mark is compared, if right side the extreme coordinates x and y of some horizontal line section, with the bottom extreme coordinates x of line segment 3 compared with y, and x
Difference is in 2 pixels, and y is differed in 2 pixels, then the horizontal line section is exactly line segment 4 to be detected, this step terminates, and enters
Next step；If can't detect the horizontal line section of the condition of satisfaction, found in the way of situation b.
B, the top end coordinate of line segment 3 and remaining all unmarked left side endpoint for completed horizontal line section are sat
Mark is compared, if left side the extreme coordinates x and y of some horizontal line section, with the top end coordinate x of line segment 3 compared with y, and x
Difference is in 2 pixels, and y is differed in 2 pixels, then the horizontal line section is exactly line segment 4 to be detected, this step terminates, and enters
Next step；If can't detect the horizontal line section of the condition of satisfaction, the line segment 3, return step 431 are skipped) restart to seek
It looks for, until finding line segment 4 or having traversed all line segments.
C, the left side extreme coordinates of line segment 3 and remaining all unmarked bottom endpoint for completed vertical segment are sat
Mark is compared, if bottom the extreme coordinates x and y of some vertical segment, with the left side extreme coordinates x of line segment 3 compared with y, and x
Difference is in 2 pixels, and y is differed in 2 pixels, then the vertical segment is exactly line segment 4 to be detected, this step terminates, and enters
Next step；If can't detect the horizontal line section of the condition of satisfaction, found in the way of situation d.
D, the right side extreme coordinates of line segment 3 and remaining all unmarked top end for completed vertical segment are sat
Mark is compared, if top end the coordinate x and y of some vertical segment, with the right side extreme coordinates x of line segment 3 compared with y, and x
Difference is in 2 pixels, and y is differed in 2 pixels, then the vertical segment is exactly line segment 4 to be detected, this step terminates, and enters
Next step；If can't detect the horizontal line section of the condition of satisfaction, the line segment 3, return step 431 are skipped) restart to seek
It looks for, until finding line segment 4 or having traversed all line segments.
435) then line segment 1 to 4 is labeled as being completed, and identifies the mark in the logical node rectangle using KNN algorithm
Symbol, identifier can be A(telemetering), D(remote signalling) ,+(addition) ,-(subtracting each other), * (multiplication) ,/(being divided by), %(remainder), logic
With), | (logic or),>(being greater than),<(being less than), O(are exported) etc., and numbered to logical node one unique ID.
44) identification signal name, detailed process are as follows:
44a) character recognized is traversed, records all [characters.
44b) [character as starting point, finds y-coordinate using each and differed in 2 pixels therewith, x coordinate is greater than should [character
X coordinate, and x coordinate differs that the smallest character, and is to be completed by the character marking found.
44c) continue character late, find y-coordinate with [differ in 2 pixels, x coordinate is greater than step 44b) find
The x coordinate of character, and x coordinate differs that the smallest character, and is to be completed by the character marking found.Until having found
One] character, then the signal name is searched and is terminated.
44d) return step 44b), all signal names are all found.
The rectangle bottom edge midpoint of each logical node 44e) is calculated at a distance from each signal name top center, it will be away from
It associates from the smallest that combination, here it is logical node and its corresponding signal names.
Step 5: identification connecting line, and the logical node information at connecting line both ends is preserved.Due to forming square
The line segment of shape is all marked as being completed, and remaining line segment is all just connecting line, and the Origin And Destination of connecting line is all
Be only and a line segment intersection.Identification process is as follows:
51) line segment is taken out from the line segment of identification, is completed if the line segment is not marked with, by the line segment and remaining
Line segment carries out intersection detection.
52) when any one endpoint of the line segment of selection is equal with the coordinate of any one endpoint of another line segment,
Add one for the intersection counter of the selection line segment.
53) it loops through after terminating, if the counter of the selection line segment is equal to 0 or 1, by the line segment labeled as end
Line segment returns to step 51), and all end line sections are found.
54) the end line section that traversal intersection counter is 0, creates a connection line object, detects each endpoint and logic section
The intersection situation of point, if the coordinate of endpoint on the vertical segment of logical node, just saves the logic in connection line object
The information (logical node signal type and logical node name and logical node ID) of node.
55) the end line section that traversal counter is 1, detects the intersection situation of endpoint and remaining line segment, if having found one
Line segment and end line segment intersection, just by the line segment labeled as being completed, and by another endpoint of the line segment and remaining line segment into
Row intersection detection, as soon as until finding an end line section, in this way, a connecting line is constituted, it, will be all connected after traversal
Line segment is collectively labeled as being completed.
56) endpoint of connecting line and the intersection situation of logical node are detected, if the coordinate of endpoint hanging down in logical node
On straightway, just saved in connection line object the logical node information (logical node signal type and logical node name and
Logical node ID).The left side storage for connecting line object is input signal, and right side is output signal.Referring specifically to Fig. 4.
Step 6: traversal logical node finds output logical node, finds out the logical expression of the output logical node.
It is specific as follows specially by the way of recursive resolve:
61) logical node is traversed, output node is found；
62) according to the connection line object where output node, input signal operator logic corresponding with the output node is found out
Node；
63) recursive function is called to the operator logical node, and a pair will be added to include outside the return expression of the recursive function
Number, the expression formula as output node；
64) all connection line objects are traversed, all input signal logic sections corresponding with the operator logical node are found out
Point, and recursive function is called to these input signal logical nodes；If logical node is that signal node is then transferred to such as A or D
Step 65)；If the node is operator logical node, such as+or *, then return step 64)；
65) signal name of the logical node, such as YC70020 are returned；
66) add a pair of of bracket outside the expression formula for returning to each recursive function, as (YC70012+YC70321+
YC70003)；
67) these parenthesized expression formulas are connected using the operator of step 63), i.e. logic chart logical table to be expressed
Up to formula.
By taking Fig. 5 as an example, the process of solution logic expression formula is as follows:
A) traverse logical node, if certain logical node be output node, i.e., signal identifiers be O node, from connecting line pair
The node that output signal identifier is O, i.e. O1 node in Fig. 5 are found as in；
B) according to the connection line object where output node, find node corresponding to corresponding input signal, i.e. in Fig. 5, L1
The corresponding Luo Jijiedian &1 of input signal, recursion method is called to the node, and will be outside the return expression of the recursion method
Portion adds a pair of of bracket, the expression formula as output node O；
C) all connection line objects are traversed, all input signal logic sections corresponding with the operator logical node are found out
Point, and recursive function is called to these input signal logical nodes；
D) add a pair of of bracket outside the expression formula for returning to recursive function each in step c), i.e. , &1 connected L2, L3 in Fig. 5
With L4 and corresponding input signal | the expression formula of 1, &2 and &3, (D1 | D2), (D3&D4) and (D5&D6), then by these band brackets
Expression formula using the mathematical operator be connected, and as the expression formula of the mathematical operator node return, that is, use operator
Be connected ((D1 | D2) &(D3&D4) &(D5&D6)), the expression formula as output node.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, several improvement and deformations can also be made, these improvement and deformations
Also it should be regarded as protection scope of the present invention.
Claims (6)
1. a kind of recognition methods of graphics logic configuration, which comprises the following steps:
1) rendering logic figure, the logic chart drawn are made of logical node and connecting line, pass through connecting line between logical node
Connection；The logical node is a closed rectangle, signal type identifier is marked in closed rectangle inside, in rectangle
Underface marks signal name；
2) logic chart drawn is taken pictures or is scanned, generate an image file；
3) median filtering and binary conversion treatment are carried out to image file generated；
4) logical node in image file, and the information preservation for each logical node that will acquire, the logic section are identified
The information of point includes: the signal type identifier of logical node, signal name and logical node ID；
5) it identifies connecting line, and the logical node information at connecting line both ends is preserved；
6) logical node is traversed, output logical node is found, finds out the logical expression of the output logical node.
2. a kind of recognition methods of graphics logic configuration according to claim 1, which is characterized in that in the step 1),
The signal type includes: remote signalling, telemetering, output and operator, wherein and remote signalling identifier uses D, and telemetering identifier uses A,
Output identification symbol uses O, and the identifier of operator uses usual mathematic sign；The signal name is surrounded using a pair of of bracket
String representation.
3. a kind of recognition methods of graphics logic configuration according to claim 1, which is characterized in that in the step 4),
Detailed process is as follows for logical node in identification image file:
41) pictorial symbolization is carried out to font used in logic chart using KNN algorithm；
42) Canny edge detection is carried out to binary image, then carries out statistical probability Hough transformation, identify all complete lines
Section；
43) line segment is traversed, identifies all rectangles；
44) using the identifier in KNN algorithm recognition logic node rectangle, and to logical node one unique ID number；
45) identification signal name；
46) the rectangle bottom edge midpoint of each logical node is calculated at a distance from each signal name top center, it will be apart from most
That small associates to combination, as logical node and its corresponding signal name.
4. a kind of recognition methods of graphics logic configuration according to claim 3, which is characterized in that the step 45) is known
Level signal name process is as follows:
It 44a) identifies all characters, the character recognized is traversed, all [characters are recorded；
44b) using it is each [character as starting point, find y-coordinate and differed in 2 pixels therewith, x coordinate be greater than should [character x coordinate,
And x coordinate differs that the smallest character, and is to be completed by the character marking found；
44c) continue character late, find y-coordinate with [differ in 2 pixels, x coordinate is greater than step 44b) character that finds
X coordinate, and x coordinate differs the smallest that character, and is to be completed by the character marking found；Until having found one
] character, then the signal name is searched and is terminated；
44d) return step 44b), all signal names are all found.
5. a kind of recognition methods of graphics logic configuration according to claim 1, which is characterized in that the step 5) connection
Line identification process is as follows:
51) line segment is taken out from the line segment of identification, is completed if the line segment is not marked with, by the line segment and remaining
Line segment carries out intersection detection；
52) it when any one endpoint of the line segment of selection is equal with the coordinate of any one endpoint of another line segment, will select
The intersection counter for the line segment selected adds one；
53) it loops through after terminating, if the counter of line segment is equal to 0 or 1, which is labeled as end line section；
54) the end line section that traversal intersection counter is 0, creates a connection line object, detects each endpoint and logical node
Intersect situation, if the coordinate of endpoint on the vertical segment of logical node, saves the logical node in connection line object
Information；
55) the end line section that traversal counter is 1, detects the intersection situation of endpoint and remaining line segment, if having found a line segment
With end line segment intersection, then the line segment is labeled as being completed, and another endpoint of the line segment and remaining line segment are subjected to phase
Detection is handed over, as soon as until finding an end line section, in this way, a connecting line is constituted, after traversal, by all connected line segments
It is collectively labeled as being completed；
56) detecting step 55) connecting line endpoint and logical node intersection situation, if the coordinate of endpoint is in logical node
Vertical segment on, then connection line object in save the logical node information.
6. a kind of recognition methods of graphics logic configuration according to claim 1, which is characterized in that the step 6) output
The logical expression solution procedure of logical node is as follows:
61) logical node is traversed, output node is found；
62) according to the connection line object where output node, input signal operator logic corresponding with the output node is found out
Node；
63) recursive function is called to the operator logical node, and a pair will be added to include outside the return expression of the recursive function
Number, the expression formula as output node；
64) all connection line objects are traversed, all input signal logic sections corresponding with the operator logical node are found out
Point, and recursive function is called to these input signal logical nodes；If logical node is signal node, it is transferred to step 65)；
If the node is operator logical node, return step 64)；
65) signal name of the logical node is returned；
66) add a pair of of bracket outside the expression formula for returning to each recursive function；
67) these parenthesized expression formulas are connected using the operator of step 63), i.e. logic chart logical table to be expressed
Up to formula.
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