CN109391252A - Control device for power semiconductor switch - Google Patents
Control device for power semiconductor switch Download PDFInfo
- Publication number
- CN109391252A CN109391252A CN201810898922.7A CN201810898922A CN109391252A CN 109391252 A CN109391252 A CN 109391252A CN 201810898922 A CN201810898922 A CN 201810898922A CN 109391252 A CN109391252 A CN 109391252A
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- control
- power semiconductor
- semiconductor switch
- control device
- pulse
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 74
- 238000012806 monitoring device Methods 0.000 claims abstract description 15
- 230000008054 signal transmission Effects 0.000 claims description 3
- 210000001367 artery Anatomy 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 210000003462 vein Anatomy 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/0812—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
- H03K17/08128—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit in composite switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
Landscapes
- Power Conversion In General (AREA)
- Electronic Switches (AREA)
Abstract
The present invention relates to the control devices for power semiconductor switch, the power semiconductor switch has the first and second power current connecting pins and control terminal, control device can receive the control signal with the control pulse being separated from each other in time, the control device includes-is arranged the first controller for electric consumption end for being electrically connected with the first power current connecting pin, the second controller for electric consumption end with setting for being electrically connected with control terminal, driving device, it is configured to generate driving voltage on second control device end according to the control signal for driving power semiconductor switch, monitoring device, it is configured to, when there are at least two control pulses next to each other, when the starting from corresponding control pulse until the corresponding first time period of the starting of immediately thereafter control pulse is controlled lower than first threshold and from accordingly The termination of pulse processed is until the corresponding second time period of the termination of immediately thereafter control pulse generates error signal when being lower than second threshold.
Description
Technical field
The present invention relates to the control devices for power semiconductor switch.
Background technique
A kind of control device for power semiconductor switch as known to 10 2,015 120 166 B3 of DE.Control device
With driving device, control signal that driving device is generated according to higher level's control mechanism, for driving power semiconductor switch
Driving voltage is generated on the control device end of power semiconductor switch.Higher level's control mechanism in order to transmission of control signals for example through
It is electrically connected by cable with control device.Control signal has the control pulse being separated from each other in time.It is dry for example, by EMC
The electrical connection that disturbing pulse can be coupled between higher level's control mechanism and control unit is disturbed, this can lead to power semiconductor switch
Mistake handover operation.
Summary of the invention
The object of the present invention is to provide a kind of control device for power semiconductor switch, which identifies logical
Cross the disturbing pulse in its received control signal.
The purpose realized by a kind of control device for power semiconductor switch, which has the
One power current connecting pin and the second power current connecting pin and control terminal, wherein control device is constructed to be permeable to receive tool
There is the control signal for the control pulse being separated from each other in time, which includes
- the first controller for electric consumption end and the second controller for electric consumption end, the first controller for electric consumption end setting for the first function
The electrical connection of rate current connection terminals, the second controller for electric consumption end are arranged for being electrically connected with control terminal,
Driving device, driving device are configured to, according to the control signal for driving power semiconductor switch in the second control
Driving voltage is generated on device end processed,
Monitoring device, monitoring device are configured to, there are at least two control pulses next to each other, when
From originating up to the corresponding first time period of the starting of immediately thereafter control pulse is lower than first for corresponding control pulse
Threshold value and terminating up to the corresponding second time period of the termination of immediately thereafter control pulse is low from corresponding control pulse
Error signal is generated when second threshold.
Advantageous structural scheme of the invention is obtained by following technical solution.
Confirm advantageously, first threshold and second threshold value having the same because at this time monitoring device have it is symmetrical
Respondent behavior.
Furthermore it confirms advantageously, first threshold and second threshold are less than or size is equal to the fortune of power semiconductor switch
The inverse of row and the switching frequency of setting, the inverse for the switching frequency being especially less than arranged for the operation of power semiconductor switch
95% because reliably identifying disturbing pulse at this time.
In this regard, it was demonstrated that advantageously, for power semiconductor switch operation and the switching frequency that is arranged corresponds to
The maximum switching frequency of the permission of power semiconductor switch.The present invention can be used for detecting the high switching frequency not allowed at this time.
Furthermore confirm there are at least three feelings for controlling pulse next to each other advantageously, monitoring device is configured to
Under condition, when the starting from corresponding control pulse up to the corresponding first time period of the starting of immediately thereafter control pulse is low
In first threshold and terminating when corresponding the second of the termination of immediately thereafter control pulse from corresponding control pulse
Between section be lower than second threshold when generate error signal.Therefore, monitoring device can in terms of identifying disturbing pulse targetedly structure
Make less sensitive.
Furthermore it confirms to generate when there are error signal and partly lead for disconnecting power advantageously, driving device is configured to
The driving voltage of body switch.Thus, it is possible to reliably protect power semiconductor switch.
Furthermore it confirms advantageously, there is power semiconductor circuits power semiconductor switch and control according to the present invention to fill
It sets, wherein first control device end is electrically connected with the first power current connecting pin of power semiconductor switch and the second control dress
End is set to be electrically connected with the control terminal of power semiconductor switch.
Furthermore it confirms advantageously, control assembly has control device according to the present invention and is connected to control device, uses
In higher level's control mechanism of signal transmission, wherein control mechanism is configured to be used to generate control signal and transmits control signal
To control device.
In this regard, it was demonstrated that advantageously, first power current at first control device end and power semiconductor switch
Connecting pin is electrically connected and second control device end is electrically connected with the control terminal of power semiconductor switch.
Detailed description of the invention
The embodiment of the present invention is illustrated below with reference to the following drawings.This is shown:
Fig. 1 shows a kind of control assembly, which has according to the present invention for power semiconductor switch
Control device is electrically connected to transmit higher level's control mechanism of signal and to have with control device with connecting with control device
Power semiconductor switch；And
Fig. 2 shows the signals generated in control assembly.
Specific embodiment
A kind of control assembly 6 is shown in FIG. 1, which opens with according to the present invention for power semiconductor
Close T control device 1, with connect with control device 1 so as to carry out higher level's control mechanism 5 of signal transmission and with and control
The power semiconductor switch T that device 1 processed is electrically connected.Control device 1 and the power semiconductor switch T being connected electrically are formed together
Power semiconductor circuits 4.
Power semiconductor switch T has the first power current connecting pin E and the second power current connecting pin C and control terminal
G.In this embodiment, apply voltage Ue and power semiconductor on the second power current connecting pin C of power semiconductor switch T
The second power current connecting pin E of switch T is electrically connected with electric loading L (such as electric motor).Power semiconductor switch T for example may be used
For the component part of half-bridge circuit.
Power semiconductor switch T is preferably with transistor, such as IGBT (insulated gate bipolar transistor) or MOSFET (metal oxygen
Compound semiconductor field effect transistor) form exist.In this embodiment, power semiconductor switch T is deposited in the form of IGBT
, wherein the first power current connecting pin E exists in the form of the emitter of IGBT, and the second power current connecting pin C is with IGBT
Collector form exist and control terminal G exist in the form of the grid of IGBT.
Control device 1 has the first controller for electric consumption end A1 and the second controller for electric consumption end A2, first controller for electric consumption
End setting is electrically connected for the first power current connecting pin E with power semiconductor switch T and the second controller for electric consumption end is set
It sets and is electrically connected for the control terminal G with power semiconductor switch T.
In power semiconductor circuits 4, the first power current of first control device end A1 and power semiconductor switch T connect
It connects end E electrical connection and second control device end A2 is electrically connected with the control terminal G of power semiconductor switch T.
Control device 1 also has driving device 2, and driving device is configured to, according to for driving power semiconductor switch T's
Control signal S generates driving voltage Ua on the A2 of second control device end.For this purpose, driving device 2 is according to by higher level's control mechanism 5
The control signal S of generation generates drive on the A2 of second control device end and in turn on the control terminal G of power semiconductor switch T
Dynamic voltage Ua.In this embodiment, driving device 2 generates the driving voltage Ua of 15V to connect power semiconductor switch T and production
The driving voltage Ua of raw -8V is to disconnect power semiconductor switch T.Power semiconductor switch T is according to the voltage value of driving voltage Ua
It switches on and off.
Control signal S has the control pulse being separated from each other in time, schematically illustrates wherein on the top Fig. 2
Control pulse P1 to P5.Second control pulse P2 is after the first control pulse P1.Third controls pulse P3 immediately the
Two control pulse P2.4th control pulse P4 is immediately after third control pulse P3.5th control pulse P5 immediately the 4th control
After pulse P4.The rising avris of each control pulse P1 to P5 indicates the starting B of each control pulse P1 to P5 and each control
The decline avris of pulse P1 to P5 processed indicates the termination E of each control pulse P1 to P5.In this embodiment, in each control arteries and veins
When rushing P1 to P5 and occupying logic high, power semiconductor switch T is connected, and occupy logic low in each control pulse P1 to P5
When level, power semiconductor switch T is disconnected.It may be noted that this can also generally be realized on the contrary completely.
From each starting B for controlling pulse P1 to P4 up to the starting B of control pulse P2 to P5 immediately after is passed through respectively
Cross first time period T1.E is terminated up to the termination E of control pulse P2 to P5 immediately after from each control pulse P1 to P4
Pass through second time period T2 respectively.Signal S is controlled to modulate preferably through pulse width.In this embodiment, control signal S is such
Pulse width-modulated, that is, first time period T1 is different and second time period T2 is constant.Alternatively, control letter
Number S can also such pulse modulated, that is, second time period T2 is different and first time period T1 is constant or when first
Between section T1 be different and second time period T2 be similarly different.
Control signal S is preferably generated by higher level's control mechanism 5 in the following manner, that is, is such as shown the middle and lower part Fig. 2 is exemplary
Out, the basis signal GS of the sinusoidal with base cycle time TG is compared by higher level's control mechanism and there is switching cycle
The switching signal SZ of time TA, the switching cycle time are less than base cycle time TG.The switching cycle time, TA was preferably so selected
It selects, that is, the integral multiple of switching cycle time TA is equivalent to base cycle time TG.Control pulse P1 is obtained in this embodiment extremely
The starting B of P5 is higher than the time point DS1 of basis signal GS as switching signal SZ, and the termination E for controlling pulse P1 to P5 makees
It is lower than the time point DS2 of basis signal GS for switching signal SZ.It is however noted that vice versa.Switching signal SZ can
There is zigzag fashion as in the embodiment, although any others signal shape is also possible.By changing switching letter
The amplitude of number SZ can make the width for controlling pulse change in the operation of power semiconductor switch T.
Switching frequency fa is obtained by fa=1/TA.Power semiconductor switch T is thus with the operation for power semiconductor switch T
And the switching frequency fa operation being arranged.For power semiconductor switch T operation and the inverse of switching frequency fa that is arranged cut
Change cycle time TA.
In the present invention, control device 1 has monitoring device 3, and monitoring device is configured to: tight each other there are at least two
In the case where the control pulse connect, in particular, for example two control pulses next to each other as in this embodiment, such as
P1 and P2, when the starting B from corresponding control pulse P1 or P2 originates B's up to immediately thereafter control pulse P2 or P3
Corresponding first time period T1 is lower than first threshold GW1, and from the termination E of corresponding control pulse P1 or P2 up to immediately thereafter
Control pulse P2 or P3 termination corresponding second time period T2 be lower than second threshold GW2 when, generate error signal F.In this regard,
It continuously detects in the first time period T1 controlled between pulse and second time period T2 next to each other and twice in succession
Error signal F is generated when lower than first threshold GW1 and second threshold GW2.
In this embodiment, from the period of the starting B of the first control pulse P1 starting B for controlling pulse P2 up to second
T1 specifically indicates have up to period T1 of the starting B of third control pulse P3 from the starting B of the second control pulse P2 with T1a
Body indicates that the period T1 for the starting B for controlling pulse P4 up to the 4th from the starting B of third control pulse P3 is specifically used with T1b
T1c is indicated and is specifically used from the period T1 of the starting B of the 4th control pulse P4 starting B for controlling pulse P5 up to the 5th
T1d is indicated.Furthermore in this embodiment, from first control pulse P1 terminate E until second control pulse P2 terminate E when
Between section T2 specifically indicated with T2a, from second control pulse P2 terminate E until third control pulse P3 terminate E period
T2 is specifically indicated with T2b, terminates E up to the period T2 tool of the termination E of the 4th control pulse P4 from third control pulse P3
Body is indicated with T2c and terminates E up to the period T2 of the termination E of the 5th control pulse P5 is specific from the 4th control pulse P4
It is indicated with T2d.
Therefore, in this embodiment, error signal F is generated when meeting the following conditions:
T1a < GW1 and T1b < GW1 and T2a < GW2 and T2b < GW2.
In normal operation, that is, when in controlling signal S there is no showing as controlling the disturbing pulse of pulse, proper
Locality has selected the condition in the case where first threshold GW1 and second threshold GW2 that will not all be met.Even if this is being controlled
It is also such when the pulse width of pulse changes.Thus avoid the mistake detection to the disturbing pulse being not present.In the first control
In the case where there is disturbing pulse between the control of pulse P1 processed and second pulse P2, all these conditions all meet and pass through monitoring
Device 3 generates error signal F.
First threshold GW1 and second threshold GW2 having the same can be worth.
First threshold GW1 and second threshold GW2 is preferably smaller than or size is equal to the operation of power semiconductor switch T and sets
The Ta=1/fa reciprocal of the switching frequency fa set, especially they be less than for power semiconductor switch T operation and cutting for being arranged
Change the 95% of the Ta=1/fa reciprocal of frequency fa, especially they are less than the operation for power semiconductor switch T and cutting for being arranged
Change the 80% of the Ta=1/fa reciprocal of frequency fa.
Monitoring device 3 also may be configured to, there are at least three control pulse P1, P2 and P3 next to each other the case where
Under, when the starting B from corresponding control pulse P1, P2 or P3 is up to the starting B of immediately thereafter control pulse P2, P3 or P4
Corresponding first time period T1 lower than first threshold GW1 and from the termination E of corresponding control pulse P1, P2 or P3 up to immediately in
Thereafter the corresponding second time period T2 of the termination E of control pulse P2, P3 or P4 generate error signal when being lower than second threshold GW2
F.Monitoring device 3 be configured at this time it is less sensitive because single disturbing pulse is without result in generating error signal F.
Driving device 2 is preferably configured as, and the drive for disconnecting power semiconductor switch T is generated when there are error signal F
Dynamic voltage Ua.Power semiconductor switch T is protected by disconnecting power semiconductor switch T.For this purpose, monitoring device 3 is by error signal F
It is transferred to driving device 2.
It should be noted that being equivalent to power half in the switching frequency fa that the operation for power semiconductor switch T is arranged
When the maximum switching frequency famax for the permission of conductor switch T for example provided in data page, the present invention can be additionally utilized for visiting
Survey the high switching frequency fa not allowed.If switching frequency fa high must be unacceptable for higher level's control mechanism 5, this is monitored
Device 3 identifies and generates error signal F.
Claims (10)
1. being used for the control device of power semiconductor switch (T), the power semiconductor switch is connected with the first power current
Hold (E) and the second power current connecting pin (C) and control terminal (G), wherein the control device (1) is constructed to be permeable to receive
Control signal (S) with the control pulse (P1-P5) being separated from each other in time, the control device include:
- the first controller for electric consumption end (A1) and the second controller for electric consumption end (A2), the setting of first controller for electric consumption end are used for
Be electrically connected with first power current connecting pin (E), second controller for electric consumption end setting for the control terminal (G)
Electrical connection,
Driving device (2), the driving device are configured to, according to for driving the control of the power semiconductor switch (T) to believe
Number (S) generates driving voltage (Ua) on the second control device end (A2),
Monitoring device (3), the monitoring device are configured to, there are at least two control pulses (P1, P2) next to each other
In the case of, when from accordingly control pulse (P1, P2) starting (B) up to immediately thereafter control pulse (P2, P3)
Begin (B) corresponding first time period (T1) lower than first threshold (GW1) and from the termination (E) of corresponding control pulse (P1, P2)
Until the corresponding second time period (T2) of the termination (E) of immediately thereafter control pulse (P2, P3) is lower than second threshold (GW2)
When generate error signal (F).
2. control device according to claim 1, which is characterized in that the first threshold (GW1) and the second threshold
(GW2) value having the same.
3. control device according to any one of the preceding claims, which is characterized in that the first threshold (GW1) and institute
State the switching frequency that second threshold (GW2) is less than or size is equal to the operation of the power semiconductor switch (T) and is arranged
(fa) inverse.
4. according to control device described in preceding claims 3, which is characterized in that the first threshold (GW1) and described second
Reciprocal 95% for the switching frequency (fa) that threshold value (GW2) is arranged less than the operation for the power semiconductor switch (T).
5. control device according to claim 3, which is characterized in that for the power semiconductor switch (T) operation and
Maximum switching frequency (famax) of the switching frequency (fa) of setting corresponding to the permission of the power semiconductor switch (T).
6. control device according to claim 1 or 2, which is characterized in that the monitoring device (3) is configured to: existing
In the case where at least three control pulses (P1, P2, P3) next to each other, when from control pulse (P1, P2, P3) accordingly
Begin (B) until the corresponding first time period (T1) of the starting (B) of immediately thereafter control pulse (P2, P3, P4) is lower than first
Threshold value (GW1) and from the termination (E) of corresponding control pulse (P1, P2, P3) up to immediately thereafter control pulse (P2, P3,
P4 the corresponding second time period (T2) of termination (E)) generates error signal (F) when being lower than second threshold (GW2).
7. control device according to claim 1 or 2, which is characterized in that the driving device (2) is configured to, and exists
The driving voltage for disconnecting the power semiconductor switch (T) is generated when error signal (F).
8. power semiconductor circuits, with power semiconductor switch (T) and according to any one of claim 1 to 7
Control device (1), wherein the first power current of the first control device end (A1) and the power semiconductor switch (T)
Connecting pin (E) is electrically connected and the second control device end (A2) and the control terminal (G) of the power semiconductor switch (T) are electrically connected
It connects.
9. control assembly, with control device according to any one of claim 1 to 7 and for signal transmission and institute
State higher level's control mechanism (5) of control device (1) connection, wherein the control mechanism (5) is configured to for generating control signal
(S) and by the control signal (S) it is transferred to the control device (1).
10. control assembly according to claim 9, the first control device end (A1) and power semiconductor switch (T)
The first power current connecting pin (E) electrical connection and the second control device end (A2) and power semiconductor switch (T) control
End (G) electrical connection processed.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102017118467.8 | 2017-08-14 | ||
| DE102017118467.8A DE102017118467B4 (en) | 2017-08-14 | 2017-08-14 | Control device for a power semiconductor switch |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109391252A true CN109391252A (en) | 2019-02-26 |
| CN109391252B CN109391252B (en) | 2024-01-05 |
Family
ID=65084367
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810898922.7A Active CN109391252B (en) | 2017-08-14 | 2018-08-08 | Control device for power semiconductor switch |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109391252B (en) |
| DE (1) | DE102017118467B4 (en) |
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| US20100176783A1 (en) * | 2007-06-19 | 2010-07-15 | Masaki Tagome | Switching device drive circuit |
| CN101847932A (en) * | 2009-02-05 | 2010-09-29 | 电力集成公司 | Be used for implementing not have the method and apparatus of regulating park mode at power inverter |
| CN102354958A (en) * | 2011-10-12 | 2012-02-15 | 北京航空航天大学 | Device and method for protecting power switching tube of inverter through software and hardware combination |
| CN102447402A (en) * | 2010-10-13 | 2012-05-09 | 电力集成公司 | Controller with punctuated switching control circuit |
| CN103107799A (en) * | 2013-01-15 | 2013-05-15 | 深圳市明微电子股份有限公司 | Power tube driving device with drive pulse regulating function |
| DE102015120166B3 (en) * | 2015-11-20 | 2016-11-17 | Semikron Elektronik Gmbh & Co. Kg | Control device for a power semiconductor switch |
| US20160359410A1 (en) * | 2015-06-04 | 2016-12-08 | Rohm Co., Ltd. | Digital control power circuit, control circuit thereof, control method, and electronic device using the same |
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| JP4682763B2 (en) * | 2005-09-14 | 2011-05-11 | 富士電機システムズ株式会社 | DC / DC converter |
-
2017
- 2017-08-14 DE DE102017118467.8A patent/DE102017118467B4/en active Active
-
2018
- 2018-08-08 CN CN201810898922.7A patent/CN109391252B/en active Active
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|---|---|---|---|---|
| US20100176783A1 (en) * | 2007-06-19 | 2010-07-15 | Masaki Tagome | Switching device drive circuit |
| CN101847932A (en) * | 2009-02-05 | 2010-09-29 | 电力集成公司 | Be used for implementing not have the method and apparatus of regulating park mode at power inverter |
| CN102447402A (en) * | 2010-10-13 | 2012-05-09 | 电力集成公司 | Controller with punctuated switching control circuit |
| CN102354958A (en) * | 2011-10-12 | 2012-02-15 | 北京航空航天大学 | Device and method for protecting power switching tube of inverter through software and hardware combination |
| CN103107799A (en) * | 2013-01-15 | 2013-05-15 | 深圳市明微电子股份有限公司 | Power tube driving device with drive pulse regulating function |
| US20160359410A1 (en) * | 2015-06-04 | 2016-12-08 | Rohm Co., Ltd. | Digital control power circuit, control circuit thereof, control method, and electronic device using the same |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN109391252B (en) | 2024-01-05 |
| DE102017118467B4 (en) | 2019-05-02 |
| DE102017118467A1 (en) | 2019-02-14 |
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