CN109391125B

CN109391125B - Power switch system and method for judging whether complementary switch is in soft switch or hard switch state

Info

Publication number: CN109391125B
Application number: CN201710652813.2A
Authority: CN
Inventors: 张永; 胡晓磊
Original assignee: Fonrich Shanghai New Energy Technology Co ltd
Current assignee: Fonrich Shanghai New Energy Technology Co ltd
Priority date: 2017-08-02
Filing date: 2017-08-02
Publication date: 2020-10-27
Anticipated expiration: 2037-08-02
Also published as: CN109391125A

Abstract

The invention relates to a power switch system and a method for judging whether a complementary switch is in a soft switch state or a hard switch state. A first switch and a second switch are connected in series between a first reference node and a second reference node, the first reference node and the second reference node have different potentials, and the complementary first switch and the second switch are driven to be alternately switched on, wherein when one is switched on, the other is switched off and cannot be switched on simultaneously; setting a dead time between an on period of the first switch and an on period of the second switch; detecting a potential commutation time node at an interconnection node of the first switch and the second switch; the commutation time node is characterized to be in a soft switching state before the dead time ending moment in each switching period; the commutation time node is characterized as being in a hard switching state later than the end of the dead time in each switching cycle.

Description

Power switch system and method for judging whether complementary switch is in soft switch or hard switch state

Technical Field

The invention mainly relates to the field of driving of power switches, in particular to a method for accurately discriminating whether a switch is in a hard switch state or a soft switch state in a scheme for driving the power switch.

Background

The switching transistor is a transistor as a switching device, and mainly includes a bipolar transistor, a metal-oxide field effect transistor, an insulated gate bipolar transistor, and the like. When designing a switching power supply, the loss of a switching tube is an important index. The efficiency and the power density of the system can be improved by reducing the loss, and the size of the heat dissipation device can be reduced, so that the switching power supply is miniaturized, and the service life of the switching power supply is prolonged. The switching tube loss is generally divided into three parts, namely turn-on loss, turn-off loss and turn-on loss. The conduction loss comprises two parts of conduction loss in energy transfer and conduction loss of follow current. The losses generated by different switching technologies vary. Hard switching means that the switch is turned on and off when the voltage and current across the switching tube are not reduced to zero, so that large turn-on loss and turn-off loss are generated. The soft switches are divided into zero voltage switches ZVS and zero current switches ZCS. ZVS means that the voltage at two ends of the switching tube is reduced to zero before the switching tube is switched on, and the switching loss of ZVS can be reduced to zero basically. ZCS means that before the switching tube is turned off, the current of the switching tube is made to be zero, and the turn-off loss of ZCS can be basically reduced to zero.

In the case of the full-bridge synchronous rectifier circuit, ZVS is used to reduce the turn-on loss with respect to the hard switching, but the turn-on loss of the free-wheeling current is also present. Furthermore, current topology parameters such as leakage inductance also affect the soft switching performance of ZVS. Therefore, the use of a single hard switching technique or a single soft switching technique is not an optimal control method, and the characteristics of the two techniques can be fully utilized to realize optimal control by intelligently switching between the soft switching and the hard switching according to certain conditions. The traditional analog control method cannot realize automatic switching between a soft switch and a hard switch, and with the development of MCU (microprogrammed control Unit) technologies in recent years, the control part of a switching power supply gradually develops towards digitization. One advantage of digital control is its flexibility and digitization of the compensation network, complex drive waveform generation, complex fault diagnosis strategy functions, etc. are all difficult to implement with analog control, so digitization has progressed faster.

To overcome the drawbacks of hard switching converters, a number of soft switching methods have been proposed. These soft switching methods can be divided into two broad categories. One is active soft switching technology, typically PWM zero voltage or zero current transition soft switching technology, which uses additional auxiliary active switch and L, C resonant elements to make the power tube complete commutation at zero voltage or zero current during the transition state; the essence of the soft switching circuit is that the real-time controllability of the voltage or current zero crossing point and the active switch of the L, C resonant circuit is utilized to realize the soft switching. However, the resonance energy here must be large enough to create a condition of zero voltage switching or zero current switching, and furthermore the active resonant circuit should operate under the control signal of the soft switch controller. In fact, the power consumption of the auxiliary circuit itself, and the complexity of the active device and the control also bring about an increase in cost and a reduction in reliability, so that the popularization and application of many soft switching technologies are greatly limited. The other is passive soft switch technology, it uses the change of main circuit power electronic tube PWM state to replace the auxiliary active switch controlled by given time sequence, only uses passive lossless component to try to form passive buffer soft switch circuit on the hard switch converter, because it does not use extra active switch and corresponding control, detection, driving circuit, it has lower cost, higher reliability, better cost performance, and it can obtain the effect close to active soft switch technology and it is increasingly paid attention.

At present, except for a special full-bridge passive soft switching converter controlled by phase-shift PWM, most of multi-tube converters using traditional pulse width modulation as a control method still have the defect that the passive soft switching technology is not practical. The phase-shift pulse width modulation control also has the defects of complex control circuit and different working states and electrical stresses of four power electronic devices. The main reasons for the above-mentioned drawbacks are these: most passive soft switching technologies are designed for single-ended non-isolated converters, and the circuit topology is not suitable for multi-tube isolated converters; the traditional multi-tube converter adopts the voltage source direct current to direct current conversion or direct current to alternating current conversion of a high-frequency transformer, an energy storage inductor is not arranged on one side of an input source, and a circuit and parameters thereof are completely different from those of a single-ended non-isolated converter; the multi-tube converter has the defects of complex circuit, serious mutual influence and limited working condition of the soft switch. Therefore, the literature reports and the related technology in the aspect are limited. According to the search, the following results are obtained: the most important technical development is a new technology (IEEE TRANSACTIONS ON POWER ELECTRONICS, vol.15, No.1, 2000(1)) proposed by Irvin division (UCI) of the university of california, usa, to implement passive soft switching ON all PWM isolated inverters using a circuit integration method. The technical key point is that the circuit characteristic and graph theory are applied, elements in the passive soft switching network are reasonably simplified by a circuit comprehensive method, a reasonable circuit topology is obtained, and a better passive soft switching effect can be obtained by using fewer elements. The technical defects are as follows: the inductance and capacitance elements used for energy exchange and transmission have larger values, which is not beneficial to the miniaturization of the circuit; the energy exchange and transmission loops are more and not simple, so that the buffer loops are greatly influenced mutually, the dependence on circuit parameters is large, the parameters of the soft switch element depend on circuit conditions, and the design is very complex; at least two additional inductors are needed, and the inductors are easy to generate larger voltage spikes and have larger loss than the capacitor.

Disclosure of Invention

In an alternative embodiment of the present invention, a method of determining whether a switch is in a soft switching state or a hard switching state is disclosed, a first switch and a second switch being connected in series between a first and a second node, wherein the method comprises: driving the complementary first switch and second switch to be alternately switched on; setting a dead time between an on period of the first switch and an on period of the second switch; detecting a potential commutation time node at an interconnection node of the first switch and the second switch; the commutation time node is characterized to be in a soft switching state before the dead time ending moment in each switching period; the commutation time node is characterized as being in a hard switching state later than the end of the dead time in each switching cycle.

The method described above, wherein: the voltage at the interconnection node of the first switch and the second switch is sampled by a voltage Divider, and the commutation time node is detected based on the sampled voltage.

The method described above, wherein: a BUCK converter BUCK is provided comprising a first switch and a second switch, an inductance being provided between the interconnection node NX1 and the voltage output node NO1 of the BUCK converter, the first and second switches being directly connected in series between a first node NI1, considered as a voltage input node, and a second node NI2, considered as a reference ground.

The method described above, wherein: a BOOST converter BOOST is provided comprising a first switch and a second switch, an inductance being provided between the interconnection node NX2 and the voltage input node NI1 of the BOOST converter, the first and second switches being connected directly in series between a first node NO1, considered to be a voltage output node, and a second node NO2, considered to be a ground reference.

The method described above, wherein: arranging a buck single arm of an H-bridge type buck-boost converter to comprise a first switch and a second switch; or a BOOST single arm of the H-bridge type BUCK-BOOST converter comprises a first switch and a second switch, namely a so-called BUCK-BOOST circuit, wherein the BUCK single arm is BUCK and the BOOST single arm is BOOST.

The method described above, wherein: an inductance is provided between the interconnection node and one of the third nodes: the first and second switches are driven to turn on alternately, and an alternating pulsating voltage which varies in a sine wave manner with respect to a predetermined reference potential is generated at the third node. The potential of the first node is generally higher than that of the second node, and the predetermined reference potential here may or may not be equivalent to that of the second node.

The method described above, wherein: a first switch and a resonant inductor are connected in series between the interconnection node and the first node; the soft switching state comprises: in the on-phase of the first switch in each switching period, the resonant inductor resonates with the parasitic capacitance of the second switch or the parallel capacitance of the second switch; the first switch operates in a zero current on and zero current off mode; the second switch operates in zero voltage on and zero voltage off modes.

The method described above, wherein: a first switch and a resonant inductor are connected in series between the interconnection node and the first node; the soft switching state comprises: in the on-phase of the second switch in each switching period, the resonant inductor resonates with the parasitic capacitance of the first switch or the parallel capacitance of the first switch; the first switch operates in a zero voltage on and zero voltage off mode; the second switch operates in zero current on and zero current off modes.

The method described above, wherein: a first switch and a resonant inductor are connected in series between the interconnection node and the first node; the soft switching state comprises: in the on-phase of the first switch in each switching period, the resonant inductor resonates with the parasitic capacitance of the second switch or with the parallel capacitance of the second switch, and the second switch works in a zero-voltage on and zero-voltage off mode; in the on-phase of the second switch in each switching period, the resonant inductor resonates with the parasitic capacitance of the first switch or with the parallel capacitance of the first switch, and the first switch operates in the zero-voltage on and zero-voltage off modes.

The method described above, wherein: the soft switching state comprises: at the turn-on time of each cycle of the first or second switch, current flows through the anti-parallel diode or parasitic reverse diode of the first or second switch, causing the voltage of the first or second switch to be reduced to zero, thereby providing a zero voltage turn-on mode for the first or second switch.

In a preferred alternative embodiment of the present invention, a power switching system capable of determining whether the power switching system is in a soft switching state or a hard switching state is disclosed, wherein the power switching system comprises: a first switch and a second switch connected in series between a first node and a second node; a voltage divider for sampling a voltage at an interconnection node of the first switch and the second switch; wherein the first switch and the second switch which are alternately turned on are complementary switches, and a dead time is set between an on period of the first switch and an on period of the second switch; detecting a potential commutation time node at the interconnection node according to the sampled voltage; the commutation time node is characterized to be in a soft switching state before the dead time ending moment in each switching period; the commutation time node is characterized as being in a hard switching state later than the end of the dead time in each switching cycle.

The power switch system described above, wherein: a buck converter is provided including the first switch and the second switch, an inductance being provided between the interconnection node and a voltage output node of the buck converter.

The power switch system described above, wherein: a boost converter is provided comprising the first switch and the second switch, an inductance being provided between the interconnection node and a voltage input node of the boost converter.

The power switch system described above, wherein: the buck single arm of the H-bridge buck-boost converter comprises a first switch and a second switch; or the boosting single arm of the H-bridge type buck-boost converter comprises a first switch and a second switch.

The power switch system described above, wherein: an inductance is provided between the interconnection node and one of the third nodes: the first and second switches are driven to turn on alternately, and an alternating pulsating voltage which varies in a sine wave manner with respect to a predetermined reference potential is generated at the third node. The potential of the first node is generally higher than that of the second node, and the predetermined reference potential here may or may not be equivalent to that of the second node.

The power switch system described above, wherein: a first switch and a resonant inductor are connected in series between the interconnection node and the first node; the soft switching state comprises: in the on-phase of the first switch in each switching period, the resonant inductor resonates with the parasitic capacitance of the second switch or the parallel capacitance of the second switch; the first switch operates in a zero current on and zero current off mode; the second switch operates in zero voltage on and zero voltage off modes.

The power switch system described above, wherein: a first switch and a resonant inductor are connected in series between the interconnection node and the first node; the soft switching states include: in the on-phase of the second switch in each switching period, the resonant inductor resonates with the parasitic capacitance of the first switch or the parallel capacitance of the first switch; the first switch operates in a zero voltage on and zero voltage off mode; the second switch operates in zero current on and zero current off modes.

The power switch system described above, wherein: a first switch and a resonant inductor are connected in series between the interconnection node and the first node; the soft switching states include: in the on-phase of the first switch in each switching period, the resonant inductor resonates with the parasitic capacitance of the second switch or with the parallel capacitance of the second switch, and the second switch operates in a zero-voltage on and zero-voltage off mode; in the on-phase of the second switch in each switching period, the resonant inductor resonates with the parasitic capacitance of the first switch or with the parallel capacitance of the first switch, and the first switch operates in the zero-voltage on and zero-voltage off modes.

Drawings

To make the above objects, features and advantages more comprehensible, embodiments accompanied with figures are described in detail below, and features and advantages of the present invention will become apparent upon reading the following detailed description and upon reference to the following figures.

Fig. 1 is a schematic diagram of waveforms for comparing a soft switching mode and a hard switching mode integrated together.

Fig. 2 is a schematic diagram of voltage and current waveforms for a switch with a power switch tube turned on and off.

Fig. 3 is a schematic diagram of the switching losses generated by the power switching tube in the zero current on and off modes.

Fig. 4 is a schematic diagram of the switching losses generated by the power switching tube in the zero voltage on and off modes.

Fig. 5 is an exemplary schematic diagram of a circuit topology with a boost single arm and a buck single arm.

Fig. 6 is a schematic diagram illustrating that soft switching and hard switching can be applied in both dc and ac systems.

Detailed Description

The technical solutions of the present invention will be clearly and completely described below with reference to various embodiments, but the described embodiments are only used for describing and illustrating the present invention and not for describing all embodiments, and the solutions obtained by those skilled in the art without making creative efforts belong to the protection scope of the present invention.

In a power switching system, a power supply usually employs a power semiconductor device as a switching element, and the duty ratio of the switching element is controlled by periodically turning on and off the switch to adjust an output voltage. The switch power supply mainly comprises an input circuit, a conversion circuit, an output circuit, a control unit and the like. The power conversion is a core part and mainly comprises a switching circuit, and a transformer is applied to some occasions. In order to meet the requirement of high power density, the converter needs to work in a high-frequency state, the switching transistor needs to adopt a transistor arm with high switching speed and short on and off time, and a typical power switch comprises a plurality of power transistors, power field effect transistors, insulated bipolar transistors and the like. The control method is divided into various methods such as pulse width modulation, pulse frequency modulation, pulse width modulation and frequency modulation hybrid modulation, and the most common method is the pulse width modulation method.

Referring to fig. 1, the DC-DC PWM power conversion technology developed and applied from the early stage in the industry is a typical hard switching technology. In order to make the switching power supply operate efficiently even in a high-frequency state, the power electronics and power supply technology at home and abroad is continuously researching and developing a high-frequency soft switching technology. Soft switching and hard switching waveforms are compared as shown.

Referring to fig. 1, the power switch tube is in a state from ON to OFF: the current I1 flowing through the switch drops to zero and the potential U1 applied across the switch rises from zero, whereby the current I1 and the potential U1 have little or very short crossover time during turn-off to avoid power switching losses and are one type of soft switching.

Referring to fig. 1, the power switch tube is turned from OFF to ON state: the current I2 flowing through the switch rises from zero and the potential U2 applied across the switch drops to zero, whereby the current I2 and the potential U2 have little or very short crossover time during turn-on to avoid power switching losses and are one type of soft switching.

Referring to fig. 1, the power switch tube is in a state from ON to OFF: the current I3 flowing through the switch drops to zero and the potential U3 applied across the switch rises from zero, whereby the current I3 and the potential U3 have a crossover point or a crossover time during turn-off that is not negligible resulting in power switching losses and is one of the hard switches.

Referring to fig. 1, the power switch tube is turned from OFF to ON state: the current I4 flowing through the switch rises from zero and the potential U4 applied across the switch drops to zero, whereby the current I4 and the potential U4 have a crossover point or a crossover time during the turn-on process that is not negligible, resulting in power switching losses and being one of the hard switches.

Referring to fig. 1, it can be seen that the soft switch is characterized by the power devices, mainly the power switches, turning on or off under zero voltage condition and turning off or on under zero current condition. Compared with a hard switch, the power device of the soft switch works under the conditions of zero voltage and zero current, and the switching loss of the power device is small. At the same time, du/dt and di/dt are greatly reduced, so that it can eliminate correspondent electromagnetic interference and radio frequency interference, and can raise reliability of converter. At the same time, high frequency must be realized in order to reduce the size and weight of the transducer. To increase the switching frequency and at the same time the conversion efficiency of the converter, the switching losses have to be reduced. The approach to reduce the switching loss is to implement soft switching of the switching tube, so the basic soft switching technology and the expanded topology of the soft switching technology have become an important research direction of the switching conversion technology. The operating characteristics of soft and hard switching are compared and soft switching techniques are elaborated.

Referring to fig. 2, in order to clearly understand the advantages of soft switching, it is necessary to first understand the operating characteristics of conventional hard switching and the loss characteristics of the power switching tube. Fig. 2 shows the waveforms of the voltage VD and the current ID when the switching tube is driven to have an on-event and an off-event, so-called switching. Most of the Switching tubes adopt bipolar transistors or field effect transistors or bipolar insulated gate transistors or thyristors and the like based on semiconductor materials, junction capacitors, various parasitic diodes, on-state resistors RDSON and the like exist in the physical structure of the semiconductor power switch, and the semiconductor power switch is not an ideal Switching device, so that when the Switching tube works, the Switching-on Loss and the Switching-off Loss are generated and are called as Switching Loss (Switching Loss). It is well known in the industry that the higher the switching frequency, the greater the total switching losses, and the lower the efficiency of the converter. The presence of switching losses limits the increase in the switching frequency of the converter, thereby limiting the miniaturization and weight reduction of the converter.

Referring to fig. 2, assuming that a certain power switch starts to turn on from time t1 and the power switch is not fully turned on until time t2, the middle total delay is a period of t1-t 2: meaning that the period t1-t2 during which the voltage VD across the power switch drops from an off-state value to zero crosses the period t1-t2 during which the current ID flowing through the power switch rises from a zero value to an ON-state value, the conduction loss of the power switch being the power consumption PLOSS-ON caused by the current and voltage present during this period itself. Assuming that a power switch starts to turn off from time t3, the power switch is not driven to turn off completely until time t4, the middle total delay is the period of t3-t 4: the period t3-t4 during which the voltage VD across the power switch rises from almost zero to an OFF-state value crosses the period t3-t4 during which the current ID flowing through the power switch falls from an on-state value to a zero value, the turn-OFF loss of the power switch being the power consumption PLOSS-OFF resulting from the current and voltage present during this period itself. The switching device driven by the PWM signal in the conventional PWM converter operates in the hard-switching state shown in fig. 2, and several defects of the hard-switching operation prevent the increase of the operating frequency of the switching device, and one of the main problems is: the turn-on and turn-off losses are large, and the current rise and the voltage drop of the switching device are simultaneously carried out to generate cross overlapping when the switching device is turned on; the voltage rise and current fall occur simultaneously at turn-off to create a crossover overlap. It is necessarily the case that the overlap of the voltage and current waveforms causes the turn-on and turn-off losses of the device to increase with increasing switching frequency. The second major problem is that: the problem of inductive turn-off is that inductive elements such as parasitic inductance or physical inductance of lead inductance and transformer leakage inductance exist in the circuit, when a switching device is turned off, large electromagnetic interference is generated due to the large change of current in unit time passing through the inductive elements, and the generated peak voltage is applied to two ends of the switching device, so that voltage breakdown is easily caused. There are three major problems: capacitive turn-on problems, when the switching device is turned on at very high voltages, the energy stored in the switching device junction capacitance will be totally dissipated within the switching device causing excessive thermal damage to the switching device. The fourth major problem is: the diode reverse recovery problem is that when the diode is switched from on to off, a reverse recovery period exists, and during the period, the diode is still in an on state, if a switching device connected with the diode in series is immediately switched on, a direct current power supply is easily subjected to instantaneous short circuit, a large impact current is generated, the switching device and the diode are rapidly increased in consumption if the direct current power supply is light, and the switching device and the diode are damaged if the direct current power supply is heavy.

As shown in fig. 2, the above problems seriously hinder the improvement of the operating frequency of the power switch, and the soft switching research technology adopted in recent years provides an effective way to overcome the above defects. Unlike hard switching, the ideal soft turn-off process is one in which the current drops to zero and the voltage then slowly rises to an off-state value, with turn-off losses approximately equal to zero. The inductive turn-off problem is solved because the current has dropped to zero before the device is turned off. The ideal soft turn-on process is that the voltage is firstly reduced to zero, the current is slowly increased to an on-state value, the turn-on loss is approximate to zero, the voltage of the junction capacitor of the device is also zero, and the capacitive turn-on problem is solved. Meanwhile, when the switch is switched on, the reverse recovery process of the diode is already finished, so that the problem of recovery of the direction of the diode is not existed.

Referring to fig. 3, the switching of high and low levels of a drive signal coupled to the GATE or base of a switch to drive the switch, i.e., a GATE signal, is shown, as one way to compromise the reduction of switching losses, fig. 3 employs a zero current turn-on and turn-off technique: in the on-phase, there is some negligible small loss, and the course of the soft OFF-period t3-t4 is mainly that the current ID flowing through the power switch is first reduced to zero from the on-state value, and the voltage VD applied across the power switch is then slowly increased to the subsequent OFF-state value, so that the OFF-loss PLOSS-OFF is approximately equal to zero. The soft switching scheme does not operate simultaneously with the voltage rise and current fall when the switch is turned off and does not produce so-called crossover overlap.

Referring to fig. 4, the switching of high and low levels of a drive signal coupled to the GATE or base of a switch to drive the switch, i.e., a GATE signal, is shown, as one way to compromise the reduction of switching losses, fig. 4 employs a zero voltage turn-on and turn-off technique: there is a small loss that is almost negligible in part during the off-phase, and the soft ON-period t1-t2 is mainly performed when the voltage VD applied across the power switch first drops from the off-state value to zero and the current ID flowing through the power switch then rises from zero to the ON-state value, and the ON-loss PLOSS-ON is approximately equal to zero. The soft switching scheme does not operate simultaneously with the voltage drop and current rise when the switch is on and does not produce so-called crossover overlap.

Referring to fig. 4, in view of the defects of the so-called hard switching and the advantages of the soft switching, the characteristics of the soft switching and the strategy for implementing the soft switching are mainly as follows: based on the doubt that switching losses, including turn-on losses and turn-off losses, exist, the goal of using soft switching techniques is to reduce the turn-on losses and turn-off losses of voltage converters. While the complementary switch of the alternative embodiment of fig. 5 is used as an example for illustration, it should be noted that the voltage converter circuit or the voltage converter/converter or the power optimizer with the complementary switch is not limited to the illustrated example, and any topology with the complementary switch in the soft switching state or in the hard switching state can be detected by the method disclosed in the present application.

Referring to fig. 5, in order to explain the inventive spirit of the hard switching and soft switching schemes involved in the present application, an illustrative voltage converter for power conversion is provided, which includes: a first front side node NI1 and a second front side node NI2, and further a first back side node NO1 and a second back side node NO 2. Wherein a switch S1 and a switch S2 employing power transistors are connected in series between the first front side node NI1 and the second front side node NI2, wherein an inductive element L is coupled between an interconnection node NX1 to which both the switch S1 and the switch S2 are connected and the first back side node NO 1. The voltage converter is a BUCK circuit, i.e., switch S1 and switch S2 constitute a BUCK single-arm. In the BUCK circuit, the illustrated switches S3-S4 can be directly eliminated from the circuit topology, and the inductive element L of the BUCK circuit can be directly connected between the interconnection node NX1 and the first back-side node NO 1. But also a back side capacitance not shown in the figure may be connected between the first back side node NO1 and the second back side node NO2 or a front side capacitance not shown in the figure may be connected between the first front side node NI1 and the second front side node NI 2. The BUCK circuit of the power conversion can operate independently.

Referring to fig. 5, in order to explain the inventive spirit of the hard switching and soft switching schemes involved in the present application, an illustrative voltage converter for power conversion is provided, which includes: a first front side node NI1 and a second front side node NI2, and further a first back side node NO1 and a second back side node NO 2. Wherein a switch S3 and a switch S4 employing power transistors are connected in series between the first back side node NO1 and the second back side node NO2, wherein an inductance L is coupled between an interconnection node NX2 to which both the switch S3 and the switch S4 are connected and the first front side node NI 1. The voltage converter is a BOOST circuit, i.e. the switch S3 and the switch S4 form a BOOST single arm. In the BOOST circuit, the illustrated switches S1-S2 may be directly eliminated from the circuit topology, and the inductor L in the BOOST circuit may be directly connected between the interconnect node NX2 and the first front-side node NI 1. But also a back side capacitance not shown in the figure may be connected between the first back side node NO1 and the second back side node NO2 or a front side capacitance not shown in the figure may be connected between the first front side node NI1 and the second front side node NI 2. The BOOST circuit of the power conversion can operate independently.

Referring to fig. 5, an alternative voltage converter for power conversion is shown as an example: a first front side node NI1 and a second front side node NI2, and a first back side node NO1 and a second back side node NO 2. The switch S1 and the switch S2 using power transistors are connected in series between the first front side node NI1 and the second front side node NI2, the switch S3 and the switch S4 using power transistors are connected in series between the first back side node NO1 and the second back side node NO2, note that the switch S1 and the switch S2 are both connected to the interconnection node NX1, and the switch S3 and the switch S4 are both connected to the interconnection node NX2, and the inductor L is connected between the first interconnection node NX1 and the second interconnection node NX 2. Therefore, the BUCK single arm as the front stage BUCK and the BOOST single arm as the back stage BOOST are combined into a BUCK-BOOST circuit which has the power conversion capability of BUCK and BOOST at the same time, wherein the BUCK-BOOST circuit is in an H bridge type.

Referring to fig. 5, the first mode: the voltage modulation method for the power conversion circuit to work in the Step-down mode comprises the following steps: the processor outputs a pulse modulated signal to control the switch S1 and the switch S2 to turn on or off. The switches S1-S2 are alternately turned ON during each buck switching cycle, where the time S1-ON for switch S1 to turn ON and the time S1-OFF for switch S1 to turn OFF are set first for each buck switching cycle, and the time S2 is turned ON for switch S2-ON and the time S2 is turned OFF for switch S2-OFF for each buck switching cycle. The dead Time D-Time, in which both switches are off, between the switch S1 being on and the switch S2 being on, prevents both switches S1-S2 from being on at the same Time, which is the main operating mechanism of the voltage step-down circuit. The fact that the switch S4 is continuously turned on and the switch S3 is continuously turned off in the Buck mode means that the BOOST portion is forced to lose the BOOST function at this stage.

Referring to fig. 5, the second mode: the voltage modulation method for the power conversion circuit to work in the boost mode Step up comprises the following steps: the pulse modulated signal output by the processor controls the switch S3 and the switch S4 to be turned on or off. The switch S3 and the switch S4 are alternately turned ON during each boost switching cycle, where the time S3-ON when the switch S3 is turned ON and the time S3-OFF when the switch S3 is turned OFF during each boost switching cycle are set, and the time S4 is turned ON during each boost switching cycle is S4-ON and the time S4 is turned OFF is S4-OFF. Also, provision is made for a dead Time D-Time during the BOOST switching cycle between the switch S3 being on and the switch S4 being off, both switches being off, to avoid the switches S3-S4 being turned on directly at the same Time, which is the operating mechanism of the BOOST circuit, and for the second mode to define the switch S1 being continuously on and the switch S2 being continuously off, meaning that at this stage the Buck portion is forced to lose its Buck function.

Referring to fig. 5, a third mode: the voltage modulation method under the condition that the power conversion circuit works in a Buck-Boost mode comprises the following steps: the pulse modulated signal output by the processor controls the switch S1 and the switch S2 to be turned on or off. The switches S1-S2 are alternately turned ON during buck switching cycles, with the switch S1 being turned ON for S1-ON and the switch S1 being turned OFF for S1-OFF for each buck switching cycle, and with the switch S2 being turned ON for S2-ON and the second switch S2 being turned OFF for S22-OFF for each buck switching cycle. A dead Time D-Time is provided between the turning on of the prescribed switch S1 and the turning on of the switch S2, in which both switches are off. The pulse modulation signal output by the processor controls the on or off of the switch S3 and the switch S4 of the subsequent voltage converter in addition to the on or off of the switch S1 and the switch S2 of the preceding voltage converter, and alternately turns on the switch S3 and the switch S4 in each boost switching cycle of the subsequent voltage converter. The Time S3-ON of the switch S3 and the Time S3-OFF of the switch S3 are set in each boost switching cycle, the Time S4 is set to be S4-ON and the Time S4 is set to be S4-OFF in each boost switching cycle, and a dead Time D-Time is set between the turn-ON of the switch S3 and the turn-ON of the switch S4 in the boost switching cycle, wherein the dead Time D-Time is set when the two switches are turned OFF. The former-stage voltage converter with the switch S1 and the switch S2 in the third mode is a Buck step-down stage, meanwhile, the latter-stage voltage converter with the switch S3 and the switch S4 in the third mode is a Boost step-up stage, and the whole power conversion circuit is embodied as a Buck-Boost circuit. Note that the second front side node NI2 and the second back side node NO2 may have the same potential, e.g. a common reference ground. When the difference value between the voltage of the NO1-NO2 end of the power conversion circuit and the voltage of the NI1-NI2 end of the power conversion circuit exceeds a preset value, the power conversion circuit works in a voltage reduction or voltage increase working state. Or when the difference value between the voltage of the NO1-NO2 end of the power conversion circuit and the voltage of the NI1-NI2 end of the power conversion circuit is not higher than a preset value, the power conversion circuit works in a buck-boost working state. The power conversion circuit is a bidirectional DC/DC conversion circuit.

Referring to fig. 5, in an alternative embodiment, a method for determining whether a complementary switch is in a soft-switching state or a hard-switching state is disclosed, which mainly comprises: wherein a switch S1 and a switch S2 are connected in series between a so-called first node, e.g. set as the front side node NI1, and a so-called second node, e.g. set as the front side node NI2, the front side node NI1 generally has a higher potential than the front side node NI 2. The complementary switch S1 and switch S2 are driven to turn ON alternately, and a dead time is set between the ON period S1-ON of the switch S1 and the ON period S2-ON of the switch S2 in each switching cycle. Then, by detecting the time of the potential commutation at the interconnection node NX1 of the switch S1 and the switch S2, a voltage divider with divider resistors R1-R2 can be used to sample the potential change at the interconnection node NX1 in an alternative embodiment, such as the positive potential switching to the negative potential or the negative potential switching to the positive potential, where the positive and negative potentials are relative to the potential carried by the second front-side node NI 2. If the potential carried by the second front-side node NI2 is set to the reference ground potential, the change in potential at the interconnect node NX1 will either zero-cross from a positive potential above ground potential and switch to a negative potential below ground potential, or zero-cross from a negative potential below ground potential and switch to a positive potential above ground potential. Judging the soft switching state when the commutation Time point in each switching period is earlier than the end Time of the dead Time D-Time, wherein the end Time of the dead Time means that the switch S1 is turned off and the switch S2 is turned on; or the commutation Time point is later than the end Time of the dead Time D-Time in each switching period, namely the hard switching state is judged. The voltage divider samples the voltage at the interconnection node NX1 of the switches S1-S2, such as the intermediate node NS of the interconnection of the resistors R1-R2, and the resistors R1-R2 are connected in series between NX1 and the front side node NI2, and the commutation time point is detected based on the sampled voltage.

Referring to fig. 5, the above is purely exemplified by the step-down circuit, and in another alternative embodiment, if exemplified by the step-up circuit, the following is satisfied: a switch S4 and a switch S3 are connected in series between a so-called first node, e.g., set as the back-side node NO1, and a so-called second node, e.g., set as the back-side node NO2, and the potential of the front-side node NI1 is generally higher than the potential of the front-side node NI 2. The complementary switch S3 and switch S4 are driven to turn ON alternately, and a dead time is set between the ON period S4-ON of the switch S4 and the ON period S3-ON of the switch S3 in each switching cycle. Then, by detecting the time of the potential commutation at the interconnection node NX2 of the switch S4 and the switch S3, in an alternative embodiment, a voltage divider with divider resistors R1-R2 can be used to sample the potential change at the interconnection node NX2, such as the positive potential switching to the negative potential, or the negative potential switching to the positive potential, where the positive and negative potentials are relative to the potential carried by the second front-side node NI2 or the second back-side node NO 2. If the potential carried by the second front-side node NI2 or the second back-side node NO2 is set to the reference ground potential, the change in potential at the interconnect node NX2 will either cross over from a positive potential above ground potential and switch to a negative potential below ground potential, or cross over from a negative potential below ground potential and switch to a positive potential above ground potential. The judging method comprises the following steps: judging the soft switching state when the commutation Time point in each switching period is earlier than the end Time of the dead Time D-Time, wherein the end Time of the dead Time means that the switch S3 is turned off and the switch S4 is turned on; or the commutation Time point is later than the end Time of the dead Time D-Time in each switching period, namely the hard switching state is judged. The voltage divider samples the voltage at the interconnection node NX2 of the switches S4 and S3, such as the intermediate node NS where the resistors R1-R2 are interconnected, and the resistors R1-R2 are connected in series between NX2 and the back-side node NO2 and detect said commutation time point based on the sampled voltage.

Referring to fig. 6, in conjunction with the topology of fig. 5, the above description basically uses the topology of fig. 5 as a dc-dc bidirectional converter, but there are many occasions when it is necessary to generate ac pulsating voltage. For example, to obtain the commercial power ac power required by the load, in the inverter system, a two-stage or even multi-stage architecture, i.e., a front-stage dc converter, is required to complete the input and output voltage matching and electrical isolation of the inverter, and a rear-stage inverter is required to complete the inversion conversion of the dc power ac. Because the output voltage and current of the inverter at the rear stage are low-frequency alternating current, the instantaneous power of the inverter stage contains double-frequency pulsating quantity, and the low-frequency pulsating power enables the input current of the inverter stage to contain larger double-frequency output voltage frequency alternating current component, so that the output current of the direct current converter at the front stage has low-frequency pulsation, and the pulsating power is shared by the output filter inductor of the direct current converter and the intermediate bus capacitor. In view of the fact that low-frequency pulsating voltage exists on a direct-current bus of the inverter, it is very necessary to reduce the fluctuation of the bus voltage of the inverter, so as to achieve decoupling between the basically constant input power and the output fluctuating power of the inverter, and then the alternating-current pulsating voltage which is equal to the low-frequency pulsating voltage of the bus in magnitude and opposite in phase is actively generated and injected onto the direct-current bus, so that the low-frequency pulsating voltage of the bus can be compensated, and the low-frequency pulsating current caused by the low-frequency pulsating voltage can be counteracted.

Referring to fig. 6, it is also considered that the switches S1 to S2 of the power converter are driven to be turned on or off in terms of energy release, and such control is not unique but coexists in various methods. An alternative to a microprocessor is a logic device, processor or control device, state machine, controller, chip, software drive control, gate array, etc. that can send drive signals to generate pulse width modulated signals. In an alternative embodiment the switch S4 is controlled to be continuously on but the switch S3 is controlled to be continuously off, or the switches S3-S4 are directly dispensed with from the circuit topology such that the inductance is directly coupled between the interconnection node NX1 and the back side node NO1, but the switches S1 and S2 are treated as complementary switches and the high frequency is alternately switched on and one is switched off and the other is switched on. For example: the microprocessor drives the switches S1-S2, in a period of 0-T1, because a low-frequency pulsating voltage signal of a direct current bus is a positive pulsating voltage of a sine wave, the switch S1 is controlled to be turned off in the period, and the switch S2 is driven to generate a series of narrow pulses with equal amplitude and unequal width to replace a negative pulsating voltage VS2 of a pulsating waveform VS required in the period of 0-T1; correspondingly, the low-frequency pulsating voltage signal of the direct current bus in the period of T1-T2 is a negative pulsating voltage of a sinusoidal waveform, and the switch S2 is turned off and the switch S1 is driven to generate a series of narrow pulses with equal amplitude but unequal width to replace the positive pulsating voltage VS1 of the pulsating waveform VS required in the period of T1-T2. The switches S1 and S2 are driven according to the above embodiment to modulate a first ripple voltage changing in a positive direction according to a sine wave rule, where the first ripple voltage is a segment VS1 of a ripple waveform VS in a period from T1 to T2, the first ripple voltage is equal to and opposite to a negative half cycle of a low-frequency ripple voltage in magnitude and phase, and the first ripple voltage is fed back to a dc bus to cancel the negative half cycle of the low-frequency ripple current. According to the above embodiments, the switch S1 and the switch S2 modulate a second ripple voltage which changes in a negative direction according to a sine wave rule, the second ripple voltage is a segment VS2 of a ripple waveform VR in a period of 0-T1, the second ripple voltage is equal to and opposite to a positive half cycle of a low-frequency ripple voltage in magnitude and phase, and the second ripple voltage is fed back to a direct-current bus to offset the positive half cycle of the low-frequency ripple current. It can be known from fig. 6 that the sine wave in any one period 0-T2 of the complete compensation ripple waveform VS includes the second ripple voltage VS2 waveform and the first ripple voltage VS1 waveform which are continuously connected. Referring to fig. 6, the compensation ripple voltage VS generated by the power converter and having the same magnitude and the opposite phase to the low-frequency ripple voltage on the dc bus is injected onto the bus, which is equivalent to the power converter generating the compensation current having the same magnitude and the opposite phase to the low-frequency ripple current and injecting the compensation current onto the bus to offset the low-frequency ripple current. The original pulsating current of the polluted power supply is restrained, so that not only the battery is protected, but also potential pulsating currents of other electric equipment on the common power supply are restrained, the utilization rate of energy is improved, and abnormal protection actions of the system are avoided.

Referring to fig. 6, in conjunction with the topology of fig. 5, in an alternative embodiment, a method for determining whether a complementary switch is in a soft-switching state or a hard-switching state is disclosed, which mainly comprises: a switch S1 and a switch S2 are connected in series between the first node, e.g., set to the front side node NI1, and the so-called second node, e.g., set to the front side node NI2, the front side node NI1 generally having a higher potential than the front side node NI 2. Driving the complementary switches S1 and S2 alternately on, placing an inductance L between the interconnection node NX1 and a third reference node, e.g., NO1, may in alternative embodiments directly control the switch S4 to be continuously on but control the switch S3 to be continuously off, or directly override the switches S3-S4 so that the inductance L is directly coupled between the interconnection node NX1 and the back-side node NO 1. The scheme for generating the ac pulsating voltage VS at the back-side node NO1 mainly includes: the drive switches S1-S2 are alternately switched on to generate an alternating pulsating voltage VS at a third reference node, e.g. NO1, which varies in a sinusoidal manner with respect to a predetermined reference potential, and the third reference node, e.g. NO1, may generate VS with respect to a common reference potential of the second front-side node NI2 or the second rear-side node NO2, which in this embodiment may be a dc voltage value on a dc bus of the inverter. Turning off switch S1 as in fig. 6 and driving switch S2 to produce a series of narrow pulses of equal amplitude but unequal width in place of the negative-going pulsating voltage VS2 of the pulsating waveform VS required during the 0-T1 period; correspondingly, the switch S2 is turned off and the switch S1 is driven to generate a series of narrow pulses of equal amplitude but unequal width in place of the forward pulsating voltage VS1 of the pulsating waveform VS required during the period T1-T2. The switches S1 and S2 are driven according to the above embodiment to modulate a first ripple voltage that varies in a positive direction according to a sine wave rule with respect to the common reference potential of the second front-side node NI2 or the second back-side node NO2, and modulate a second ripple voltage that varies in a negative direction according to a sine wave rule with respect to the common reference potential of the second front-side node NI2 or the second back-side node NO2, the first ripple voltage is a segment VS1 of the ripple waveform VS in a period from T1 to T2, the second ripple voltage is a segment VS2 of the ripple waveform VR in a period from 0 to T1, and the ripple waveform VS is fed back to the dc bus to cancel the low-frequency ripple voltage. In summary, the power converter can modulate the first ripple voltage VS1 that changes in a positive direction according to a sine wave law with respect to the dc voltage on the dc BUS, and the first ripple voltage fed back to the dc BUS has the same magnitude and opposite phase to the negative half cycle of the low-frequency ripple voltage that causes the low-frequency ripple current. The second ripple voltage VS2 which changes in negative direction according to sine wave rule relative to the DC voltage of the DC BUS BUS is modulated by the power converter, and the second ripple voltage fed back to the DC BUS BUS is equal in magnitude and opposite in phase with the positive half cycle of the low-frequency ripple voltage causing the low-frequency ripple current.

Referring to fig. 5, it is prescribed in generating the alternating current pulsating voltage VS that a dead time is set between the ON period S1-ON of the switch S1 and the ON period S2-ON of the switch S2 in each switching cycle. Then, detecting the timing of the potential commutation at the interconnection node NX1 of the switches S1 and S2, a voltage divider with divider resistors R1-R2 can be used to sample the potential commutation at the interconnection node NX1, such as positive potential commutation to negative potential or negative potential commutation from negative potential to positive potential, where the positive or negative potential is relative to the potential carried by the second front-side node NI2 or the second back-side node NO 2. If the potential of the second front side node NI2 is set to the reference potential first, the potential change at the interconnect node NX1 will switch from a positive potential higher than the reference potential to a negative potential lower than the reference potential, or from a negative potential lower than the reference potential and to a positive potential higher than the reference potential. When the commutation Time point in each switching period is earlier than the end Time of the dead Time D-Time, the soft switching mode is determined, and the end Time of the dead Time means that the switch S1 is turned off and the switch S2 is turned on; or the commutation Time point is later than the end Time of the dead Time D-Time in each switching period, namely the hard switching mode is judged.

Referring to fig. 5, resonance technology Resonant is applied to soft switching technology, and its application eliminates the overlapping phenomenon of voltage and current during the switching process of the switching device in the converter operation, and reduces the switching loss of the switching device. In the various embodiments described above, there is no requirement to connect the switch S1 and the resonant inductance LA in series between the first front side node NI1 and the interconnect node NX1, i.e. the resonant inductance LA may be substantially eliminated from fig. 5. However, in a soft switching scheme using resonant technology, it is a preferred embodiment that the switch S1 and the resonant inductor LA are connected in series between the front-side node NI1 and the interconnection node NX 1. For example, a first terminal of the switch S1 is connected to the first front side node NI1 and a second terminal of the switch S1, which may be a drain and a source, is connected to the resonant inductor LA between the interconnect node NX 1. Taking the illustrated current switch/zero voltage switch one-cycle resonant Buck-Boost bidirectional converter as an example, LA is a resonant inductor and the switch S2 is connected in parallel with a resonant capacitor C2, note that the capacitor C2 may be a junction capacitor parasitic by a semiconductor material between a source and a drain of the power switch S2 itself, or an external capacitor C2 may be directly connected in parallel to two ends of the switch S2. In the forward operation mode of the bidirectional converter, the switches S1-S2 work complementarily, the resonant inductor LA and the resonant capacitor C2 resonate in the on phase of the switch S1, the switch S1 is turned on and off at zero current, and the switch S2 is turned on at zero voltage and turned off at zero voltage due to the resonant capacitor C2, in this embodiment, only the switch S2 is arranged in parallel with the resonant capacitor C2, but the capacitor C1 indicated across the switch S1 is discarded from the circuit topology.

Referring to fig. 5, in another alternative embodiment, LA is required to be a resonant inductor and the switch S1 is connected in parallel with a resonant capacitor C1, note that the capacitor C1 may be a junction capacitor parasitic by a semiconductor material between a source and a drain of the power switch S1 itself, or an external capacitor C1 may be directly connected in parallel across the switch S1. In the operation mode of the bidirectional converter, the switches S1-S2 are driven to work in a complementary switch mode, the resonant inductor LA and the resonant capacitor C1 resonate in the on phase of the switch S2, the switch S2 is switched on and off at zero current, and the switch S1 is switched on and off at zero voltage due to the resonant capacitor C2, in this embodiment, only the switch S1 is arranged in parallel with the resonant capacitor C1, but the capacitor C2 indicated across the switch S2 is discarded from the circuit topology.

Referring to fig. 5, in another alternative embodiment, LA is required to be a resonant inductor and the switch S1 is connected in parallel with a resonant capacitor C1 and the switch S2 is connected in parallel with a resonant capacitor C2. The capacitor C1 may be a junction capacitor parasitic to the semiconductor material between the source and the drain of the switch S1, or an external capacitor C1 may be connected in parallel across the switch S1. The capacitor C2 may be a junction capacitor parasitic to the semiconductor material between the source and the drain of the power switch S2, or an external capacitor C2 may be connected in parallel across the switch S2. In the operation mode of the bidirectional converter, the switches S1-S2 are driven to perform complementary switch operation, the resonant inductor LA resonates with the resonant capacitor C1 or C2 in the on stage of the switch S2 or S1, the switch S2 is turned on and off at zero voltage due to the resonant capacitor C2, the switch S1 is turned on and off at zero voltage due to the resonant capacitor C1, and the switches S1-S2 are all in zero voltage switch mode in this embodiment.

Referring to fig. 5, the present application discloses a power switching system and can determine whether a complementary switch of the power switching system is in a soft-switching state or a hard-switching state, comprising: first and second switches connected in series between the first and second nodes, e.g., S1-S2; further comprising a voltage divider for sampling the voltage at the interconnection node NX1 of the first and second switches, e.g. a voltage divider formed by voltage dividing resistors R1-R2 connected in series between the interconnection node NX1 and the second front side node NI 2; wherein the first switch and the second switch that are alternately turned on are complementary switches, and a dead Time D-Time is set between an on period of the first switch and an on period of the second switch; detecting a potential commutation time point at said interconnection node NX1 from a voltage sampled at a voltage divider intermediate node NS; this potential commutation is for example from a positive potential to a negative potential or vice versa, note that here the so-called positive or negative potential is relative to the potential carried by the second front side node NI 2. The commutation time point is earlier than the dead time ending time in each switching Cycle-time, and the commutation time point is characterized to be in a soft switching state; within each switching Cycle time, a commutation time point which is later than the end of the dead time is characteristic of a hard switching state. In fig. 5, the second front-side node NI2 and the second rear-side node NO2 are illustrated as having the same common reference potential. Determining whether the complementary switch is in the soft-switching state or the hard-switching state is significant for accurately controlling the power switching system, because hard-switching is easier to implement and drive and soft-switching has low switching loss despite the complex topology, and in practical applications, if trying to clamp the switching system into the hard-switching mode, it is necessary to determine whether the switch system is already in the hard-switching mode, otherwise, if trying to clamp the switching system into the soft-switching mode, it is necessary to determine whether the switch system is already in the soft-switching mode, which provides a basis for switching between hard-switching and soft-switching.

Referring to fig. 5, the resonant capacitors C1-C2 and resonant inductors can be eliminated from the topology, because the switches S1-S2 are physically power switches such as MOSFETs, which have reverse diodes parasitic between the source and the drain, and the parasitic reverse diodes can be replaced by additional reverse parallel diodes. For example, a first terminal of the switch S1 is connected to the front side node NI1, a second terminal of the switch S1 and a first terminal of the switch S2 are connected to a so-called interconnect node NX1, and a second terminal of the switch S2 is connected to the front side node NI 2. The first and second terminals may be a drain and a source here. An inverting diode inside or outside the switch is connected in parallel with the switch in such a manner that the anode is connected to the second terminal and the cathode is connected to the first terminal. The soft switching states in this embodiment include: the current flowing through the antiparallel diode or parasitic reverse diode of switches S1-S2 at the turn-on time of each cycle of switches S1-S2 directly results in the voltage of switches S1-S2 being reduced to zero, thereby providing a zero voltage turn-on mode for switches S1-S2.

Referring to fig. 5, in an optional but not required embodiment disclosed in the present application, in summary, the following driving modes exist for the topology: the complementary switches S1-S2 are alternately turned on, the complementary switches S3-S4 are alternately turned on, a dead time is set between turning on of the complementary switches S1-S2, and a dead time is also set between turning on of the complementary switches S3-S4. As is known to those skilled in the art, the dead time of the complementary switch/push-pull switch means that neither of the two complementary switches is turned on, and the prior art does not have a scheme for determining whether to switch hard or soft. The present application claims to determine the topological soft-hard switching of the voltage transitions during the dead time of the two sets of complementary switches S1-S2 and during the dead time of the complementary switches S3-S4. The embodiment is a method for detecting whether a switching power supply system, especially a power-optimized voltage conversion circuit, implements soft and hard switching in any one complete switching cycle, taking a certain switching cycle as an example: during the first phase, in which switch S1 remains on but switch S2 remains off: the switch S3 is turned on and the switch S4 is turned off, then the switch S3 is turned off and the switch S4 is turned on, and the turning off of the switch S3 and the turning on of the switch S4 continue until the second stage where the switch S1 is turned off and the switch S2 is turned on. The first stage is switched by turning on the switch S3 and turning off the switch S4, the state of turning on the switch S3 and turning off the switch S4 is kept for a short period of time, and then the first stage is switched by turning off the switch S3 and turning on the switch S4. It will be appreciated that the voltage conversion circuit transitions to performing the first phase after performing the second phase, the voltage conversion circuit cycling between the first phase and the second phase, and the complete switching cycle includes the first and second phases. The first stage power optimizer detects a potential commutation Time point TC1 at the interconnection node NX2 of the complementary switches S3-S4, this embodiment provides that a first dead Time D-Time1 is provided during the first stage of the switching cycle between the turn-on of the switch S3 and the turn-on of the switch S4, in which both switches are off, the commutation Time point TC1 is earlier than the end of the dead Time D-Time1 to determine that the voltage conversion circuit is in a soft-switching state, and conversely, the commutation Time point TC1 is later than the end of the dead Time D-Time1 to determine that the voltage conversion circuit is in a hard-switching state. The second stage power optimizer detects a potential commutation Time point TC2 at the interconnection node NX1 of the complementary switches S1-S2, which provides that a second dead Time D-Time2 is provided during the second stage of the switching cycle between the turn-on of the switch S1 and the turn-on of the switch S2, wherein the commutation Time point TC2 is earlier than the end of the dead Time D-Time2 to determine that the voltage conversion circuit is in the soft-switching state, and vice versa, otherwise the commutation Time point TC2 is later than the end of the dead Time D-Time2 to determine that the voltage conversion circuit is in the hard-switching state. It can be seen that the voltage converting circuit in this embodiment may be switched from the soft switch or the hard switch at the first commutation time point TC1 to the soft switch or the hard switch at the second commutation time point TC2, and has four states. In a preferred embodiment, since the duty cycle of the driving signals for driving the switches S1-S2 and the duty cycle of the driving signals for driving the switches S3-S4 are adjustable, the voltage converting circuit is preferably limited after detecting the actual soft or hard switching state of the voltage converting circuit: in each switching cycle, the turn-on time of the first-stage trim switch S4 is later than the first commutation time point TC1 of the first stage and the turn-on time of the second-stage trim switch S2 is later than the second commutation time point TC2 of the second stage. In this embodiment, the voltage converter is capable of achieving very high conversion efficiency and extremely low switching-on losses and/or switching-off power losses.

While the present invention has been described with reference to the preferred embodiments and illustrative embodiments, it is to be understood that the invention as described is not limited to the disclosed embodiments. Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above description. Therefore, the appended claims should be construed to cover all such variations and modifications as fall within the true spirit and scope of the invention. Any and all equivalent ranges and contents within the scope of the claims of the present application should be considered to be within the intent and scope of the present invention.

Claims

1. A method of determining whether a complementary switch is in a soft-switching state or a hard-switching state, wherein a first switch and a second switch are connected in series between a first node and a second node, the method comprising:

driving the complementary first switch and second switch to be alternately switched on;

setting a dead time between an on period of the first switch and an on period of the second switch;

detecting a potential commutation time point at an interconnection node of the first switch and the second switch;

judging the commutation time point to be in a soft switching state when the commutation time point is earlier than the end time of the dead time in each switching period;

and judging the commutation time point to be in a hard switching state after the dead time in each switching period.

2. The method of claim 1, wherein:

the voltage at the interconnection node of the first switch and the second switch is sampled by a voltage divider, and the commutation time point is detected based on the sampled voltage.

3. The method of claim 1, wherein:

a buck converter is provided comprising said first switch and said second switch.

4. The method of claim 1, wherein:

a boost converter is provided comprising the first switch and the second switch.

5. The method of claim 1, wherein:

arranging a buck single arm of an H-bridge type buck-boost converter to comprise the first switch and the second switch; or

A single boost arm of the H-bridge buck-boost converter is provided and comprises the first switch and the second switch.

6. The method of claim 1, wherein:

an inductance is provided between the interconnect node and a third reference node:

the first and second switches are driven to turn on alternately, and an alternating pulsating voltage varying in a sine wave manner with respect to a predetermined reference potential is generated at the third reference node.

7. The method of claim 1, wherein:

a first switch and a resonant inductor are connected in series between the interconnection node and the first node;

the soft switching state comprises:

in the on-phase of the first switch in each switching period, the resonant inductor resonates with the parasitic capacitance of the second switch or the parallel capacitance of the second switch;

the first switch operates in a zero current on and zero current off mode;

the second switch operates in zero voltage on and zero voltage off modes.

8. The method of claim 1, wherein:

the soft switching state comprises:

in the on-phase of the second switch in each switching period, the resonant inductor resonates with the parasitic capacitance of the first switch or the parallel capacitance of the first switch;

the first switch operates in a zero voltage on and zero voltage off mode;

the second switch operates in zero current on and zero current off modes.

9. The method of claim 1, wherein:

the soft switching state comprises:

in the on-phase of the first switch in each switching period, the resonant inductor resonates with a parasitic capacitor of the second switch or with a parallel capacitor of the second switch, and the second switch operates in a zero-voltage on and zero-voltage off mode;

in the on-phase of the second switch in each switching period, the resonant inductor resonates with the parasitic capacitance of the first switch or with the parallel capacitance of the first switch, and the first switch operates in the zero-voltage on and zero-voltage off modes.

10. The method of claim 1, wherein:

the soft switching state comprises:

at the turn-on time of each cycle of the first or second switch, current flows through the anti-parallel diode or parasitic reverse diode of the first or second switch, causing the voltage of the first or second switch to be reduced to zero, thereby providing a zero voltage turn-on mode for the first or second switch.

11. A power switching system capable of determining whether the power switching system is in a soft switching state or a hard switching state, comprising:

a first switch and a second switch connected in series between a first node and a second node;

a voltage divider for sampling a voltage at an interconnection node of the first switch and the second switch;

wherein the first switch and the second switch that are alternately turned on are complementary switches, and a dead time is set between an on period of the first switch and an on period of the second switch;

detecting a potential commutation time point at the interconnection node according to the sampled voltage;

the commutation time point is earlier than the dead time ending time in each switching period, and the commutation time point is characterized to be in a soft switching state;

within each switching cycle, a commutation time point later than the end of the dead time indicates a hard switching state.