CN109390411A - A kind of lamination active layer thin film transistor (TFT) and preparation method thereof - Google Patents
A kind of lamination active layer thin film transistor (TFT) and preparation method thereof Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims abstract description 38
- 238000003475 lamination Methods 0.000 title claims abstract description 35
- 238000002360 preparation method Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 42
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052593 corundum Inorganic materials 0.000 claims abstract description 34
- 229910001845 yogo sapphire Inorganic materials 0.000 claims abstract description 34
- 238000001755 magnetron sputter deposition Methods 0.000 claims abstract description 26
- 239000011521 glass Substances 0.000 claims abstract description 24
- 239000010408 film Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 17
- 238000004544 sputter deposition Methods 0.000 claims description 40
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 30
- 229910052786 argon Inorganic materials 0.000 claims description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 15
- 239000007789 gas Substances 0.000 claims description 15
- 239000001301 oxygen Substances 0.000 claims description 15
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 10
- 238000004140 cleaning Methods 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 6
- 239000008367 deionised water Substances 0.000 claims description 5
- 229910021641 deionized water Inorganic materials 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
- 238000001035 drying Methods 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 abstract description 4
- 231100000252 nontoxic Toxicity 0.000 abstract description 2
- 230000003000 nontoxic effect Effects 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 97
- 238000010586 diagram Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 238000010276 construction Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 239000011149 active material Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02551—Group 12/16 materials
- H01L21/02554—Oxides
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/22—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/22—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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Abstract
The invention belongs to thin-film transistor technologies field, a kind of lamination active layer thin film transistor (TFT) and preparation method thereof is disclosed.The lamination active layer thin film transistor (TFT) is by the glass substrate, the Al:Nd film gates, Al that stack gradually2O3: Nd gate insulating layer, AZO semiconductor layer, Al2O3Semiconductor decorative layer and Al source-drain electrode are constituted.AZO semiconductor layer, Al has been prepared using r. f. magnetron sputtering in the present invention2O3Semiconductor decorative layer constitutes AZO/Al2O3Active layer, the element that AZO film contains are Al, Zn, O, these three element resources are abundant, and all nontoxic, can be very good the environment protection requirement that response is advocated instantly, can realize the production of large area at the same time, and preparation process does not need to heat.
Description
Technical field
The invention belongs to thin-film transistor technologies fields, and in particular to a kind of lamination active layer thin film transistor (TFT) and its preparation
Method.
Background technique
As display develops to large scale, high-resolution and Flexible Displays.Have more to TFT (thin film transistor (TFT)) device
High requirement.Traditional TFT device is and the device of this structure using active layer of the single layer of semiconductor layer as TFT device
It generally requires to be heat-treated.It is by the single layer AZO of the room temperature preparation main difficulty for being applied to face in the active layer of TFT device at present
Defect is more in single layer AZO carrier concentration height and AZO body, cannot effectively realize the switching characteristic of TFT device.
It there is now the technology to solve the above problems: active material/insulating materials/active material/insulation material prepared using ALD
Material heap folds active layer structure (Ahn C H, Senthil K, Cho H K, et al.Artificial semiconductor/
insulator superlattice channel structure for high-performance oxide thin-film
2013,3 (39): transistors [J] .Scientific Reports 2737.), is provided although above-mentioned technology can be prepared
There is the TFT device of switching characteristic, but in order to eliminate latent defect and then improve performance, device is made annealing treatment, and with
Plastics are that the TFT device of flexible substrate cannot pass through high annealing, therefore above-mentioned method cannot be generalized in Flexible Displays；This
The active layer of TFT device described in outer this method is 6 layers, and complex process cannot effectively reduce cost.
Summary of the invention
In order to solve the disadvantage that the prior art and shortcoming, the primary purpose of the present invention is that it is active to provide a kind of lamination
Layer film transistor.
Another object of the present invention is to provide the preparation method of above-mentioned lamination active layer thin film transistor (TFT).
The purpose of the present invention is achieved through the following technical solutions:
A kind of lamination active layer thin film transistor (TFT), by glass substrate, the Al:Nd film gates, Al stacked gradually2O3: Nd grid
Pole insulating layer, AZO semiconductor layer, Al2O3Semiconductor decorative layer and Al source-drain electrode are constituted.
Preferably, the doping concentration of the Al:Nd is 1~5at%.
Preferably, the Al:Nd film gates with a thickness of 100~300nm.
Preferably, the Al2O3: the doping concentration of Nd is 1~5at%.
Preferably, the Al2O3: Nd gate insulating layer with a thickness of 200~400nm.
Preferably, the AZO semiconductor layer with a thickness of 3.5~4.5nm.
Preferably, the Al2O3Semiconductor decorative layer with a thickness of 3~4nm.
Preferably, the Al source-drain electrode with a thickness of 180~200nm.
The preparation method of above-mentioned lamination active layer thin film transistor (TFT), comprising the following steps:
(1) by substrate of glass cleaning, drying；
(2) one layer of Al:Nd film gates of Deposited By Dc Magnetron Sputtering are used on the glass substrate, then in Al:Nd film
One layer of Al is grown by anodic oxidation on grid2O3: Nd gate insulating layer；
(3) using r. f. magnetron sputtering in Al2O3: be sequentially depositing on Nd gate insulating layer one layer of AZO semiconductor layer and
One layer of Al2O3Semiconductor decorative layer, then in Al2O3One layer of Al source-drain electrode is deposited using d.c. sputtering on semiconductor decorative layer.
Preferably, step (1) cleaning is successively to clean 10~15min with deionized water and isopropanol ultrasonic vibration,
More preferably ultrasonic vibration cleans 10min.
Preferably, step (1) drying refers to dries at 80~85 DEG C, more preferably dries at 80 DEG C.
Preferably, in step (3) when depositing one layer of AZO semiconductor layer, the technique of the r. f. magnetron sputtering is joined
Number is as follows: sputtering power 100W, sputtering pressure 1mtorr, argon gas and oxygen proportion are 100:2.
Preferably, as one layer of Al of deposition in step (3)2O3When semiconductor decorative layer, the work of the r. f. magnetron sputtering
Skill parameter is as follows: sputtering power 120W, sputtering pressure 1mtorr, argon gas and oxygen proportion are 100:0.
Preferably, the technological parameter of step (3) the d.c. sputtering deposition is as follows: sputtering power 100W, sputtering pressure
It is 100:0 for 1mtorr, argon gas and oxygen proportion.
Compared with prior art, the invention has the advantages that and the utility model has the advantages that
(1) present invention is prepared for AZO semiconductor layer, Al using r. f. magnetron sputtering2O3Semiconductor decorative layer is constituted
AZO/Al2O3Active layer, the element that AZO film contains are Al, Zn, O, these three element resources are abundant, and all nontoxic, can
To respond the environment protection requirement advocated instantly well.
(2) present invention employs the double-deck AZO/Al2O3Active layer of the structure as TFT device, does not need to be heat-treated,
It may be directly applied to flexible device field.
(3) present invention prepares bilayer AZO/Al using magnetron sputtering2O3Structure can be realized large area preparation.
Detailed description of the invention
Fig. 1 is a kind of stepped construction schematic diagram of lamination active layer thin film transistor (TFT) of the present invention, wherein 01 is glass
Glass substrate, 02 is Al:Nd film gates, and 03 is Al2O3: Nd gate insulating layer, 04 is AZO semiconductor layer, and 05 is Al2O3Partly lead
Body decorative layer, 06 is Al source-drain electrode.
Fig. 2 is a kind of output characteristic curve figure of lamination active layer thin film transistor (TFT) prepared by embodiment 1.
Fig. 3 is a kind of transfer characteristic curve figure of lamination active layer thin film transistor (TFT) prepared by embodiment 1.
Fig. 4 is a kind of output characteristic curve figure of lamination active layer thin film transistor (TFT) prepared by embodiment 2.
Fig. 5 is a kind of transfer characteristic curve figure of lamination active layer thin film transistor (TFT) prepared by embodiment 2.
Fig. 6 is a kind of output characteristic curve figure of lamination active layer thin film transistor (TFT) prepared by embodiment 3.
Fig. 7 is a kind of transfer characteristic curve figure of lamination active layer thin film transistor (TFT) prepared by embodiment 3.
Specific embodiment
Below with reference to embodiment, the present invention is described in further detail, and embodiments of the present invention are not limited thereto.
Embodiment 1
A kind of lamination active layer thin film transistor (TFT) manufactured in the present embodiment, stepped construction schematic diagram are as shown in Figure 1.By according to
The substrate of glass 01 of secondary stacking, Al:Nd film gates 02, Al2O3: Nd gate insulating layer 03, AZO semiconductor layer 04, Al2O3Half
Conductor decorative layer 05, Al source-drain electrode 06 are constituted.
Lamination active layer thin film transistor (TFT) described in the present embodiment the preparation method is as follows:
(1) substrate of glass is successively cleaned into 10min with deionized water and isopropanol ultrasonic vibration, then by the glass after cleaning
Glass substrate is put into baking oven, dries at 80 DEG C；
(2) the Al:Nd film gates (doping of Nd of one layer of 200nm of Deposited By Dc Magnetron Sputtering is used on the glass substrate
Concentration is 3at%), the Al of one layer of 300nm is then grown by anodic oxidation on Al:Nd film gates2O3: Nd gate insulator
Layer (doping concentration of Nd is 3at%).
(3) in Al2O3: pass through the AZO semiconductor layer of one layer of 4nm of r. f. magnetron sputtering on Nd gate insulating layer, it is described
The technological parameter of r. f. magnetron sputtering is as follows: sputtering power 100W, sputtering pressure 1mtorr, argon gas and oxygen proportion
For 100:2；Then pass through the Al of one layer of 3.5nm of r. f. magnetron sputtering on AZO semiconductor layer2O3Semiconductor decorative layer, institute
The technological parameter for stating r. f. magnetron sputtering is as follows: sputtering power 120W, sputtering pressure 1mtorr, argon gas and oxygen ratio
Example is 100:0；Finally in Al2O3The Al source-drain electrode of one layer of 200nm is deposited on semiconductor decorative layer using d.c. sputtering, it is described
The technological parameter of d.c. sputtering deposition is as follows: sputtering power 100W, sputtering pressure 1mtorr, argon gas and oxygen proportion are
100:0。
A kind of output characteristic curve figure of lamination active layer thin film transistor (TFT) prepared by embodiment 1 is as shown in Fig. 2, it is shifted
Performance diagram as shown in figure 3, from the result of Fig. 2 and 3 it can be concluded that, the saturation mobility [mu] of the TFTsatFor 0.7cm2/ Vs,
On-off ratio Ion/IoffIt is 1.34 × 105。
Embodiment 2
A kind of lamination active layer thin film transistor (TFT) manufactured in the present embodiment, stepped construction schematic diagram are as shown in Figure 1.By according to
The substrate of glass 01 of secondary stacking, Al:Nd film gates 02, Al2O3: Nd gate insulating layer 03, AZO semiconductor layer 04, Al2O3Half
Conductor decorative layer 05, Al source-drain electrode 06 are constituted.
Lamination active layer thin film transistor (TFT) described in the present embodiment the preparation method is as follows:
(1) substrate of glass is successively cleaned into 10min with deionized water and isopropanol ultrasonic vibration, then by the glass after cleaning
Glass substrate is put into baking oven, dries at 80 DEG C；
(2) the Al:Nd film gates (doping of Nd of one layer of 200nm of Deposited By Dc Magnetron Sputtering is used on the glass substrate
Concentration is 3at%), the Al of one layer of 300nm is then grown by anodic oxidation on Al:Nd film gates2O3: Nd gate insulator
Layer (doping concentration of Nd is 3at%).
(3) in Al2O3: pass through the AZO semiconductor layer of one layer of 3.2nm of r. f. magnetron sputtering, institute on Nd gate insulating layer
The technological parameter for stating r. f. magnetron sputtering is as follows: sputtering power 100W, sputtering pressure 1mtorr, argon gas and oxygen ratio
Example is 100:2；Then pass through the Al of one layer of 3.5nm of r. f. magnetron sputtering on AZO semiconductor layer2O3Semiconductor decorative layer,
The technological parameter of the r. f. magnetron sputtering is as follows: sputtering power 120W, sputtering pressure 1mtorr, argon gas and oxygen
Ratio is 100:0；Finally in Al2O3The Al source-drain electrode of one layer of 200nm, institute are deposited on semiconductor decorative layer using d.c. sputtering
The technological parameter for stating d.c. sputtering deposition is as follows: sputtering power 100W, sputtering pressure 1mtorr, argon gas and oxygen proportion are
100:0。
A kind of output characteristic curve figure of lamination active layer thin film transistor (TFT) prepared by embodiment 2 is as shown in figure 4, it is shifted
Performance diagram as shown in figure 5, from the result of Figure 4 and 5 it can be concluded that, the saturation mobility [mu] of the TFTsatFor 0.06cm2/V·
S, on-off ratio Ion/IoffIt is 2.25 × 104。
Embodiment 3
A kind of lamination active layer thin film transistor (TFT) manufactured in the present embodiment, stepped construction schematic diagram are as shown in Figure 1.By according to
The substrate of glass 01 of secondary stacking, Al:Nd film gates 02, Al2O3: Nd gate insulating layer 03, AZO semiconductor layer 04, Al2O3Half
Conductor decorative layer 05, Al source-drain electrode 06 are constituted.
Lamination active layer thin film transistor (TFT) described in the present embodiment the preparation method is as follows:
(1) substrate of glass is successively cleaned into 10min with deionized water and isopropanol ultrasonic vibration, then by the glass after cleaning
Glass substrate is put into baking oven, dries at 80 DEG C；
(2) the Al:Nd film gates (doping of Nd of one layer of 200nm of Deposited By Dc Magnetron Sputtering is used on the glass substrate
Concentration is 3at%), the Al of one layer of 300nm is then grown by anodic oxidation on Al:Nd film gates2O3: Nd gate insulator
Layer (doping concentration of Nd is 3at%).
(3) in Al2O3: pass through the AZO semiconductor layer of one layer of 3.8nm of r. f. magnetron sputtering, institute on Nd gate insulating layer
The technological parameter for stating r. f. magnetron sputtering is as follows: sputtering power 100W, sputtering pressure 1mtorr, argon gas and oxygen ratio
Example is 100:2；Then pass through the Al of one layer of 3.5nm of r. f. magnetron sputtering on AZO semiconductor layer2O3Semiconductor decorative layer,
The technological parameter of the r. f. magnetron sputtering is as follows: sputtering power 120W, sputtering pressure 1mtorr, argon gas and oxygen
Ratio is 100:0；Finally in Al2O3The Al source-drain electrode of one layer of 200nm, institute are deposited on semiconductor decorative layer using d.c. sputtering
The technological parameter for stating d.c. sputtering deposition is as follows: sputtering power 100W, sputtering pressure 1mtorr, argon gas and oxygen proportion are
100:0。
A kind of output characteristic curve figure of lamination active layer thin film transistor (TFT) prepared by embodiment 3 is as shown in fig. 6, it is shifted
Performance diagram as shown in fig. 7, from the result of Fig. 6 and 7 it can be concluded that, the saturation mobility [mu] of the TFTsatFor 0.4cm2/ Vs,
On-off ratio Ion/IoffIt is 8.84 × 104。
The above embodiment is a preferred embodiment of the present invention, but embodiments of the present invention are not by above-described embodiment
Limitation, other any changes, modifications, substitutions, combinations, simplifications made without departing from the spirit and principles of the present invention,
It should be equivalent substitute mode, be included within the scope of the present invention.
Claims (10)
1. a kind of lamination active layer thin film transistor (TFT), which is characterized in that by stack gradually glass substrate, Al:Nd film gates,
Al2O3: Nd gate insulating layer, AZO semiconductor layer, Al2O3Semiconductor decorative layer and Al source-drain electrode are constituted.
2. lamination active layer thin film transistor (TFT) according to claim 1, which is characterized in that the doping concentration of the Al:Nd
For 1~5at%, the Al:Nd film gates with a thickness of 100~300nm.
3. lamination active layer thin film transistor (TFT) according to claim 2, which is characterized in that the Al2O3: the doping of Nd is dense
Degree is 1~5at%, the Al2O3: Nd gate insulating layer with a thickness of 200~400nm.
4. lamination active layer thin film transistor (TFT) according to claim 3, which is characterized in that the thickness of the AZO semiconductor layer
Degree is 3.5~4.5nm, the Al2O3Semiconductor decorative layer with a thickness of 3~4nm.
5. lamination active layer thin film transistor (TFT) according to any one of claims 1 to 4, which is characterized in that the Al source and drain
Electrode with a thickness of 180~200nm.
6. the preparation method of any one of Claims 1 to 5 lamination active layer thin film transistor (TFT), which is characterized in that including with
Lower step:
(1) by substrate of glass cleaning, drying；
(2) one layer of Al:Nd film gates of Deposited By Dc Magnetron Sputtering are used on the glass substrate, then in Al:Nd film gates
It is upper that one layer of Al is grown by anodic oxidation2O3: Nd gate insulating layer；
(3) using r. f. magnetron sputtering in Al2O3: one layer of AZO semiconductor layer and one layer are sequentially depositing on Nd gate insulating layer
Al2O3Semiconductor decorative layer, then in Al2O3One layer of Al source-drain electrode is deposited using d.c. sputtering on semiconductor decorative layer.
7. the preparation method of lamination active layer thin film transistor (TFT) according to claim 6, which is characterized in that step (1) is described
Successively to clean 10~15min with deionized water and isopropanol ultrasonic vibration, step (1) drying refers to 80~85 for cleaning
It is dried at DEG C.
8. the preparation method of lamination active layer thin film transistor (TFT) according to claim 6, which is characterized in that in step (3) when
When depositing one layer of AZO semiconductor layer, the technological parameter of the r. f. magnetron sputtering is as follows: sputtering power 100W, sputtering
Air pressure is 1mtorr, argon gas and oxygen proportion are 100:2.
9. the preparation method of lamination active layer thin film transistor (TFT) according to claim 6, which is characterized in that in step (3) when
Deposit one layer of Al2O3When semiconductor decorative layer, the technological parameter of the r. f. magnetron sputtering is as follows: sputtering power 120W,
Sputtering pressure is 1mtorr, argon gas and oxygen proportion are 100:0.
10. the preparation method of lamination active layer thin film transistor (TFT) according to claim 6, which is characterized in that step (3) is described
The technological parameter of d.c. sputtering deposition is as follows: sputtering power 100W, sputtering pressure 1mtorr, argon gas and oxygen proportion are
100:0。
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| CN201811146879.5A CN109390411A (en) | 2018-09-29 | 2018-09-29 | A kind of lamination active layer thin film transistor (TFT) and preparation method thereof |
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| CN105679833A (en) * | 2016-01-12 | 2016-06-15 | 华南理工大学 | Thin film transistor with laminated active layer and preparation method for thin film transistor |
| CN107170832A (en) * | 2017-06-14 | 2017-09-15 | 华南理工大学 | A kind of oxide thin film transistor and preparation method thereof |
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Application publication date: 20190226 |