CN109390347B - Three-dimensional storage device and forming method thereof - Google Patents

Three-dimensional storage device and forming method thereof Download PDF

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Publication number
CN109390347B
CN109390347B CN201811169224.XA CN201811169224A CN109390347B CN 109390347 B CN109390347 B CN 109390347B CN 201811169224 A CN201811169224 A CN 201811169224A CN 109390347 B CN109390347 B CN 109390347B
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layer
stack
material layer
channel hole
memory device
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CN109390347A (en
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杨号号
张若芳
张富山
徐前兵
王恩博
李兆松
刘沙沙
卢峰
何家兰
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

The embodiment of the invention discloses a three-dimensional storage device and a forming method thereof, wherein the method comprises the following steps: filling a lower channel hole with polysilicon along an upper surface of a lower stack of a three-dimensional memory device to deposit a first polysilicon layer on the upper surface of the lower stack and a second polysilicon layer on the lower channel hole; polishing to remove the first polysilicon layer and the lower lamination layer with the preset thickness; depositing a first material layer over the polished lower stack; depositing an upper stack over the first material layer; and etching the upper lamination to form an upper channel hole corresponding to the lower channel hole.

Description

Three-dimensional storage device and forming method thereof
Technical Field
The embodiment of the invention relates to the field of semiconductor devices and manufacturing thereof, in particular to a three-dimensional memory device and a forming method thereof.
Background
To overcome the limitations of the two-dimensional memory device, the industry has developed a memory device having a three-dimensional structure to increase integration density by arranging memory cells three-dimensionally over a substrate.
In an existing dual-layer three-dimensional memory device, for example, a dual-layer three-dimensional computer flash memory device (3D NAND) memory device, an upper layer stack and a lower layer stack of the dual-layer three-dimensional memory device are stacked vertically to form a stacked 3D NAND memory device. As shown in fig. 1, the conventional dual-layer 3D NAND memory device is shown, in which a lower stack 10 and an upper stack 11 of the stacked memory device are formed by alternately stacking semiconductor layers 101 and insulating layers 102, and the upper stack 11 has an upper via Hole corresponding to a lower via Hole (CH) of the lower stack.
However, in the conventional two-layer three-dimensional memory device, a corner portion 13 is formed at the overlapping portion of the upper via hole of the upper stack and the lower via hole of the lower stack, and the semiconductor layer 101 of the upper stack 11 or the lower stack 10 is in contact with the corner portion 13, so that a weak region is easily formed at the corner portion 13 in the subsequent process of removing the semiconductor layer 101 and filling the metal layer, thereby affecting the reliability of the device.
Disclosure of Invention
In view of the above, embodiments of the present invention provide a method for forming a three-dimensional memory device and a three-dimensional memory device, which can avoid the problem that the reliability of the device is affected by the weak region easily formed at the corner portion in the process of removing the semiconductor layer and filling the metal layer.
The technical scheme of the embodiment of the invention is realized as follows:
in a first aspect, an embodiment of the present invention provides a method for forming a three-dimensional memory device, where the method includes:
filling a lower channel hole with polysilicon along an upper surface of a lower stack of a three-dimensional memory device to deposit a first polysilicon layer on the upper surface of the lower stack and a second polysilicon layer on the lower channel hole;
polishing to remove the first polysilicon layer and the lower lamination layer with the preset thickness;
depositing a first material layer over the polished lower stack;
depositing an upper stack over the first material layer;
and etching the upper lamination to form an upper channel hole corresponding to the lower channel hole.
In other embodiments, the lower stack and the upper stack are formed by alternately stacking a plurality of second material layers and a plurality of third material layers;
the polishing removes the first polysilicon layer and the lower lamination with the preset thickness, and comprises the following steps:
polishing and removing the first polysilicon layer by adopting a Chemical Mechanical Polishing (CMP) process;
leaving a first layer of the second material adjacent to the upper surface of the lower stack.
In other embodiments, the polishing removes the first polysilicon layer and the lower stack of predetermined thicknesses, including:
if the uppermost layer of the lower lamination layer is the third material layer, polishing and removing the first polycrystalline silicon layer and the uppermost layer of the lower lamination layer by adopting the CMP process;
and if the uppermost layer of the lower laminated layer is the second material layer, polishing and removing the first polycrystalline silicon layer by adopting the CMP process.
In other embodiments, the depositing a first material layer over the polished lower stack includes:
depositing said first layer of material over said first layer of second material; wherein, the first second material layer and the first material layer are made of the same material.
In other embodiments, before filling the lower via hole with polysilicon along an upper surface of the lower stack of the three-dimensional memory device, the method further comprises:
and etching the lower lamination of the three-dimensional memory device to form the lower channel hole.
In other embodiments, after forming the lower channel hole, the method further comprises:
sequentially forming a first silicon oxide-silicon nitride-silicon oxide ONO structure along the side wall of the lower channel hole from inside to outside;
and after the upper channel hole is formed, a second ONO structure is formed along the side wall of the upper channel hole from inside to outside.
In other embodiments, after etching the upper stack to form an upper via hole corresponding to the lower via hole, the method further comprises:
removing the third material layer to form a blank layer;
and filling a metal material in the blank layer to form a metal layer.
In a second aspect, an embodiment of the present invention provides a three-dimensional memory device, including:
a lower lamination layer;
a lower channel aperture located within the lower stack;
a second polysilicon layer covering the lower channel hole;
a first material layer deposited over the polished lower stack;
an upper layer stack deposited over the first material layer;
an upper channel hole within the upper stack corresponding to the lower channel hole.
In other embodiments, the lower stack and the upper stack are formed by alternately stacking a plurality of second material layers and a plurality of third material layers;
the uppermost layer of the polished lower lamination is a first second material layer close to the upper surface of the lower lamination; wherein, the first second material layer and the first material layer are made of the same material.
In other embodiments, the three-dimensional memory device further comprises:
a first silicon oxide-silicon nitride-silicon oxide ONO structure sequentially formed along the side wall of the lower channel hole from inside to outside; and a second ONO structure formed along the sidewall of the upper channel hole from inside to outside.
In other embodiments, the three-dimensional memory device further comprises:
and a metal layer formed by filling a metal material at the blank layer formed after the third material layer is removed.
In other embodiments, the overlapping position of the lower laminate and the upper laminate forms a corner portion, the corner portion is in contact with the first material layer or the second material layer, and the corner portion is not in contact with the third material layer.
The embodiment of the invention provides a three-dimensional storage device and a forming method thereof, wherein the method comprises the following steps: filling a lower channel hole with polysilicon along an upper surface of a lower stack of a three-dimensional memory device to deposit a first polysilicon layer on the upper surface of the lower stack and a second polysilicon layer on the lower channel hole; polishing to remove the first polysilicon layer and the lower lamination layer with the preset thickness; depositing a first material layer over the polished lower stack; depositing an upper stack over the first material layer; and etching the upper lamination to form an upper channel hole corresponding to the lower channel hole. In this way, since the first material layer is deposited on the polished lower stack, the formed corner part can be ensured not to be in contact with the semiconductor layer, so that a weak area can not be formed on the corner part in the subsequent process of removing the semiconductor layer and filling the metal layer, and the reliability of the device can be improved.
Drawings
In the drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different examples of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed herein.
FIG. 1 is a conventional dual-layer 3D NAND memory device;
fig. 2 is a schematic flow chart illustrating an implementation of a method for forming a three-dimensional memory device according to an embodiment of the present invention;
FIG. 3A is a schematic diagram of a process of forming a first polysilicon layer and a second polysilicon layer in a three-dimensional memory device according to an embodiment of the invention;
FIG. 3B is a schematic diagram of a process of polishing a first polysilicon layer in a three-dimensional memory device according to an embodiment of the invention;
FIG. 3C is a schematic diagram of a process of depositing a first material layer for a three-dimensional memory device according to an embodiment of the invention;
FIG. 3D is a schematic diagram of a process for forming an upper stack layer of a three-dimensional memory device according to an embodiment of the invention;
FIG. 3E is a schematic diagram of a process for forming an upper via hole in a three-dimensional memory device according to an embodiment of the invention;
fig. 4 is a schematic flow chart illustrating an implementation of a method for forming a three-dimensional memory device according to a second embodiment of the present invention;
FIG. 5A is a schematic diagram of a process of forming an isolation layer on a substrate in a two-dimensional memory device according to an embodiment of the invention;
FIG. 5B is a schematic diagram of a process of forming a lower stack layer of a two-dimensional memory device according to an embodiment of the invention;
FIG. 5C is a schematic diagram of a process of forming a lower via hole in a two-dimensional memory device according to an embodiment of the invention;
FIG. 5D is a schematic diagram illustrating a process of forming a first ONO structure in a two-dimensional memory device according to an embodiment of the present invention;
FIG. 5E is a schematic diagram of a process of forming a first polysilicon layer and a second polysilicon layer in a two-dimensional memory device according to an embodiment of the invention;
FIG. 5F is a schematic diagram of a process of polishing a first polysilicon layer in a two-dimensional memory device according to an embodiment of the invention;
FIG. 5G is a schematic diagram of a process of depositing a first material layer for a two-dimensional memory device according to an embodiment of the invention;
FIG. 5H is a schematic diagram of a process of forming an upper stack layer of a two-dimensional memory device according to an embodiment of the present invention;
FIG. 5I is a schematic diagram of a process of forming an upper via hole in a two-dimensional memory device according to an embodiment of the invention;
FIG. 5J is a schematic diagram illustrating a process of forming a second ONO structure in a two-dimensional memory device according to an embodiment of the invention;
FIG. 5K is a schematic diagram of a process of forming a blank layer in a two-dimensional memory device according to an embodiment of the invention;
FIG. 5L is a schematic diagram of a process of forming a metal layer in a two-dimensional memory device according to an embodiment of the invention;
fig. 6 is a schematic structural diagram of a three-dimensional memory device according to a third embodiment of the present invention;
fig. 7 is a schematic structural diagram of a three-dimensional memory device according to a fourth embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the following describes specific technical solutions of the present invention in further detail with reference to the accompanying drawings in the embodiments of the present invention. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.
In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
Example one
An embodiment of the present invention provides a method for forming a three-dimensional memory device, and fig. 2 is a schematic diagram illustrating an implementation flow of the method for forming a three-dimensional memory device according to an embodiment of the present invention, as shown in fig. 2, the method includes the following steps:
step S201, filling a lower via hole with polysilicon along an upper surface of a lower stack of a three-dimensional memory device to deposit a first polysilicon layer on the upper surface of the lower stack and to deposit a second polysilicon layer on the lower via hole.
As shown in fig. 3A, a polysilicon (polysilicon) material is filled on the upper surface of the lower stack 31 having the lower via hole 311 to deposit a first polysilicon layer 312 on the upper surface of the lower stack, the first polysilicon layer 321 covering the upper surface of the lower stack 31, and a second polysilicon layer 313 deposited on the lower via hole 311, the second polysilicon layer 313 covering the lower via hole 311. Wherein the first polysilicon layer 312 is connected to the second polysilicon layer 313.
It should be noted that, before the step S201 of etching the lower stack of the three-dimensional memory device, the method further includes the following steps:
in step S2011, the lower stack of the three-dimensional memory device is etched to form a lower via hole.
In this embodiment, the lower via hole is a through hole in the lower stack, and the lower stack may be etched by using an Etching technique, such as a Reactive Ion Etching (RIE) technique, until the substrate surface is exposed, so as to form the lower via hole. Alternatively, the lower via hole may be formed by photolithography, for example, by exposing after covering a photoresist layer, and then etching.
Step S202, polishing and removing the first polysilicon layer and the lower lamination layer with the preset thickness.
Here, the lower stack and the upper stack are formed by alternately stacking a plurality of second material layers 302 and a plurality of third material layers 303. The second material layer 302 is an insulating layer, the third material layer 303 is a semiconductor layer, for example, the second material layer 302 may be silicon oxide, and the third material layer 303 may be silicon nitride. The lower stack layer and the upper stack layer of the three-dimensional memory device are stack layers in which insulating layers and semiconductor layers are alternately stacked.
In this embodiment, the step S202 of polishing and removing the first polysilicon layer and the lower stacked layer with a preset thickness may be implemented by the following steps:
step S2021, polishing and removing the first polysilicon layer by using a chemical mechanical polishing CMP process.
Step S2022, leaving the first second material layer adjacent to the upper surface of the lower stack.
As shown in fig. 3B, when performing the CMP process, the first polysilicon layer 312 is polished first, and then the upper surface of the lower stack is further polished until the preset thickness of the lower stack is polished. Here, the preset thickness of the lower laminate is ground such that when the first second material layer 302a near the upper surface of the lower laminate is ground, the grinding is stopped, thereby achieving retention of the first second material layer 302a near the upper surface of the lower laminate.
Step S203, a first material layer is deposited on the polished lower stack.
As shown in fig. 3C, a first material layer 301 is deposited on top of the ground lower stack, where the first material layer 301 is the same material as the first second material layer 302 a. After depositing a first material layer on top of the ground lower stack, the first material layer 301 is overlapped with the first second material layer 302a to form a new insulating layer 302 with a certain thickness.
Step S204, depositing and forming an upper lamination layer on the first material layer.
As shown in fig. 3D, an upper stack 32 is deposited on the first material layer 301, and the upper stack 32 is also formed by alternately stacking a plurality of second material layers 302 and a plurality of third material layers 303, as well as the lower stack 31. The second material layer 302 is an insulating layer, the third material layer 303 is a semiconductor layer, for example, the second material layer 302 may be silicon oxide, and the third material layer 303 may be silicon nitride. The upper lamination layer and the lower lamination layer of the three-dimensional memory device are all stacking layers formed by alternately stacking insulating layers and semiconductor layers.
In this embodiment, a plurality of second material layers 302 and third material layers 303 may be alternately stacked on the first material Layer 301 in sequence by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or other Deposition methods.
Step S205, etching the upper lamination to form an upper channel hole corresponding to the lower channel hole.
In the present embodiment, after the upper stack layer 32 is deposited on the first material layer 301, as shown in fig. 3E, the upper stack layer 32 of the three-dimensional memory device is etched corresponding to the lower via hole 311 to form an upper via hole 321 corresponding to the lower via hole 311. Wherein each upper passage hole 321 corresponds to one lower passage hole 311. Here, the correspondence means that the upper passage hole 321 is positioned directly above the lower passage hole 311, and the upper passage hole 321 communicates with the lower passage hole 311.
The method for forming the three-dimensional memory device comprises the steps of firstly, filling polycrystalline silicon into a lower channel hole along the upper surface of a lower lamination of the three-dimensional memory device to form a first polycrystalline silicon layer covering the upper surface of the lower lamination and a second polycrystalline silicon layer covering the lower channel hole; then, polishing and removing the first polysilicon layer and the lower laminated layer with the preset thickness; depositing a first material layer over the polished lower stack; finally, depositing an upper lamination layer on the first material layer; and etching the upper lamination to form an upper channel hole corresponding to the lower channel hole. Thus, the corner part formed by the overlapped part of the upper channel hole of the upper lamination and the lower channel hole of the lower lamination is ensured not to be contacted with the semiconductor layer, so that a weak area is not formed on the corner part in the subsequent process of removing the semiconductor layer and filling the metal layer, and the reliability of the device can be improved.
Example two
An embodiment of the present invention provides a method for forming a three-dimensional memory device, and fig. 4 is a schematic diagram illustrating an implementation flow of a method for forming a three-dimensional memory device according to a second embodiment of the present invention, as shown in fig. 4, the method includes the following steps:
step S401, providing a substrate, and forming an isolation layer on the substrate.
As shown in fig. 5A, an isolation layer 52 is formed on a substrate 51. The material of the substrate 51 may be selected from one of silicon Si, silicon germanium alloy SiGe, silicon carbide SiC, alumina Al2O3, aluminum nitride AlN, zinc oxide ZnO, gallium oxide Ga2O3, lithium aluminate LiAlO2, and the like. Since the Si substrate is inexpensive and easy to dope and at the same time is easy to react to form a heterogeneous isolation layer, Si may be selected as the substrate 51 in the present embodiment.
The isolation layer 52 may be a silicon oxide material, and the isolation layer 52 functions to electrically isolate the substrate 51 from the upper structure of the isolation layer 52.
Step S402, forming a lower stack layer over the isolation layer.
As shown in fig. 5B, the lower stack 53 may be formed by vertically stacking a plurality of memory cells. For example, the lower stack 53 may be formed by alternately stacking a plurality of second material layers 502 and a plurality of third material layers 503. The number of the second material layers 502 and the third material layers 503 may be any number. Multiple layers of second material 502 and third material 503 are alternately stacked on the isolation layer 52 in sequence by CVD or ALD or other deposition methods.
In this embodiment, the third material layer 503 is a semiconductor layer, and the third material layer 503 may be silicon nitride; the second material layer 502 is an insulating layer, and the second material layer 502 may be silicon oxide.
Step S403, etching the lower stacked layer of the three-dimensional memory device to form the lower via hole.
After forming the lower stack 53 over the isolation layer 52, as shown in fig. 5C, the lower stack 53 of the three-dimensional memory device is etched to form a lower via hole 533.
In the present embodiment, the lower via hole 533 is a through hole in the lower stack 53, and an etching technique, such as RIE, may be used to etch the lower stack until the substrate surface is exposed to form the lower via hole. Alternatively, the lower via hole 533 may be realized by using a photolithography technique, for example, exposing after covering the photoresist layer, and then etching.
In step S404, a first silicon oxide-silicon nitride-silicon oxide ONO structure is sequentially formed along the sidewall of the lower channel hole from inside to outside.
In the process of forming the three-dimensional memory device, after the lower stack layer of the three-dimensional memory device is etched to form the lower via hole 533, a first ONO structure forming step is further performed with respect to the lower via hole 533. As shown in fig. 5D, a blocking insulating layer 5341, a charge trapping layer 5342 and a tunneling insulating layer 5343 are sequentially formed along the sidewall of the lower channel hole 533 from the inside to the outside. The blocking insulating layer 5341, the charge trap layer 5342, and the tunneling insulating layer 5343 constitute a memory layer of the three-dimensional memory device. The blocking insulating layer 5341 may be made of silicon oxide, the charge trapping layer 5342 may be made of silicon nitride, and the tunneling insulating layer 5343 may be made of silicon oxide, such that the memory layer formed of silicon oxide-silicon nitride-silicon oxide is the first ONO structure 534. Of course, other materials may be selected for each layer in the first ONO structure, which is not limited in this embodiment.
Step S405, filling a lower via hole with polysilicon along an upper surface of a lower stack of a three-dimensional memory device, forming a first polysilicon layer covering the upper surface of the lower stack, and a second polysilicon layer covering the lower via hole.
As shown in fig. 5E, the upper surface of the lower stack 53 having the lower via hole 533 is filled with a polysilicon material to form a first polysilicon layer 531 covering the upper surface of the lower stack 53 and a second polysilicon layer 532 covering the lower via hole 533. Wherein the first polysilicon layer 531 is connected to the second polysilicon layer 532.
Step S406, polishing and removing the first polysilicon layer and the lower lamination layer with the preset thickness.
Here, the lower stack and the upper stack are formed by alternately stacking a plurality of second material layers 502 and a plurality of third material layers 503. The second material layer 502 is an insulating layer, and the third material layer 503 is a semiconductor layer.
In an embodiment of the present invention, step S406 may be implemented by the following steps:
step S4061, if the uppermost layer of the lower lamination layer is the third material layer, the CMP process is adopted to polish and remove the first polysilicon layer and the uppermost layer of the lower lamination layer.
Here, if the uppermost layer of the lower stack is the third material layer, which means that the uppermost layer of the lower stack is the semiconductor layer, it is necessary to polish off the semiconductor layer of the uppermost layer. Therefore, after the CMP process is used to polish and remove the first polysilicon layer, the lower stack layer needs to be further polished until the uppermost layer of the lower stack layer is polished.
Step S4062, if the uppermost layer of the lower lamination layer is the second material layer, the CMP process is adopted to polish and remove the first polysilicon layer.
Here, if the uppermost layer of the lower stack is the second material layer, indicating that the uppermost layer of the lower stack is an insulating layer, the uppermost layer of the lower stack may remain. Therefore, the first polysilicon layer can be removed only by polishing by the CMP process without polishing the lower lamination layer continuously.
As shown in fig. 5F, the first polysilicon layer and the lower stack with a predetermined thickness are removed for polishing, and the first second material layer 502a near the upper surface of the lower stack is remained.
In step S407, a first material layer is deposited on the polished lower stack.
In an embodiment of the present invention, step S407 may be implemented by the following steps:
step S4071, depositing the first material layer over the first second material layer.
Here, the first second material layer 502a is the same material as the first material layer 501. As shown in fig. 5G, the first material layer 501 is deposited on the first second material layer 502 a. After depositing the first material layer 501 on the polished lower stack, the first material layer 501 is overlapped with the first second material layer 502a to form a new insulating layer 512 with a certain thickness.
Step S408, depositing an upper stack layer over the first material layer.
After the deposition of the first material layer 501 is completed, as shown in fig. 5H, an upper stack 54 is deposited over the first material layer, and the upper stack 54 may be formed by vertically stacking a plurality of memory cells, as the lower stack 53. For example, the upper stack 54 may be formed by cyclically stacking the second material layer 502 and the third material layer 503. The number of the second material layer 502 and the third material layer 503 may be any number. A plurality of second material layers 502 and third material layers 503 are alternately stacked on the first material layer 501 in sequence by CVD or ALD or other deposition methods.
Step 409, etching the upper lamination to form an upper channel hole corresponding to the lower channel hole.
As shown in fig. 5I, the upper stack 54 is etched corresponding to the lower via hole 533, so as to form the upper via hole 541 in the upper stack 54.
In step S410, a second ONO structure is formed along the sidewall of the upper via hole from inside to outside.
In the process of forming the three-dimensional memory device, after the upper stack of the three-dimensional memory device is etched to form the upper channel hole 541, a second ONO structure forming step is also performed with respect to the upper channel hole 541. As shown in fig. 5J, a blocking insulating layer 5421, a charge trapping layer 5422, and a tunneling insulating layer 5423 are sequentially formed along the sidewall of the upper channel hole 541 from the inside to the outside. The blocking insulating layer 5421, the charge trap layer 5422, and the tunnel insulating layer 5423 constitute a storage layer of the three-dimensional memory device. The material of the blocking insulating layer 5421 may be silicon oxide, the material of the charge trapping layer 5422 may be silicon nitride, and the material of the tunneling insulating layer 5423 may be silicon oxide, so that the memory layer formed of silicon oxide-silicon nitride-silicon oxide is the second ONO structure 542. Of course, other materials may be selected for each layer in the second ONO structure, which is not limited in this embodiment.
In step S411, the third material layer is removed to form a blank layer.
As shown in fig. 5K, the third material layer 503 is a silicon nitride layer, so that the silicon nitride layer can be removed by using phosphoric acid, and after the third material layer 503 serving as a semiconductor layer is removed, a blank layer 504 is formed at the position of the third material layer 503, and the blank layer 504 is used for refilling the metal layer.
Step S412, filling a metal material in the blank layer to form a metal layer.
As shown in fig. 5L, a metal material is filled in the blank layer 504 to form a metal layer 505. In this embodiment, the metal material may be tungsten.
According to the method for forming the three-dimensional memory device, the insulating layer of silicon oxide is formed at the overlapped part of the lower lamination layer and the upper lamination layer, so that the semiconductor layer of silicon nitride is not contacted with the corner part formed at the overlapped part, and thus, in the processes of removing the semiconductor layer to form a blank layer and filling the metal layer, a weak area is not formed at the corner part, and the reliability of the device can be improved.
EXAMPLE III
The embodiment of the invention provides a three-dimensional storage device, and in the embodiment, the three-dimensional storage device can be a 3D flash memory, such as a 3D NAND flash memory.
Fig. 6 is a schematic structural diagram of a three-dimensional memory device according to a third embodiment of the present invention, and as shown in fig. 6, the three-dimensional memory device includes:
a lower laminate 61;
a lower channel hole 611 located within the lower stack 61;
a second polysilicon layer 62 covering the lower channel hole 611;
a first material layer 63 deposited over the polished lower stack;
an upper layer stack 64 deposited over the first material layer 63;
an upper channel hole 641 corresponding to the lower channel hole 611 located within the upper stack 64.
Here, the lower stack 61 is a stack in which insulating layers and semiconductor layers are alternately stacked. The lower stack 61 may be formed in a manner of vertically stacking a plurality of memory cells. For example, the lower stack 61 may be formed by cyclically stacking the second material layer 612 and the third material layer 613. The number of the second material layer 612 and the third material layer 613 may be any number. A plurality of second material layers 612 and third material layers 613 are alternately deposited and stacked in sequence by CVD or ALD or other deposition methods. The third material layer 613 is a semiconductor layer, and the third material layer 613 may be silicon nitride; the second material layer 612 is an insulating layer, and the second material layer 612 may be silicon oxide.
The lower via hole 611, which is a through hole in the lower stack 61, may be formed by etching the lower stack using an etching technique until the substrate surface is exposed, so as to form the lower via hole 611. Alternatively, the lower channel hole 611 may be formed by photolithography, for example, by exposing after covering a photoresist layer, and then etching.
The second polysilicon layer 62 is formed to cover the lower via hole 611 in order to fill the lower via hole 611 with a polysilicon material.
The first material layer 63 and the second material layer 612 are the same material.
The upper stack 64, like the lower stack 61, may be formed by vertically stacking a plurality of memory cells. For example, the upper stack 64 may also be formed by cyclically stacking the second material layer 612 and the third material layer 613. The number of the second material layer 612 and the third material layer 613 may be any number. A plurality of second material layers 612 and third material layers 613 are alternately stacked on the first material layers 63 in sequence by CVD or ALD or other deposition methods.
The upper via 641, which is a through hole in the upper stack 64, can also be etched by the same etching technique as the lower via 611 until the substrate surface is exposed, so as to form the upper via 641. Alternatively, the upper channel hole 641 may be implemented by using a photolithography technique, for example, exposing after covering a photoresist layer, and then etching.
According to the three-dimensional memory device provided by the embodiment of the invention, the first material layer is deposited on the polished lower lamination, and then the first material layer, namely silicon oxide, is in contact with the corner part formed at the overlapped part of the lower lamination and the upper lamination, so that a weak area cannot be formed at the corner part in the subsequent process of removing the semiconductor layer (third material layer) and filling the metal layer, and the reliability of the device can be improved.
Example four
The embodiment of the invention provides a three-dimensional storage device, and in the embodiment, the three-dimensional storage device can be a 3D flash memory, such as a 3D NAND flash memory.
Fig. 7 is a schematic structural diagram of a three-dimensional memory device according to a fourth embodiment of the present invention, and as shown in fig. 7, the three-dimensional memory device includes:
a substrate 71;
an isolation layer 72 formed over the substrate 71;
forming a lower stack 73 over the isolation layer 72;
a lower channel hole 731 in the lower stack;
a first silicon oxide-silicon nitride-silicon oxide ONO structure 732 formed in sequence from inside to outside along the sidewall of the lower channel hole;
a second polysilicon layer 74 covering the lower via hole 731;
a first material layer 75 deposited over the polished lower stack;
an upper layer stack 76 deposited over the first material layer 75;
an upper channel hole 761 corresponding to the lower channel hole 731 in the upper stack 76;
a second ONO structure 762 formed from inside to outside along a sidewall of the upper channel hole 761;
a corner portion 763;
a metal layer 764 formed by filling a metal material at the blank layer formed after removing the third material layer.
Here, the material of the substrate 71 may be selected from one of Si, SiGe, SiC, Al2O3, AlN, ZnO, Ga2O3, LiAlO2, LiAlO3, or the like. Since the Si substrate is inexpensive and easy to dope and at the same time is easy to react to form a heterogeneous isolation layer, Si may be selected as the substrate 71 in this embodiment.
The isolation layer 72, which may be a silicon oxide material, functions as the isolation layer 72 to electrically isolate the substrate 71 from the upper structure of the isolation layer 72.
The lower stack 73 is a stack in which insulating layers and semiconductor layers are alternately stacked. The lower stack 73 may be formed in a manner of vertically stacking a plurality of memory cells. For example, the lower laminate 73 may be formed by cyclically stacking the second material layer and the third material layer.
Lower via holes 731, which are vias in the lower stack 73, can be etched using an etching technique until the substrate surface is exposed to form lower via holes 731. Alternatively, the lower via hole 731 may be formed by photolithography, for example, by exposing after covering a photoresist layer, and then etching.
The first ONO structure 732 is formed by sequentially forming a blocking insulating layer, a charge trapping layer, and a tunneling insulating layer in the lower via hole from inside to outside along the sidewall of the lower via hole 731. The blocking insulating layer, the charge trapping layer and the tunneling insulating layer constitute a storage layer of the three-dimensional memory device. The blocking insulating layer may be made of silicon oxide, the charge trapping layer may be made of silicon nitride, and the tunneling insulating layer may be made of silicon oxide, so that the memory layer formed of silicon oxide-silicon nitride-silicon oxide is the first ONO structure 732. Of course, other materials may be selected for each layer of first ONO structure 732, which is not limited in this embodiment.
The second polysilicon layer 74 is formed to cover the lower via hole 731 by filling the lower via hole 731 with a polysilicon material.
The first material layer 75 is the same material as the second material layer.
The upper stack 76, like the lower stack 73, may be formed by vertically stacking a plurality of memory cells. For example, the upper stack 76 may also be formed by cyclically stacking the second material layer and the third material layer. The number of the second material layer and the third material layer can be any number. Multiple layers of second material and third material are alternately stacked sequentially on top of the first material layer 75 using CVD or ALD or other deposition methods.
Upper via holes 761, which are vias in the upper stack 76, as well as the lower via holes 731, can also be etched using an etching technique until the substrate surface is exposed to form the upper via holes 761. Alternatively, the upper channel hole 761 may be formed by photolithography, for example, by exposing after covering a photoresist layer, and then etching.
The second ONO structure 762 is formed by sequentially forming a blocking insulating layer, a charge trapping layer, and a tunneling insulating layer in the upper channel hole along the sidewall of the upper channel hole 761 from inside to outside. The blocking insulating layer, the charge trapping layer and the tunneling insulating layer constitute a storage layer of the three-dimensional memory device. The blocking insulating layer may be made of silicon oxide, the charge trapping layer may be made of silicon nitride, and the tunneling insulating layer may be made of silicon oxide, so that the memory layer formed of silicon oxide-silicon nitride-silicon oxide is the second ONO structure 762. Of course, other materials may be selected for each layer of the second ONO structure 762, which is not limited in this embodiment. In this embodiment, each upper channel hole 761 has a second ONO structure 762.
Corner 763, which is the location where the lower laminate 73 overlaps the upper laminate 76, where corner 763 is in contact with the first material layer 75 or the second material layer, and where corner 763 is not in contact with the third material layer.
The metal layer 764 is formed by filling a metal material in a blank layer formed after the third material layer is removed. Wherein the metal material may be tungsten.
In the three-dimensional memory device provided by the embodiment of the invention, the first material layer or the second material layer, namely silicon oxide, is in contact with the corner part, and the corner part is not in contact with the third material layer, namely is not in contact with silicon nitride. Therefore, in the subsequent step of removing the semiconductor layer (third material layer) and filling the metal layer, the weak region is not formed at the corner portion, and the reliability of the device can be improved.
It should be understood by those skilled in the art that other configurations and functions of the three-dimensional memory device and the method for forming the same according to the embodiments of the present invention are known to those skilled in the art, and are not described in detail in order to reduce redundancy.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example" or "some examples" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims (5)

1. A method of forming a three-dimensional memory device, the method comprising:
filling polysilicon into a lower channel hole along the upper surface of a lower lamination of the three-dimensional memory device so as to deposit a first polysilicon layer on the upper surface of the lower lamination and deposit a second polysilicon layer on the lower channel hole, wherein the lower lamination and the upper lamination are formed by alternately stacking a plurality of second material layers and a plurality of third material layers; the second material layer and the third material layer are different materials;
polishing to remove the first polysilicon layer and the lower lamination layer with the preset thickness;
depositing a first material layer on the polished lower laminate, wherein the first material layer and the second material layer are made of the same material;
depositing the upper stack over the first material layer;
etching the upper lamination to form an upper channel hole corresponding to the lower channel hole, wherein the communication position of the lower channel hole and the upper channel hole is not in contact with the third material layer;
the polishing removes the first polysilicon layer and the lower lamination with the preset thickness, and comprises the following steps:
polishing and removing the first polysilicon layer by adopting a Chemical Mechanical Polishing (CMP) process;
leaving a first layer of a second material adjacent to the upper surface of the lower stack;
if the uppermost layer of the lower lamination layer is the third material layer, polishing and removing the first polycrystalline silicon layer and the uppermost layer of the lower lamination layer by adopting the CMP process;
and if the uppermost layer of the lower laminated layer is the second material layer, polishing and removing the first polycrystalline silicon layer by adopting the CMP process.
2. The method of claim 1, wherein depositing a first material layer over the lapped lower stack comprises:
depositing said first layer of material over said first layer of second material; wherein, the first second material layer and the first material layer are made of the same material.
3. The method of claim 1, wherein prior to filling the lower via hole with polysilicon along an upper surface of the lower stack of the three-dimensional memory device, the method further comprises:
and etching the lower lamination of the three-dimensional memory device to form the lower channel hole.
4. The method of claim 3, wherein after forming the lower channel hole, the method further comprises:
sequentially forming a first silicon oxide-silicon nitride-silicon oxide ONO structure along the side wall of the lower channel hole from inside to outside;
and after the upper channel hole is formed, a second ONO structure is formed along the side wall of the upper channel hole from inside to outside.
5. The method of claim 1, wherein after etching the upper stack to form an upper via hole corresponding to the lower via hole, the method further comprises:
removing the third material layer to form a blank layer;
and filling a metal material in the blank layer to form a metal layer.
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