CN109390302A - Semiconductor structure and its manufacturing method - Google Patents

Semiconductor structure and its manufacturing method Download PDF

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Publication number
CN109390302A
CN109390302A CN201711230971.5A CN201711230971A CN109390302A CN 109390302 A CN109390302 A CN 109390302A CN 201711230971 A CN201711230971 A CN 201711230971A CN 109390302 A CN109390302 A CN 109390302A
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China
Prior art keywords
substrate
conductive
dielectric layer
conductive structure
bare die
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CN201711230971.5A
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Chinese (zh)
Inventor
刘醇鸿
陈宪伟
陈明发
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN109390302A publication Critical patent/CN109390302A/en
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present embodiments relate to semiconductor structure and its manufacturing methods.Some embodiments of the present invention disclose a kind of semiconductor structure, and the semiconductor structure includes substrate, the bare die being placed in above the first surface of the substrate, the RDL being placed in above the second surface of the substrate, the conductive structure being placed in the RDL.The conductive structure is configured as sealing ring, and the sealing ring protects the RDL and the substrate from the damage as caused by crack, fragment or other pollutants during production or simple grain.In this way, the delamination of component or the damage to the semiconductor structure during production or simple grain can be minimized or be prevented.

Description

Semiconductor structure and its manufacturing method
Technical field
The present embodiments relate to semiconductor structure and its manufacturing methods.
Background technique
It is necessary for many modern Applications using the electronic equipment of semiconductor device.With electronic technology into Step, the size of semiconductor device become smaller and smaller while having larger functional and larger amount of integrated circuit.Due to partly leading Body device through miniaturization scale, therefore on substrate, flip on piece covers chip (chip on wafer on substrate) (CoWoS) it is widely used for several integrated chips through through-silicon via (TSV) into single semiconductor device.? During CoWoS is operated, by several chipsets loaded on single semiconductor device.In addition, real in this small semiconductor device Apply numerous manufacturing operations.
However, the manufacturing operation of semiconductor device is related to many steps and behaviour that the semiconductor device small and thin to this carries out Make.Complex is become to the manufacture with the semiconductor device through miniaturization scale.Manufacture the increasing of the complexity of semiconductor device Add the defects of can lead to such as Poor structure configuration, the delamination of component or other problems, is closed so as to cause the height of semiconductor device The loss of lattice rate and the increase of manufacturing cost.In this way, in the presence of the structure for modifying semiconductor device and improving being permitted for manufacturing operation More challenges.
Summary of the invention
In an aspect, the present embodiments relate to a kind of semiconductor structure, the semiconductor structure includes: the first lining Bottom, it includes first surface and the second surfaces opposite with the first surface；Access extends through first substrate； Bare die is placed in above the first surface of first substrate；Redistribution layer RDL is placed in first substrate Above the second surface, and includes dielectric layer above the second surface, is placed in the dielectric layer and is electrically connected to First conductive structure of the access, and the second conductive structure for being placed in the dielectric layer and being electrically isolated with the access； Second substrate, it includes third surface and fourth surfaces opposite with the third surface；And conductive bump, it is placed in described One is bonded between the third surface of second substrate and the RDL and by first conductive structure and second substrate It rises.
Detailed description of the invention
According to the aspect described in detail below that this exposure is best understood read together with attached drawing.It is emphasized that according to work Standard practices in industry, various components are not necessarily drawn to scale.In fact, can arbitrarily increase and add deduct for the sake of discussing clearly The size of small various components.
Fig. 1 is the schematic cross section according to the semiconductor structure of some embodiments of this exposure.
Figure 1A and 1B is with the schematic enlarged view of the second conductive structure of various structures configuration.
Fig. 2 is the diagrammatic top cross-sectional view of the dielectric layer and conductive structure in Fig. 1.
Fig. 3 is the schematic cross section according to the semiconductor structure of some embodiments of this exposure.
Fig. 4 is the diagrammatic top cross-sectional view of the dielectric layer and conductive structure in Fig. 3.
Fig. 5 is the schematic cross section according to the semiconductor structure comprising groove of some embodiments of this exposure.
Fig. 6 is the schematic cross-section according to the semiconductor structure comprising several bare dies of some embodiments of this exposure Figure.
Fig. 7 is the flow chart according to the method for the manufacture semiconductor structure of some embodiments of this exposure.
Fig. 7 A to 7K is the signal that semiconductor structure is manufactured according to the method by Fig. 7 of some embodiments of this exposure Figure.
Specific embodiment
It discloses below and many different embodiments or examples of the different component for implementing provided subject matter is provided.Hereafter The particular instance of component and arrangement is described to simplify this exposure.Certainly, these are only example and are not intended to be restrictive.It lifts Example for, in the de-scription first component is formed above second component or on the second component may include wherein first component and Embodiment that second component is directly contact formed and also may include that wherein additional member can be formed in first component and the second structure The embodiment that be not directly contacted with first component and second component can.In addition, this exposure can weigh in various examples Multiple Ref. No. and/or letter.This repeats to be for simple and clear purpose and not essentially indicate that discussed various realities Apply the relationship between example and/or configuration.
In addition, can herein for be easy to describe and use space relative terms (such as " lower section ", " following ", " lower part ", " above ", " top " etc.) relationship of an element or component and another element or component described, as illustrated in each figure It is bright.The difference in addition to describing orientation in figure that the spatially relative term intends to include device in use or operation is fixed To.Equipment can be oriented in other ways and (be rotated by 90 ° or with other orientations) and therefore can similarly understand used herein Space is opposite to describe language.
Within this document, term " coupling " also may be referred to " being electrically coupled ", and term " connection " can be referred to as " electrical connection "." coupling Conjunction " and " connection " may be used to indicate that two or more element coordination with one another or interaction.
It also may include other components and process.It for example, may include test structure to help to 3D encapsulation or 3DIC dress Set carry out validation test.For example, test structure may include the testing cushion being formed in redistribution layer or on substrate, the substrate Allow to encapsulate 3D or the test of 3DIC, using etc. to probe and/or probe card.It can be to intermediate structure and final structure Execute validation test.In addition, structure disclosed herein and method are in combination with the middle verification being incorporated to known good bare die With increase qualification rate and reduce the test method of cost come using.
Semiconductor chip is manufactured by several operations.During manufacturing process, will have different functionalities and size Semiconductor chip be integrated into individual module.Several semiconductor chips are placed on above substrate and then through simple grain to become For semiconductor device.After simple grain, some fragments or some cracking initiations are removed from semiconductor chip at once and is expanded to In semiconductor chip.Fragment and crack will cause structural failure to semiconductor chip.
In this exposure, a kind of semiconductor structure is disclosed.The semiconductor structure includes the first surface for being placed in substrate The bare die of top, be placed in above the second surface of substrate redistribution layer (RDL) and the conductive bump that is placed in above RDL.It leads Electric structure is placed in RDL, extends, along the edge of RDL around the component and interconnection being placed on RDL and substrate or in it Part, and sealing ring is configured as to protect RDL and substrate from by crack, fragment or other pollutions during production or simple grain Damage caused by object.In this way, the delamination of component can be minimized or be prevented during production or simple grain or to semiconductor structure Damage.
Fig. 1 is the schematic cross section according to the semiconductor structure 100 of the various embodiments of this exposure.In some implementations In example, semiconductor structure 100 includes the first substrate 101, access 102, bare die 103 and redistribution layer (RDL) (107,108).
In some embodiments, semiconductor structure 100 is semiconductor packages.In some embodiments, semiconductor structure 100 It is that integrated be fanned out to (InFO) is encapsulated, wherein the I/O terminal of bare die 103 is fanned out to and is redistributed with larger area in bare die 103 Surface.In some embodiments, semiconductor structure 100 is that flip on piece covers chip (CoWoS) encapsulating structure on substrate. In some embodiments, semiconductor structure 100 is system integrated chip (system on integrated chips) (SoIC) Encapsulating structure.In some embodiments, semiconductor structure 100 is three dimensional integrated circuits (3D IC).
In some embodiments, the first substrate 101 is semiconductive substrate.In some embodiments, the first substrate 101 includes Semiconductive material, such as silicon, germanium, gallium, arsenic or combinations thereof.In some embodiments, the first substrate 101 is intermediary layer etc..? In some embodiments, the first substrate 101 is silicon substrate or silicon intermediary layer.In some embodiments, the first substrate 101 including, for example, Ceramics, glass, polymer etc. material.In some embodiments, the first substrate 101 includes organic material.In some embodiments In, the first substrate 101 has quadrangle, rectangle, square, polygon or any other suitable shape.
In some embodiments, the first substrate 101 includes first surface 101a and opposite with first surface 101a second Surface 101b.In some embodiments, access 102 is placed in the first substrate 101.In some embodiments, access 102 extends Across the first substrate 101.In some embodiments, access 102 extends the first surface 101a and the second table of the first substrate 101 Between the 101b of face.In some embodiments, access 102 includes conductive material, such as copper, silver, gold, aluminium etc..In some embodiments In, access 102 is through substrate access or through-silicon via (TSV).In some embodiments, between two neighbouring accesses away from From for about 40um to about 70um.In some embodiments, the distance between two neighbouring accesses are about 60um.In some embodiments In, the width of access 102 is about 8um to about 15um.In some embodiments, the width of access 102 is about 10um.
In some embodiments, conductive pad 102a is placed in 102 top of access.In some embodiments, conductive pad 102a It is electrically connected to access 102.In some embodiments, conductive pad 102a is placed in above the first surface 101a of the first substrate 101. In some embodiments, conductive pad 102a is surround by the first substrate 101.In some embodiments, conductive pad 102a includes conduction Material, such as chromium, copper, gold, titanium, silver, nickel, palladium or tungsten etc..In some embodiments, conductive pad 102a is solderable surface and use Act on the platform for receiving conductive structure.
In some embodiments, bare die 103 is placed in 101 top of the first substrate.In some embodiments, bare die 103 is put It is placed in above the first surface 101a of the first substrate 101.In some embodiments, bare die 103 is made as having in bare die 103 There is predetermined function circuit.In some embodiments, bare die 103 by mechanical or laser knife from semiconductive wafer by simple grain Change.In some embodiments, bare die 103 includes a variety of circuits suitable for specific application.In some embodiments, circuit packet Containing various devices, such as transistor, capacitor, resistor, diode and/or similar device.In some embodiments, bare die 103 it is logic device bare die, graphics processing unit (GPU) bare die, deposits using processing (AP) bare die, memory die, high bandwidth Reservoir (HBM) bare die etc..In some embodiments, bare die 103 is chip or encapsulation.In some embodiments, bare die 103 has Have in quadrangle, rectangular or square shape top cross section (cross section of the top view from semiconductor structure 100, such as It is demonstrated in Figure 1).
In some embodiments, bare die 103 is comprising front side 103a, the rear side 103b opposite with front side 103a and between front side Side wall 103c between 103a and rear side 103b.In some embodiments, side wall 103c be generally orthogonal to front side 103a or after Side 103b.In some embodiments, front side 103a is several electrical components master end placed thereon.In some embodiments, Rear side 103b is the non-active side there is no electrical component placed thereon.
In some embodiments, the first conductive bump 104 is placed between the first substrate 101 and bare die 103.In some realities It applies in example, the first conductive bump 104 is placed between the front side 103a of bare die 103 and the first surface 101a of the first substrate 101. In some embodiments, bare die 103 is bonded together by the first conductive bump 104 and the first substrate 101.In some implementations In example, the first conductive bump 104 is electrically connected to access 102.In some embodiments, the first conductive bump 104 and access 102 or Conductive pad 102a is bonded together.
In some embodiments, the first conductive bump 104 is cylindrical, spherical or hemispherical shape.In some embodiments In, the first conductive bump 104 is solder joints, solder projection, soldered ball, ball grid array (BGA) ball, controlled collapse chip connection (C4) convex block, dimpling block etc..In some embodiments, the first conductive bump 104 is conductive column or column.In some implementations In example, the first conductive bump 104 includes metal, such as lead, tin, copper, gold, nickel etc..In some embodiments, two neighbouring first The distance between conductive bump 104 is about 150um to about 200um.In some embodiments, two neighbouring first conductive bumps The distance between 104 be about 180um.
In some embodiments, the first primer material 105 is placed in 101 top of the first substrate and around the first conductive bump 104 and bare die 103.In some embodiments, the first primer material 105 is placed on the first surface 101a of the first substrate 101 Side.In some embodiments, the first primer material 105 is encapsulated the first conductive bump 104.In some embodiments, the first primer material Material 105 is contacted with the side wall 103c of the first surface 101a of the first substrate 101, the front side 103a of bare die 103 and bare die 103.? In some embodiments, a part of side wall 103c is covered by the first primer material 105.In some embodiments, the first primer material Interval between 105 filling of material, two neighbouring first conductive bumps 104.In some embodiments, the first primer material 105 is to use In the adhesive that is electrically insulated for protecting the engagement between the first conductive bump 104 or fixed bare die 103 and the first substrate 101.One In a little embodiments, the first primer material 105 includes epoxy resin, resin, epoxy molding material etc..
In some embodiments, molded 106 is placed in 101 top of the first substrate and around bare die 103.In some implementations In example, molded 106 is placed in above the first surface 101a of the first substrate 101 and around bare die 103, the first primer material 105 and first conductive bump 104.In some embodiments, side wall 103c, the first primer material of molded 106 and bare die 103 105 and first substrate 101 first surface 101a contact.In some embodiments, the rear side 103b of bare die 103 is from molded 106 exposures.In some embodiments, molded 106 can be monofilm or composite stack.In some embodiments, molded 106 Include a variety of materials, such as moulding compound, molding primer, epoxy resin, resin etc..In some embodiments, molded 106 has There are high-termal conductivity, low moisture absorption rate and high flexural strength.
In some embodiments, RDL (107,108) is placed in above the second surface 101b of the first substrate 101.Some In embodiment, RDL (107,108) is configured to circuit paths of the rewiring from bare die 103 and redistributes bare die 103 I/O terminal.In some embodiments, RDL (107,108) includes and is placed in above the second surface 101b of the first substrate 101 Dielectric layer 107 and the several conductive structures 108 being placed in dielectric layer 107.
In some embodiments, dielectric layer 107 is contacted with the second surface 101b of the first substrate 101.In some embodiments In, dielectric layer 107 includes several layers (107a, 107b, 107c, 107d) that self is stacked.Although Fig. 1 shows dielectric layer 107 include 4 dielectric layers (107a, 107b, 107c, 107d), it will be understood that, dielectric layer 107 is not limited to comprising 4 dielectric layers (107a,107b,107c,107d).Dielectric layer 107 can include one or more of dielectric layer.
In some embodiments, dielectric layer 107 includes polymeric material.In some embodiments, dielectric layer 107 includes polyamides Imines (PI), polybenzoxazoles (PBO) etc..In some embodiments, dielectric layer 107 includes polyimides (PI), can be Solidify under low temperature (that is, being substantially below about 400 DEG C or in the range of about 200 DEG C to 300 DEG C).In some embodiments, it is situated between Electric layer 107 includes polybenzoxazoles (PBO), can be solidified under high temperature (that is, being substantially greater than about 400 DEG C).In some implementations In example, each layer (107a, 107b, 107c, 107d) in dielectric layer 107 includes different from each other or identical dielectric material.? In some embodiments, dielectric layer 107 is transparent or can be penetrated by visible light.
In some embodiments, dielectric layer 107 with a thickness of about 20um to about 50um.In some embodiments, dielectric layer 107 with a thickness of about 30um to 40um.In some embodiments, a layer in dielectric layer 107 (107a, 107b, 107c, 107d) with a thickness of about 3um to about 13um.In some embodiments, a layer in dielectric layer 107 (107a, 107b, 107c, 107d) with a thickness of about 5um to about 8um.In some embodiments, a layer in dielectric layer 107 (107a, 107b, 107c, 107d) with a thickness of about 7um.
In some embodiments, conductive structure 108 is placed in dielectric layer 107.In some embodiments, conductive structure 108 include conductive material, such as gold, silver, copper, nickel, tungsten, aluminium, tin and/or its alloy.In some embodiments, conductive structure 108 extend through one or more layers (107a, 107b, 107c, 107d) in dielectric layer 107.In some embodiments, conductive knot Structure 108 includes the first conductive structure 108a and the second conductive structure 108b.
In some embodiments, the first conductive structure 108a is placed in dielectric layer 107 and is electrically connected to access 102.? In some embodiments, the first conductive structure 108a is placed in the central portion of dielectric layer 107.In some embodiments, first Conductive structure 108a is electrically connected to access 102.In some embodiments, the first conductive structure 108a is electrically connected by access 102 It is connected to bare die 103.In some embodiments, the first conductive structure 108a extends through at least one of dielectric layer 107 layer.? In some embodiments, the distance between the edge (or edge of RDL 107,108) of the first conductive structure 108a and dielectric layer 107 D2 is about 100um to about 130um.In some embodiments, distance D2 is about 110um.
In some embodiments, the first conductive structure 108a includes the first welding section (land) part 108a-1 and with first The first passage portion 108a-2 that welding section part 108a-1 is coupled.In some embodiments, the first welding section part 108a-1 is laterally extended in dielectric layer 107.In some embodiments, the first passage portion 108a-2 is extended vertically in dielectric layer In 107 and pass through at least one of dielectric layer 107 layer.In some embodiments, the first welding section part 108a-1 and first Passage portion 108a-2 is stacked self.In some embodiments, the first welding section part 108a-1 and the first passage portion 108a-2 is alternately stacked.
In some embodiments, the second conductive structure 108b is placed in dielectric layer 107 and is electrically isolated with access 102.? In some embodiments, the second conductive structure 108b is placed adjacent to the edge of dielectric layer 107.In some embodiments, second Conductive structure 108b is placed adjacent to the first conductive structure 108a.In some embodiments, the second conductive structure 108b extends Across at least one of dielectric layer 107 layer.In some embodiments, the second conductive structure 108b and bare die 103 are electrically isolated.? In some embodiments, the second conductive structure 108b is dummy structures.In some embodiments, the second conductive structure 108b is sealing Ring and it is configured as barrier, the barrier after simple grain or sawing operation for preventing pollutant (such as fragment, wet Gas, chemicals, Corrosive Materia etc.) it is penetrated into semiconductor structure 100 or dielectric layer 107 and prevents crack from expanding to semiconductor In structure 100 or dielectric layer 107.
In some embodiments, the second conductive structure 108b extends along the edge of dielectric layer 107, as shown in FIG. 2. In some embodiments, the second conductive structure 108b is extended to surround the first conductive structure 108a.In some embodiments, The top cross section of two conductive structure 108b is in band or frame shape.In some embodiments, pass through dielectric under visible light Layer 107 and visible second conductive structure 108b.
In some embodiments, the width W1 of the second conductive structure 108b is about 30um to about 70um.In some embodiments In, width W1 is about 50um.In some embodiments, the distance between the edge of dielectric layer 107 and the second conductive structure 108b D1 is generally less than the distance between edge and the first conductive structure 108a of dielectric layer 107 D2.In some embodiments, distance D1 is about 35um to about 55um.In some embodiments, distance D1 is about 45um.In some embodiments, the first conductive structure The distance between 108a and the second conductive structure 108b D3 are about 15um to about 30um.In some embodiments, distance D3 is about 20um。
In some embodiments, the second conductive structure 108b include the second welding section part 108b-1 and with the second welding section The alternate path part 108b-2 that part 108b-1 is coupled.In some embodiments, the second welding section part 108b-1 It is laterally extended in dielectric layer 107.In some embodiments, alternate path part 108b-2 is extended vertically in dielectric layer 107 And pass through at least one of dielectric layer 107 layer.In some embodiments, the second welding section part 108b-1 and alternate path portion 108b-2 is divided self to stack.In some embodiments, the second welding section part 108b-1 and alternate path part 108b-2 It is alternately stacked.In some embodiments, 102 electricity of the second welding section part 108b-1 and alternate path part 108b-2 and access Isolation.
In some embodiments, the second conductive structure 108b is configured with various structures, as shown in Figure 1A and 1B.? In some embodiments, the second conductive structure 108b includes to be laterally extended layer (107a, 107b, a 107c in dielectric layer 107 Or 107d) above several second welding sections part 108b-1, and from layer (107a, 107b, 107c in dielectric layer 107 Or 107d) in the vertically extending several alternate path part 108b-2 of one of the second welding section part 108b-1.
In some embodiments, passage portion 108b-2 is in along layer (107a, 107b, 107c in dielectric layer 107 Or 107d) extend various length.In some embodiments, a layer in dielectric layer 107 (107a, 107b, 107c or The length L1 of passage portion 108b-2 in 107d) is about 10um to about 15um.In some embodiments, length L1 is about 14um.In some embodiments, the length L2 between passage portion 108b-2 and the edge of dielectric layer 107 is about 45um to about 50um.In some embodiments, length L2 is about 48um.In some embodiments, passage portion 108b-2 and first is conductive ties Length L3 between structure 108a is about 25um to about 30um.In some embodiments, length L3 is about 27um.In some embodiments In, welding section part 108b-1 from passage portion 108b-2 length L4 outstanding be about 25um to about 30um.In some embodiments In, length L4 is about 28um.In some embodiments, length L4 is about 5um to about 15um.In some embodiments, length L4 It is about 10um.In some embodiments, length L4 is about 7um.In some embodiments, length L4 is about 1um to about 5um.? In some embodiments, length L4 is about 3um.
In some embodiments, barrier layer 109 is placed between the first substrate 101 and dielectric layer 107.In some embodiments In, barrier layer 109 is configured to that conductive structure 108 is prevented to be diffused into the first substrate 101.In some embodiments, barrier layer 109 surround a part of access 102.In some embodiments, barrier layer 109 is placed in the first substrate 101 and the second conductive knot Between structure 108b.In some embodiments, the second conductive structure 108b is contacted with barrier layer 109.In some embodiments, second Conductive structure 108b is separated by barrier layer 109 with the first substrate 101.In some embodiments, barrier layer 109 includes nitridation Object.In some embodiments, barrier layer 109 includes nitride, can be solidified under low temperature (that is, substantially below 400 DEG C).
In some embodiments, RDL (107,108) is placed in 112 top of the second substrate.In some embodiments, second Substrate 112 makes on it predetermined function circuit.In some embodiments, the second substrate 112 includes to be placed in the second substrate Several conductive traces and several electrical components, such as transistor, diode in 112 etc..In some embodiments, the second substrate 112 include semiconductive material, such as silicon, germanium, gallium, arsenic or combinations thereof.In some embodiments, the second substrate 112 including, for example, Ceramics, glass, polymer etc. material.In some embodiments, the second substrate 112 is silicon substrate.In some embodiments, Two substrates 112 are printed circuit board (PCB).In some embodiments, the second substrate 112 have quadrangle, rectangle, square, Polygon or any other suitable shape.
In some embodiments, the second substrate 112 includes third surface 112a and the opposite with third surface 112a the 4th Surface 112b.In some embodiments, third surface 112a is towards dielectric layer 107.In some embodiments, (107,108) RDL It is placed between the first substrate 101 and the second substrate 112.In some embodiments, dielectric layer 107, the first conductive structure 108a And second conductive structure 108b be placed between the first substrate 101 and the second substrate 112.
In some embodiments, connector 113 is placed in above the 4th surface 112b of the second substrate 112.In some realities It applies in example, connector 113 is configured to be engaged in another substrate or encapsulation top and by the circuit of the second substrate 112 and another lining The electrical connection of the circuit of bottom or encapsulation.In some embodiments, connector 113 is solder joints, solder projection, soldered ball, ball bar battle array Arrange (BGA) ball, controlled collapse chip connection (C4) convex block, dimpling block, conductive column, column etc..In some embodiments, even Connecing device 113 includes metal, such as lead, tin, copper, gold, nickel etc..
In some embodiments, the second conductive bump 110 is placed between the second substrate 112 and RDL (107,108).? In some embodiments, the second conductive bump 110 is placed between the third surface 112a and dielectric layer 107 of the second substrate 112.? In some embodiments, the second conductive bump 110 is placed in above the first conductive structure 108a.In some embodiments, it first leads Electric structure 108a is bonded together by the second conductive bump 110 and the second substrate 112.In some embodiments, the second lining The circuit at bottom 112 passes through the second conductive bump 110,104 electricity of the first conductive structure 108a, access 102 and the first conductive bump It is connected to bare die 103.
In some embodiments, be placed in the second conductive bump 110 above the second conductive structure 108b be there is no. In some embodiments, the second conductive bump 110 and the second conductive structure 108b are electrically isolated.In some embodiments, it second leads Electric convex block 110 is separated with the second conductive structure 108b and is not contacted with the second conductive structure 108b.In some embodiments, second Conductive component 108b and access 102, the second conductive bump 110 and the first conductive structure 108a are electrically isolated.In some embodiments, RDL (107,108) is placed between access 102 and the second conductive bump 110.
In some embodiments, the second conductive bump 110 is cylindrical, spherical or hemispherical shape.In some embodiments In, the second conductive bump 110 is solder joints, solder projection, soldered ball, ball grid array (BGA) ball, controlled collapse chip connection (C4) convex block, dimpling block etc..In some embodiments, the second conductive bump 110 is conductive column or column.In some implementations In example, the second conductive bump 110 includes metal, such as lead, tin, copper, gold, nickel etc..
In some embodiments, the second primer material 111 be placed in the top of the second substrate 112 and around the first substrate 101, RDL (107,108) and the second conductive bump 110.In some embodiments, the second primer material 111 is placed in the second substrate 112 Third surface 112a above.In some embodiments, the second primer material 111 is encapsulated the second conductive bump 110.In some realities It applies in example, the third surface of the side wall of the second primer material 111 and the first substrate 101, dielectric layer 107 and the second substrate 112 112a contact.In some embodiments, a part of the third surface 112a of the second substrate 112 is sudden and violent from the second primer material 111 Dew.In some embodiments, a part of the side wall of the first substrate 101 is covered by the second primer material 111.In some embodiments In, the second primer material 111 fills the interval between two neighbouring second conductive bumps 110.In some embodiments, the second bottom Glue material 111 is for protecting the second conductive bump 110 or fixing between the first substrate 101 and the second substrate 112 or dielectric The adhesive that is electrically insulated of engagement between layer 107 and the second substrate 112.In some embodiments, the second primer material 111 includes Epoxy resin, resin, epoxy molding material etc..
In some embodiments, reinforcer 115 is placed in above the third surface 112a of the second substrate 112 and around molding Object 106, the first substrate 101 and the second primer material 111.In some embodiments, reinforcer is placed in 106 top of molded. In some embodiments, reinforcer 115 is circular in configuration.
In some embodiments, device 116 is placed in above the third surface 112a of the second substrate 112.In some implementations In example, device 116 is placed between the second primer material 111 and reinforcer 115.In some embodiments, device 116 is surface Mounting device (SMD).
Fig. 3 is the schematic cross section according to the semiconductor structure 200 of the various embodiments of this exposure.In some implementations In example, semiconductor structure 200 includes to have and the first substrate of similar configuration illustrated in described above or Fig. 1 101, access 102, bare die 103, the first conductive bump 104, the first primer material 105, molded 106, RDL (107,108), resistance Barrier layer 109, the second conductive bump 110, the second primer material 111, the second substrate 112 and connector 113.
In some embodiments, RDL (107,108) includes two second placed adjacent to the edge of dielectric layer 107 Conductive structure 108b.In some embodiments, one of two second conductive structure 108b are placed in the first conductive structure Between the other of 108a and two second conductive structure 108b.In some embodiments, two the second conductive structure 108b It is electrically isolated with access 102, the second conductive bump 110 and the first conductive structure 108a.Although illustrating two second in Fig. 3 Conductive structure 108b, it will be understood that, one or more second conductive structure 108b may be included in dielectric layer 107.In some implementations In example, two the second conductive structure 108b have and the second conductive structure 108b illustrated in described above or Fig. 1 Similar configuration.
In some embodiments, two the second conductive structure 108b extend along the edge of dielectric layer 107, such as institute in Fig. 4 It shows.In some embodiments, two the second conductive structure 108b are extended to surround the first conductive structure 108a.In some realities It applies in example, the top cross section of two the second conductive structure 108b is in band or frame shape.In some embodiments, visible Pass through 107 visible two the second conductive structure 108b of dielectric layer under light.In some embodiments, two the second conductive structures The distance between 108b D4 is about 8um to about 15um.In some embodiments, distance D4 is about 12um.
Fig. 5 is the schematic cross section according to the semiconductor structure 300 of the various embodiments of this exposure.In some implementations In example, semiconductor structure 300 includes with first with similar configuration illustrated in described above or Fig. 1 or 3 Substrate 101, access 102, bare die 103, the first conductive bump 104, the first primer material 105, molded 106, RDL (107, 108), barrier layer 109, the second conductive bump 110, the second primer material 111, the second substrate 112 and connector 113.
In some embodiments, groove 107e is placed in 107 top of dielectric layer.In some embodiments, groove 107e court It is recessed into dielectric layer 107 to the first substrate 101.In some embodiments, groove 107e is from dielectric layer towards the first substrate 101 second surface 101b is recessed into.In some embodiments, groove 107e is configured to production or single granulating operation rear defence Only fragment damages dielectric layer 107 or semiconductor structure 300 or prevents crack from expanding to dielectric layer 107 or semiconductor structure 300 In.In some embodiments, groove 107e is used as crack arrester (crack stopper).In some embodiments, groove 107e is adjacent It is bordering on the second conductive structure 108b and places.In some embodiments, between groove 107e and the second conductive structure 108b away from From being generally less than the distance between groove 107e and the first conductive structure 108a.In some embodiments, the width of groove 107e Degree is about 30um to about 50um.In some embodiments, groove 107e is about 40um.
Fig. 6 is the schematic cross section according to the semiconductor structure 400 of the various embodiments of this exposure.In some implementations In example, semiconductor structure 400 includes with the with similar configuration illustrated in described above or Fig. 1,3 or 5 One substrate 101, access 102, bare die 103, the first conductive bump 104, the first primer material 105, molded 106, RDL (107, 108), barrier layer 109, the second conductive bump 110, the second primer material 111, the second substrate 112 and connector 113.
In some embodiments, semiconductor structure 400 includes the second bare die 114 placed adjacent to bare die 103.One In a little embodiments, the second bare die 114 is placed in above the first surface 101a of the first substrate 101.In some embodiments, second Bare die 114 is made as having predetermined function circuit in the second bare die 114.In some embodiments, the second bare die 114 passes through Mechanical or laser knife and be granulated from semiconductive wafer coverlet.In some embodiments, the second bare die 114 includes suitable for spy Surely a variety of circuits applied.In some embodiments, circuit includes various devices, such as transistor, capacitor, resistor, two Pole pipe and/or similar device.In some embodiments, the second bare die 114 is high bandwidth memory (HBM) bare die etc..One In a little embodiments, the second bare die 114 is chip or encapsulation.In some embodiments, it is in quadrangle, square that the second bare die 114, which has, The top cross section (cross section of the top view from semiconductor structure 400, as illustrated in figure 6) of shape or square shape.
In some embodiments, after the second bare die 114 is comprising the second front side 114a, opposite with the second front side 114a second Side 114b.In some embodiments, the second front side 114a is several electrical components master end placed thereon.In some embodiments In, the second rear side 114b is the non-active side there is no electrical component placed thereon.In some embodiments, the second rear side 114b is exposed from molded 106.
In this exposure, a kind of method for manufacturing semiconductor structure (100,200,300,400) is also disclosed.In some implementations In example, semiconductor structure (100,200,300,400) are formed by method 500.Method 500 include several operation and description and Illustrate the limitation for not being considered as the sequence of operation.Fig. 7 is the method for manufacturing semiconductor structure (100,200,300,400) 500 embodiment.Method 500 includes several operations (501,502,503,504,505,506 and 507).
In operation 501, the first substrate 101 is provided or receives, as shown in Fig. 7 A.In some embodiments, first Substrate 101 includes the first surface 101a and second surface 101b opposite with first surface 101a.In some embodiments, first Substrate 101 is intermediary layer.In some embodiments, the first substrate 101 has and institute in described above or Fig. 1,3,5 or 6 The similar configuration of the first substrate illustrated.
In some embodiments, access 102 is formed in the first substrate 101.In some embodiments, access 102 extends Across the first substrate 101.In some embodiments, access 102 extends the first surface 101a and the second table of the first substrate 101 Between the 101b of face.In some embodiments, access 102 is through substrate access or through-silicon via (TSV).In some embodiments In, access 102 is formed by following operation: removing a part of the first substrate 101 to form opening and then by conduction material Material is placed into opening to form access 102.In some embodiments, to the removal of the part of the first substrate 101 include photoetching, Etching or any other suitable operation.It in some embodiments, include sputter, plating or any other to the placement of conductive material It is suitble to operation.In some embodiments, conductive material includes copper, silver, gold, aluminium etc..In some embodiments, access 102 has The configuration similar with access illustrated in described above or Fig. 1,3,5 or 6.
In some embodiments, conductive pad 102a is formed in 102 top of access.In some embodiments, conductive pad 102a It is formed in above the first surface 101a of the first substrate 101.In some embodiments, conductive pad is formed by following operation 102a: remove the first substrate 101 a part with expose access 102 and above access 102 formed opening parallel connection will be conductive Material is placed into opening to form conductive pad 102a.In some embodiments, it is logical with exposure to remove the part of the first substrate 101 Road 102 includes photoetching, etching or any other suitable operation.In some embodiments, conductive material is placed on access 102 Side includes sputter, plating or any other suitable operation.In some embodiments, conductive material include chromium, copper, gold, titanium, silver, Nickel, palladium or tungsten etc..In some embodiments, conductive pad 102a has and illustrates in described above or Fig. 1,3,5 or 6 The similar configuration of bright conductive pad.
In some embodiments, barrier layer 109 is placed in above the second surface 101b of the first substrate 101.In some realities It applies in example, barrier layer 109, which is configured, prevents conductive material to be diffused into the first substrate 101.In some embodiments, barrier layer 109 surround a part of access 102.In some embodiments, barrier layer 109 passes through spin coating, deposition, chemical vapor deposition (CVD) or it is any other it is suitable operation and place.In some embodiments, barrier layer 109 includes nitride.In some embodiments In, barrier layer 109 solidifies at a predetermined temperature.In some embodiments, predetermined temperature is substantially below 400 DEG C.In some realities It applies in example, barrier layer 109 solidifies at about 200 DEG C to about 300 DEG C.In some embodiments, barrier layer 109 is at about 250 DEG C Solidification.
In operation 502, bare die 103 is placed above the first substrate 101, as shown in Fig. 7 B.In some embodiments In, bare die 103 is placed in above the first surface 101a of the first substrate 101.In some embodiments, bare die 103 includes front side 103a, the rear side 103b opposite with front side and the side wall 103c for being generally orthogonal to front side 103a and rear side 103b.Some In embodiment, bare die 103 is logic device bare die, graphics processing unit (GPU) bare die, using processing (AP) bare die, memory Bare die, high bandwidth memory (HBM) bare die etc..In some embodiments, bare die 103 is chip or encapsulation.In some implementations In example, bare die 103 has the configuration similar with bare die illustrated in described above or Fig. 1,3,5 or 6.
In some embodiments, the first conductive bump 104 is placed in above the front side 103a of bare die 103.In some implementations In example, cream (pasting), silk-screen printing or any other suitable operation are applied by falling sphere (ball dropping), solder and put Set the first conductive bump 104.In some embodiments, the first conductive bump 104 is solder joints, solder projection, soldered ball, ball bar Array (BGA) ball, controlled collapse chip connection (C4) convex block, dimpling block etc..In some embodiments, the first conductive bump 104 be conductive column or column.In some embodiments, the first conductive bump 104 has and described above or Fig. 1,3,5 Or the similar configuration of illustrated first conductive bump in 6.
In some embodiments, bare die 103 is engaged in 101 top of the first substrate by the first conductive bump 104.One In a little embodiments, the first conductive bump 104 is bonded together with access 102 or conductive pad 102a.In some embodiments, bare die 103 are electrically connected to access 102 by the first conductive bump 104.In some embodiments, the first conductive bump 104 is being placed By reflow after above access 102 or the first conductive pad 102a.
In some embodiments, the first primer material 105 is placed in 101 top of the first substrate and in the placement of bare die 103 Later around the first conductive bump 104 and bare die 103, as shown in Fig. 7 C.In some embodiments, the first primer material 105 surround a part of bare die 103 and the first conductive bump 104 and cover one of the first surface 101a of the first substrate 101 Point.In some embodiments, the first primer material 105 fills the gap between neighbouring first conductive bump 104.In some implementations In example, the first primer material 105 is placed by flowing, injection or any other suitable operation.In some embodiments, first Primer material 105 has and the first primer material illustrated in described above or Fig. 1,3,5 or 6 is similar matches It sets.
In some embodiments, molded 106 is formed in 101 top of the first substrate and the ring after the placement of bare die 103 Around bare die 103, as shown in Fig. 7 C.In some embodiments, molded 106 is formed to surround bare die 103 and the first bottom Glue material 105.In some embodiments, a part of the side wall 103c of molded 106 and bare die 103, the first primer material 105 And first substrate 101 first surface 101a contact.In some embodiments, molded 106 by transfer formation, project at Type, it is overmolded or it is any other it is suitable operation and formed.In some embodiments, the rear side 103b of bare die 103 is from molded 106 exposures.In some embodiments, molded 106 is polished to expose the rear side 103b of bare die 103.In some embodiments, Molded 106 is ground and milling, planarizing, chemically-mechanicapolish polish (CMP) or any other suitable operation.In some realities It applies in example, molded 106 includes a variety of materials, such as moulding compound, molding primer, epoxy resin, resin etc..In some implementations In example, molded 106 has the configuration similar with molded illustrated in described above or Fig. 1,3,5 or 6.
In operation 503, dielectric layer 107 is placed above the first substrate 101, as shown in Fig. 7 D.In some implementations In example, dielectric layer 107 is placed in above the second surface 101b of the first substrate 101.In some embodiments, dielectric layer 107 is put It is placed in 109 top of barrier layer.In some embodiments, barrier layer 109 is placed between the first substrate 101 and dielectric layer 107.? In some embodiments, dielectric layer 107 passes through spin coating, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), highly dense It spends plasma CVD (HDPCVD) or any other suitable operation and is deposited.In some embodiments, dielectric layer 107 includes Polyimides (PI), polybenzoxazoles (PBO) etc..In some embodiments, dielectric layer 107 solidifies at a predetermined temperature.? In some embodiments, predetermined temperature is substantially below about 400 DEG C.In some embodiments, predetermined temperature is about 200 DEG C to 300 ℃.In some embodiments, predetermined temperature is about 250 DEG C.In some embodiments, predetermined temperature is to be substantially greater than about 400 ℃。
In some embodiments, dielectric layer 107 include self stack several layers (107a, 107b, 107c, 107d).In some embodiments, the second layer 107b of dielectric layer 107 is placed in above the first layer 107a of dielectric layer 107, and The third layer of dielectric layer 107 is placed in above second layer 107b, and the 4th layer of 107d of dielectric layer 107 is placed in third layer Above 107c.In some embodiments, each layer (107a, 107b, 107c, 107d) in dielectric layer 107 includes different from each other Or identical dielectric material.In some embodiments, dielectric layer 107 has and is schemed in described above or Fig. 1,3,5 or 6 Solve the similar configuration of the dielectric layer of explanation.
In operation 504, the first conductive structure 108a and the second conductive structure 108b is formed in dielectric layer 107, is such as schemed It is shown in 7E or 7F.In some embodiments, by remove dielectric layer 107 a part with formed opening and then will be conductive Material is placed into opening and forms the first conductive structure 108a and the second conductive structure 108b.In some embodiments, to Jie The removal of the part of electric layer 107 includes photoetching, etching or any other suitable operation.In some embodiments, to conductive material Placement include sputter, plating or any other suitable operation.In some embodiments, conductive material includes copper, silver, gold, aluminium Deng.In some embodiments, the first conductive structure 108a and the second conductive structure 108b are simultaneously or separately formed.In some realities It applies in example, the first conductive structure 108a and the second conductive structure 108b have and schemed in described above or Fig. 1,3,5 or 6 Solve the first conductive structure of explanation and the configuration that the second conductive structure is similar.
In some embodiments, the first conductive structure 108a is formed in 102 top of access and is electrically connected to access 102.? In some embodiments, the first conductive structure 108a is electrically connected to bare die 103 by the first conductive bump 104 and access 102.? In some embodiments, the first conductive structure 108a is formed in the central portion of dielectric layer 107.In some embodiments, first Conductive structure 108a extends through at least one of dielectric layer 107 layer.
In some embodiments, the first conductive structure 108a include the first welding section part 108a-1 and with the first welding section The first passage portion 108a-2 that part 108a-1 is coupled.In some embodiments, the first conductive structure 108a passes through It operates and is formed below: placing the first layer 107a of dielectric layer 107, remove a part of first layer 107a to form opening, incite somebody to action Conductive material is placed into opening to form the first welding section part 108a-1 or the first passage portion 108a-2, place dielectric layer 107 second layer 107b, a part of second layer 107b is removed to form opening and conductive material is placed into opening with shape At the first welding section part 108a-1 or the first passage portion 108a-2.In some embodiments, the first welding section part 108a- 1 and first passage portion 108a-2 self stack.In some embodiments, the first welding section part 108a-1 and first is logical Road part 108a-2 is alternately stacked.
In some embodiments, the second conductive structure 108b is formed in 109 top of barrier layer.In some embodiments, Two conductive structure 108b and access 102 are electrically isolated.In some embodiments, the second conductive structure 108b and the first conductive structure 108a is electrically isolated.In some embodiments, the second conductive structure 108b is placed far from the first conductive structure 108a.In some realities It applies in example, the second conductive structure 108b is formed adjacent to the edge of dielectric layer 107.In some embodiments, the second conductive knot Structure 108b extends through at least one of dielectric layer 107 layer.
In some embodiments, the second conductive structure 108b include the second welding section part 108b-1 and with the second welding section The alternate path part 108b-2 that part 108b-1 is coupled.In some embodiments, the second conductive structure 108b passes through It operates and is formed below: placing the first layer 107a of dielectric layer 107, remove a part of first layer 107a to form opening, incite somebody to action Conductive material is placed into opening to form the second welding section part 108b-1 or alternate path part 108b-2, place dielectric layer 107 second layer 107b, a part of second layer 107b is removed to form opening and conductive material is placed into opening with shape At the second welding section part 108b-1 or alternate path part 108b-2.In some embodiments, the second welding section part 108b- 1 and alternate path part 108b-2 is stacked self.In some embodiments, the second welding section part 108b-1 and second is logical Road part 108b-2 is alternately stacked.
In some embodiments, two the second conductive structure 108b are formed, as shown in Fig. 7 F.In some embodiments In, two the second conductive structure 108b are formed adjacent to the edge of dielectric layer 107.In some embodiments, it leads for two second Electric structure 108b and access 102 and the first conductive structure 108a are electrically isolated.In some embodiments, two the second conductive structures 108b is simultaneously or separately formed.
In some embodiments, groove 107e is formed in 107 top of dielectric layer, as shown in Fig. 7 G.In some implementations In example, groove 107e is recessed into dielectric layer 107 towards the first substrate 101.In some embodiments, groove 107e is configured To prevent fragment damage dielectric layer 107 or semiconductor structure 300 after production or single granulating operation or prevent crack from expanding to In dielectric layer 107 or semiconductor structure 300.In some embodiments, groove 107e is put adjacent to the second conductive structure 108b It sets.In some embodiments, dielectric layer 107 is a part of removed to form groove 107e.In some embodiments, groove 107e is formed by etching or any other suitable operation.In some embodiments, groove 107e have with it is described above Or the similar configuration of illustrated groove in Fig. 1,3,5 or 6.
In operation 505, the second conductive bump 110 is placed above the first conductive structure 108a, as shown in Fig. 7 H. In some embodiments, the second conductive bump 110 be electrically connected to the first conductive structure 108a but with the second conductive structure 108b electricity Isolation.In some embodiments, cream, silk-screen printing or any other suitable operation placement second is applied by falling sphere, solder to lead Electric convex block 110.In some embodiments, the second conductive bump 110 is solder joints, solder projection, soldered ball, ball grid array (BGA) ball, controlled collapse chip connection (C4) convex block, dimpling block etc..In some embodiments, the second conductive bump 110 is Conductive column or column.In some embodiments, the second conductive bump 110 have in described above or Fig. 1,3,5 or 6 The similar configuration of the second illustrated conductive bump.
In operation 506, the second substrate 112 is provided or receives, as shown in Fig. 7 I.In some embodiments, second Substrate 112 is silicon substrate.In some embodiments, the second substrate 112 is printed circuit board (PCB).In some embodiments, Two substrates 112 include the third surface 112a and fourth surface 112b opposite with third surface 112a.In some embodiments, even Device 113 is connect to be placed in above the 4th surface 112b of the second substrate 112.In some embodiments, connector 113 is configured to connect Together in another substrate or encapsulation top and the circuit of the second substrate 112 is electrically connected with the circuit of another substrate or encapsulation.One In a little embodiments, connector 113 is solder joints, solder projection, soldered ball, ball grid array (BGA) ball, controlled collapse chip connection (C4) convex block, dimpling block, conductive column, column etc..In some embodiments, the second substrate 112 and connector 113 have with The similar configuration of illustrated the second substrate and connector in described above or Fig. 1,3,5 or 6.
In operation 507, the second conductive bump 110 is engaged in 112 top of the second substrate, as shown in Fig. 7 J.? In some embodiments, the first conductive structure 108a is bonded together by the second conductive bump 110 and the second substrate 112.? In some embodiments, the circuit of the second substrate 112 by the second conductive bump 110, the first conductive structure 108a, access 102 and First conductive bump 104 and be electrically connected to bare die 103.In some embodiments, the second conductive bump 110 is being engaged in the second lining By reflow after 112 top of bottom.
In some embodiments, the second primer material 111 be placed in the top of the second substrate 112 and around the first substrate 101, RDL (107,108) and the second conductive bump 110.In some embodiments, the second primer material 111 is placed in the second substrate 112 Third surface 112a above.In some embodiments, the second primer material 111 is encapsulated the second conductive bump 110.In some realities It applies in example, the second primer material 111 fills the gap between neighbouring second conductive bump 110.In some embodiments, the second bottom Glue material 111 is placed by flowing, injection or any other suitable operation.In some embodiments, the second primer material 111 Include epoxy resin, resin, epoxy molding material etc..In some embodiments, the second primer material 111 has and institute above The similar configuration of the second illustrated primer material in description or Fig. 1,3,5 or 6.In some embodiments, it is formed such as Illustrated semiconductor structure 100 in Fig. 1.
In this exposure, a kind of semiconductor structure is disclosed.The semiconductor structure includes substrate, is placed in the first of substrate The bare die of surface, the RDL being placed in above the second surface of substrate, the conductive structure being placed in RDL.The conductive knot Structure is configured as sealing ring, the sealing ring protected during production or simple grain RDL and substrate from by crack, fragment or its Damage caused by its pollutant.In this way, the delamination of component can be minimized or be prevented during production or simple grain or to semiconductor The damage of structure.
In some embodiments, a kind of semiconductor structure includes: the first substrate, it includes first surface and with described first The opposite second surface in surface；Access extends through first substrate；Bare die is placed in the institute of first substrate It states above first surface；Redistribution layer (RDL) is placed in above the second surface of first substrate, and includes to be located at Dielectric layer above the second surface, the first conductive structure for being placed in the dielectric layer and being electrically connected to the access and The second conductive structure for being placed in the dielectric layer and being electrically isolated with the access；Second substrate, it includes third surface and Fourth surface opposite with the third surface；And second substrate, it includes third surfaces and opposite with the third surface 4th surface；And conductive bump, it is placed between the third surface of second substrate and the RDL and by described One conductive structure is bonded together with second substrate.
In some embodiments, the RDL is placed between first substrate and second substrate or the access Between the conductive bump.In some embodiments, second conductive structure adjacent to first conductive structure or The edge of the RDL and place.In some embodiments, the second surface of the dielectric layer and first substrate connects Touching.In some embodiments, second conductive structure is to extend along the edge of the RDL or the edge of the dielectric layer Sealing ring.In some embodiments, the distance between the edge of the RDL and second conductive structure are generally less than described The distance between the edge of RDL and first conductive structure.In some embodiments, the dielectric layer includes first layer and heap The second layer being laminated on above the first layer.In some embodiments, the dielectric layer includes polymeric material, polyimides (PI) Or polybenzoxazoles (PBO).In some embodiments, the semiconductor structure further include be placed in first substrate with Barrier layer between the dielectric layer.In some embodiments, second conductive structure by the barrier layer with it is described The separation of first substrate.In some embodiments, the barrier layer includes nitride.In some embodiments, the semiconductor junction Structure further includes: the first primer material, is placed in the third surface of second substrate and around described the One substrate, the RDL and the conductive bump；Second conductive bump is placed in the institute of the bare die Yu first substrate It states between first surface and the bare die and the access is bonded together；Second primer material is placed in described first Above the first surface of substrate and around second conductive bump；Molded is placed in the institute of first substrate It states above first surface and around the bare die；Second conductive bump and second primer material；Or groove, direction First substrate and be recessed into the dielectric layer.
In some embodiments, a kind of semiconductor structure includes: the first substrate, it includes first surface and with described first The opposite second surface in surface；Multiple accesses extend through first substrate；Bare die is placed in first substrate The first surface above；Multiple dielectric layers, be placed in above the second surface of first substrate and each other on Lower stacking；First conductive structure is placed at least one in the multiple dielectric layer and be electrically connected in the multiple access Person；Second conductive structure is placed in the multiple dielectric layer；Second substrate, it includes third surface and with the third The 4th opposite surface of surface；And conductive bump, be placed in second substrate the third surface and the multiple Jie It is bonded together between electric layer and by first conductive structure and second substrate, wherein second conductive structure and institute Multiple accesses, the conductive bump and first conductive structure is stated to be electrically isolated.
In some embodiments, the multiple dielectric layer, first conductive structure and second conductive structure are placed Between first substrate and second substrate.In some embodiments, further comprise third conductive structure, place In in the multiple dielectric layer and being placed between first conductive structure and second conductive structure, wherein the third Conductive structure and the multiple access, the conductive bump and first conductive structure are electrically isolated.In some embodiments, institute The width for stating the second conductive structure is about 50um.In some embodiments, the distance between the two in the multiple access is It is generally less than about 60um.
In some embodiments, a kind of method manufacturing semiconductor structure includes: providing the first substrate, first substrate Comprising first surface, the second surface opposite with the first surface and extend the first surface and the second surface it Between access；Bare die is placed above the first surface of first substrate；In second table of first substrate Dielectric layer is placed above face；The first conductive structure and the second conductive structure are formed in the dielectric layer；It is conductive described first Superstructure places conductive bump, wherein second conductive structure and the access are electrically isolated.
In some embodiments, first conductive structure is formed in above the access and is electrically connected to the access, And second conductive structure is electrically isolated with the conductive bump and first conductive structure.In some embodiments, described Method solidifies the dielectric layer at a temperature of being further contained in substantially below about 400 DEG C；First substrate with it is described Barrier layer is placed between dielectric layer；It is described naked to surround that molded is formed above the first surface of first substrate Piece.
Foregoing teachings summarize the component of several embodiments, so that those skilled in the art can preferably understand this exposure Aspect.It will be understood by one of ordinary skill in the art that its can easily use this exposure as design or modify for implement with The identical purpose of embodiments described herein and/or the other processes and structure for realizing the advantage identical as the embodiment Basis.Those skilled in the art will also be appreciated that such equivalent constructions without departing from the spirit and scope of this exposure, and its Various changes, replacement and change can be made herein without departing substantially from the spirit and scope of this exposure.

Claims (1)

1. a kind of semiconductor structure comprising:
First substrate, it includes first surface and the second surfaces opposite with the first surface；
Access extends through first substrate；
Bare die is placed in above the first surface of first substrate；
Redistribution layer RDL is placed in above the second surface of first substrate, and includes above the second surface Dielectric layer, the first conductive structure for being placed in the dielectric layer and being electrically connected to the access, and it is placed in the dielectric layer The second conductive structure that is interior and being electrically isolated with the access；
Second substrate, it includes third surface and fourth surfaces opposite with the third surface；And
Conductive bump is placed between the third surface of second substrate and the RDL and conductive by described first Structure is bonded together with second substrate.
CN201711230971.5A 2017-08-14 2017-11-29 Semiconductor structure and its manufacturing method Pending CN109390302A (en)

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