CN109377264A - A kind of method of rapid evaluation chip design and production cost - Google Patents
A kind of method of rapid evaluation chip design and production cost Download PDFInfo
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Abstract
The invention discloses a kind of design of rapid evaluation chip and the methods of production cost, the metal layer of chip is fifth metal layer, the 4th metal layer, third metal layer, second metal layer and the first metal layer from top to bottom, on the basis of not destroying its entire circuit planes structure to chip, using to its any one jiao of longitudinal dissection, after the metal layer for confirming chip, quickly etching de-layer is carried out in conjunction with chemical attack reagent.By above-mentioned, the method of the design of rapid evaluation chip and production cost of the invention, to chip on the basis of not destroying its entire circuit planes structure, it is dissected using the longitudinal direction to any one jiao of chip, after confirming its metal layer, quickly etching de-layer is carried out in conjunction with chemical attack reagent, it can be on the usage quantity of a chips, the design and production cost of chip are evaluated in short time, the not strong influence of timeliness due to caused by chip is few and de-layer is slow is greatly reduced, the market survey and R & D Decision to chip product can be conducive to.
Description
Technical field
The present invention relates to the field of chip more particularly to the methods of a kind of design of rapid evaluation chip and production cost.
Background technique
Design and production cost analysis and assessment of the IC design company to chip, are an essential means.
At the beginning of designing project verification, the mainstream chip in market for needing to be related to it carries out a series of analysis, certain to obtain
Technical data and Costco Wholesale estimation；In market sale, needs to be designed its competing product and be commented with production cost
Analysis is estimated, to obtain the information of its Competitive Advantage and Disadvantage in the market；It can also can be evaded by such analysis means
The patent of certain layout design, on the contrary, the also firsthand information of available some domain infringement chips.
In the application end of chip, some chips are the products customized, need to obtain by tearing the modes such as machine open；Some chips
It is to need to the application of design manufacturer or application vendor application, therefore the quantity of sample just becomes extremely valuable.Acquired sample,
Otherwise analysis is also done, so the sample that can do chip design and production cost analysis just becomes extremely rare, usually
Being is one.How on the basis of an only sample, completely chip design and the analysis of production cost are completed, are these
Field problem urgently to be resolved.
Summary of the invention
The invention mainly solves the technical problem of providing rapid evaluation chip design and production cost method, using pair
One jiao of chip of longitudinal dissection combines chemical attack reagent to carry out quickly etching de-layer, can be in the usage quantity of a chips
On, the design and production cost of chip are evaluated in the short time, are greatly reduced due to caused by chip is few and de-layer is slow
The not strong influence of timeliness can be conducive to market survey and R & D Decision to chip product.
In order to solve the above technical problems, one technical scheme adopted by the invention is that: provide a kind of rapid evaluation chip
Design and production cost method, the metal layer of chip be from top to bottom fifth metal layer, the 4th metal layer, third metal layer,
Second metal layer and the first metal layer, on the basis of not destroying its entire circuit planes structure to chip, using any to its
One jiao of longitudinal direction is dissected, and after the metal layer for confirming chip, carries out quickly etching de-layer in conjunction with chemical attack reagent, including with
Lower specific steps:
Step 1 dissects one jiao of chip of longitudinal direction
A1, chip is subjected to embedding sample；
B1, longitudinal grinding is carried out to one of angle of chip, need to be only ground to chip circuit；
C1, the chip after grinding is polished and is cleaned；
D1, to after polishing and cleaning chip abradant surface carry out it is gold-plated, it is gold-plated after chip enter electronic scanner microscope
It is interior, the actual metal number of plies of chip is observed, and measure required size；
E1, the chip of embedding sample is taken out and is cleaned using heat gun；
Step 2 carries out quickly etching de-layer to chip using chemical attack reagent
A2, the chip of taking-up is removed with the oxide layer that is dipped to that chemical attack reagent carries out the short time, and hardware
Belong to the phenomenon that layer bounces；
B2, nano-milled liquid is added on the grinding cloth, gently on the grinding cloth by chip pressing, grinding removal bounce the
Five metal layers and the barrier layer under it；
C2, it repeats that chip is carried out to carry out quickly etching de-layer using chemical attack reagent, until getting rid of third gold
Belong to layer；
D2, the chip with second metal layer is cleaned up, and be put into scanning electron microscope；
Step 3 is scanned electron microscope observation to second metal layer and measures numerical value
A3, the chip modules with second metal layer are sampled, tentatively distinguishes digital circuit blocks, simulation
Circuit module and various types memory；
B3, distance and metal wire in digital circuit blocks, in multiple point measuring second metal layer between two metal line items
The line width of item；
C3, chip is taken out；
Step 4 carries out quickly etching de-layer to the second metal using chemical attack reagent, and micro- using electron scanning
Numerical value is observed and measured to mirror
A4, de-layer is etched to second metal layer using chemical attack reagent；
B4, the chip with the first metal layer is put into scanning electron microscope, confirms digital circuit blocks, simulation electricity
Road module and various types memory；
C4, the parameter value that digital units are measured in digital module
D4, various types memory is sampled, and measures the size number for surveying storage unit in various types memory
Value；
Step 5 carries out quickly etching de-layer to the first metal layer using chemical attack reagent, and aobvious using electron scanning
Numerical value is observed and measured to micro mirror
A5, de-layer is etched to the first metal layer using chemical attack reagent；
B5, the chip with polysilicon layer is put into scanning electron microscope, its polycrystalline is measured in digital circuit blocks
The grid length parameter value of grid；
C5, various types memory is sampled, and measures the size number for surveying storage unit in various types memory
Value；
Polysilicon layer on chip is removed by step 6 using chemical attack reagent, and with optical microscopy to chip
It takes pictures on surface
A6, the polysilicon layer on chip is removed completely using chemical attack reagent；
B6, it is taken pictures using optical microscopy to chip surface, obtains chip general picture figure；
C6, according to scanning electron microscope to the confirmation of chip modules as a result, being measured in chip general picture figure each
The area of module；
Step 7, according to obtained measurement parameter is tested, estimate the design cost of the device count of modules and be produced into
This
A7, the sampling according to scanning electron microscope to second metal layer, the first metal layer and polysilicon layer modules,
In conjunction with the area of modules, the number of devices of digital circuit and the capacity of each memory are estimated；
The parameter measurement of b7, basis to one jiao of chip of longitudinal dissection and the modules of polysilicon layer, estimates production
Cost.
In a preferred embodiment of the present invention, the chip uses Digital Analog Hybrid Circuits chip.
In a preferred embodiment of the present invention, the circuit structure that the chip is included include digital circuit blocks,
Analog module, I/O circuit module and eeprom memory module.
In a preferred embodiment of the present invention, the chip includes five layers of metal layer from top to bottom, and at least one
Layer polysilicon layer passes through through-hole connection between adjacent two layers metal layer.
In a preferred embodiment of the present invention, the metal material of five layers of metal layer is aluminium, connects adjacent two layers
The through-hole material of metal layer is tungsten.
In a preferred embodiment of the present invention, the chemical attack reagent uses HF: water=1:4.
In a preferred embodiment of the present invention, the scanning electron microscope is field emission scanning electron microscope.
The beneficial effects of the present invention are: the method for the design of rapid evaluation chip and production cost of the invention, using to core
One jiao of piece of longitudinal dissection combines chemical attack reagent to carry out quickly etching de-layer, can be in the usage quantity of a chips
On, the design and production cost of chip are evaluated in the short time, are greatly reduced due to caused by chip is few and de-layer is slow
The not strong influence of timeliness can be conducive to market survey and R & D Decision to chip product.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing, in which:
Fig. 1 is the process signal of a preferred embodiment of the method for rapid evaluation chip design of the present invention and production cost
Figure.
Specific embodiment
The technical scheme in the embodiments of the invention will be clearly and completely described below, it is clear that described implementation
Example is only a part of the embodiments of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
Technical staff's all other embodiment obtained without making creative work belongs to the model that the present invention protects
It encloses.
As shown in Figure 1, the embodiment of the present invention includes:
The method of a kind of design of rapid evaluation chip and production cost, the metal layer of chip is fifth metal from top to bottom
Layer, the 4th metal layer, third metal layer, second metal layer and the first metal layer are not destroying its entire circuit planes to chip
On the basis of structure, dissected using to its any one jiao longitudinal direction, after the metal layer for confirming chip, in conjunction with chemical attack reagent
Quickly etching de-layer is carried out, comprising the following specific steps
Step 1 dissects one jiao of chip of longitudinal direction
A1, chip is subjected to embedding sample；
B1, longitudinal grinding is carried out to one of angle of chip, need to be only ground to chip circuit；
C1, the chip after grinding is polished and is cleaned；
D1, to after polishing and cleaning chip abradant surface carry out it is gold-plated, it is gold-plated after chip enter electronic scanner microscope
It is interior, the actual metal number of plies of chip is observed, and measure required size；
E1, the chip of embedding sample is taken out and is cleaned using heat gun；
Step 2 carries out quickly etching de-layer to chip using chemical attack reagent
A2, the chip of taking-up is removed with the oxide layer that is dipped to that chemical attack reagent carries out the short time, and hardware
Belong to the phenomenon that layer bounces；
B2, nano-milled liquid is added on the grinding cloth, gently on the grinding cloth by chip pressing, grinding removal bounce the
Five metal layers and the barrier layer under it；
C2, it repeats that chip is carried out to carry out quickly etching de-layer using chemical attack reagent, until getting rid of third gold
Belong to layer；
D2, the chip with second metal layer is cleaned up, and be put into scanning electron microscope；
Step 3 is scanned electron microscope observation to second metal layer and measures numerical value
A3, the chip modules with second metal layer are sampled, tentatively distinguishes digital circuit blocks, simulation
Circuit module and various types memory；
B3, distance and metal wire in digital circuit blocks, in multiple point measuring second metal layer between two metal line items
The line width of item；
C3, chip is taken out；
Step 4 carries out quickly etching de-layer to the second metal using chemical attack reagent, and micro- using electron scanning
Numerical value is observed and measured to mirror
A4, de-layer is etched to second metal layer using chemical attack reagent；
B4, the chip with the first metal layer is put into scanning electron microscope, confirms digital circuit blocks, simulation electricity
Road module and various types memory；
C4, the parameter value that digital units are measured in digital module
D4, various types memory is sampled, and measures the size number for surveying storage unit in various types memory
Value；
Step 5 carries out quickly etching de-layer to the first metal layer using chemical attack reagent, and aobvious using electron scanning
Numerical value is observed and measured to micro mirror
A5, de-layer is etched to the first metal layer using chemical attack reagent；
B5, the chip with polysilicon layer is put into scanning electron microscope, its polycrystalline is measured in digital circuit blocks
The grid length parameter value of grid；
C5, various types memory is sampled, and measures the size number for surveying storage unit in various types memory
Value；
Polysilicon layer on chip is removed by step 6 using chemical attack reagent, and with optical microscopy to chip
It takes pictures on surface
A6, the polysilicon layer on chip is removed completely using chemical attack reagent；
B6, it is taken pictures using optical microscopy to chip surface, obtains chip general picture figure；
C6, according to scanning electron microscope to the confirmation of chip modules as a result, being measured in chip general picture figure each
The area of module；
Step 7, according to obtained measurement parameter is tested, estimate the design cost of the device count of modules and be produced into
This
A7, the sampling according to scanning electron microscope to second metal layer, the first metal layer and polysilicon layer modules,
In conjunction with the area of modules, the number of devices of digital circuit and the capacity of each memory are estimated；
The parameter measurement of b7, basis to one jiao of chip of longitudinal dissection and the modules of polysilicon layer, estimates production
Cost.
Among the above, the chip uses Digital Analog Hybrid Circuits chip.Wherein, the circuit structure that the chip is included
Including digital circuit blocks, analog module, I/O circuit module and eeprom memory module.
Further, the chip include five layers of metal layer, and at least one layer of polysilicon layer from top to bottom, adjacent two
It is connected between layer metal layer by through-hole.Wherein, the metal material of five layers of metal layer is aluminium, connects adjacent two layers metal
The through-hole material of layer is tungsten.
Further, the chemical attack reagent uses HF: water=1:4, to the oxidation on each metal layer of chip
Layer has the function of corrosion, and the short time impregnates.The chemical attack reagent is to the corrosivity of metal layer compared with oxide layer
Corrosivity is poor, so in use, the immersion of short time can detach metal layer, optical microscopy out of oxide layer
The effect of observation bounces for metal wire, and the method that grinding hereafter can be used quickly removes metal layer and barrier layer.
In the present embodiment, the scanning electron microscope is field emission scanning electron microscope.
On the basis of not destroying its entire circuit planes structure to chip, dissected using to its any one jiao longitudinal direction,
After confirming its metal layer, the quick method for etching de-layer is carried out in conjunction with chemical attack reagent.One step of every completion, requires
Parameter measurement is carried out to it using scanning electron microscope, is dissected in the longitudinal direction to any one jiao, is actual metal layer to be confirmed
Number, and measure the spacing of each interlayer；To second metal layer, the first metal layer and polysilicon layer, mainly between the minimum lines of measurement
Away from, device parameters, memory parameter.Parameter value in summary, on chip bottom layer image, using to modules area
Measurement, can accurately estimate the design and production cost of chip.
It is specific:
The method of the design of rapid evaluation chip and production cost, comprising:
Step 1: chip being subjected to embedding sample, longitudinal grinding is carried out to one of angle of chip, need to only be ground to chip electricity
Road；After abradant surface progress is gold-plated, into electronic scanner microscope, observes and confirm the actual metal number of plies, and measure institute
The size needed；The sample of embedding sample is taken out using heat gun after being measured, and is cleaned；
Step 2: being dipped to oxide layer removal with the short time that chemical attack reagent carries out 5~10 seconds, and observe the 5th
The phenomenon that layer metal layer bounces；Nano-milled liquid is added on the grinding cloth, gently on the grinding cloth by sample pressing, grinds
It grinds off except the fifth metal layer and the barrier layer under it bounced；It repeats that sample is carried out to carry out using chemical attack reagent quick
Etching de-layer, until get rid of third layer metal layer；Chip with second layer metal layer is cleaned up, and is put into scanning
In electron microscope.Measure the planar structure parameter on second layer metal；After the completion of measurement, the progress of chemical attack reagent is reused
Second layer metal is removed, scanning electron microscope is put into, measures the planar structure parameter on first layer metal；After the completion of measurement,
It reuses chemical attack reagent and is removed first layer metal, be put into scanning electron microscope, measure the plane on polysilicon layer
Structural parameters.
Step 3: using chemical attack reagent by polysilicon corrode completely, and with optical microscopy to the entire bottom of chip into
Row Image Acquisition.
Step 4: comprehensive in second layer metal layer, first layer metal layer, the measurement parameters value of polysilicon layer, in chip bottom
Image, outline the memory module of digital circuit blocks, analog module, each type.And estimate the face of modules
Product estimates the capacity of the memory of device count used in modules and each type.In conjunction with the vertical structure figure of angle lap
Parameter, the analysis to chip complete design and production cost.
The parameter of required measurement:
When analyzing experiment, using a chips, to whole chips in vertical structure, confirm that the metal layer of chip is real
The border number of plies, the spacing distance parameter between each layer；One quickly etching is carried out to each metal layer using chemical attack reagent
De-layer, with spacing and device, analog circuit device, Memory Storage Unit between scanning electron microscope measurement digital circuit lines
Etc. parameters.Finally in chip bottom figure layer, according to the layout area of modules, accurately and quickly chip can be estimated
Design and producing cost, the as embodiment of a kind of design of rapid evaluation chip and the method for production cost in practical function.
In conclusion the method for the design of rapid evaluation chip and production cost of the invention, is indulged using to one jiao of chip
Chemical attack reagent is combined to carry out quickly etching de-layer to dissection, it can be on the usage quantity of a chips, in the short time
The design and production cost for evaluating chip, the timeliness greatly reduced due to caused by chip is few and de-layer is slow be not strong
It influences, the market survey and R & D Decision to chip product can be conducive to.
The above description is only an embodiment of the present invention, is not intended to limit the scope of the invention, all to utilize this hair
Equivalent structure or equivalent flow shift made by bright description is applied directly or indirectly in other relevant technology necks
Domain is included within the scope of the present invention.
Claims (7)
1. the method for a kind of design of rapid evaluation chip and production cost, which is characterized in that the metal layer of chip is from top to bottom
Fifth metal layer, the 4th metal layer, third metal layer, second metal layer and the first metal layer, it is entire not destroying it to chip
On the basis of circuit planes structure, dissected using to its any one jiao longitudinal direction, after the metal layer for confirming chip, in conjunction with chemistry
Corrosion reagent carries out quickly etching de-layer, comprising the following specific steps
Step 1 dissects one jiao of chip of longitudinal direction
A1, chip is subjected to embedding sample；
B1, longitudinal grinding is carried out to one of angle of chip, need to be only ground to chip circuit；
C1, the chip after grinding is polished and is cleaned；
D1, to after polishing and cleaning chip abradant surface carry out it is gold-plated, it is gold-plated after chip enter in electronic scanner microscope, see
The actual metal number of plies of chip is surveyed, and measures required size；
E1, the chip of embedding sample is taken out and is cleaned using heat gun；
Step 2 carries out quickly etching de-layer to chip using chemical attack reagent
A2, the chip of taking-up is removed with the oxide layer that is dipped to that chemical attack reagent carries out the short time, and fifth metal layer
The phenomenon that bouncing；
B2, nano-milled liquid is added on the grinding cloth, gently on the grinding cloth by chip pressing, the hardware that grinding removal is bounced
Belong to layer and the barrier layer under it；
C2, it repeats that chip is carried out to carry out quickly etching de-layer using chemical attack reagent, until getting rid of third metal layer；
D2, the chip with second metal layer is cleaned up, and be put into scanning electron microscope；
Step 3 is scanned electron microscope observation to second metal layer and measures numerical value
A3, the chip modules with second metal layer are sampled, tentatively distinguishes digital circuit blocks, analog circuit
Module and various types memory；
B3, in digital circuit blocks, distance and metal wire in multiple point measuring second metal layer between two metal line items
Line width；
C3, chip is taken out；
Step 4, using chemical attack reagent to the second metal carry out quickly etching de-layer, and using electronic scanner microscope into
Row observation and measurement numerical value
A4, de-layer is etched to second metal layer using chemical attack reagent；
B4, the chip with the first metal layer is put into scanning electron microscope, confirms digital circuit blocks, analog circuit mould
Block and various types memory；
C4, the parameter value that digital units are measured in digital module
D4, various types memory is sampled, and measures the dimensional values for surveying storage unit in various types memory；
Step 5 carries out quickly etching de-layer to the first metal layer using chemical attack reagent, and uses electronic scanner microscope
Observed and measured numerical value
A5, de-layer is etched to the first metal layer using chemical attack reagent；
B5, the chip with polysilicon layer is put into scanning electron microscope, its polysilicon gate is measured in digital circuit blocks
Grid length parameter value；
C5, various types memory is sampled, and measures the dimensional values for surveying storage unit in various types memory；
Polysilicon layer on chip is removed by step 6 using chemical attack reagent, and with optical microscopy to chip surface
It takes pictures
A6, the polysilicon layer on chip is removed completely using chemical attack reagent；
B6, it is taken pictures using optical microscopy to chip surface, obtains chip general picture figure；
C6, according to scanning electron microscope to the confirmation of chip modules as a result, measuring modules in chip general picture figure
Area；
Step 7, according to obtained measurement parameter is tested, estimate the design cost and production cost of the device count of modules
A7, the sampling according to scanning electron microscope to second metal layer, the first metal layer and polysilicon layer modules, in conjunction with
The area of modules estimates the number of devices of digital circuit and the capacity of each memory；
The parameter measurement of b7, basis to one jiao of chip of longitudinal dissection and the modules of polysilicon layer, estimates production cost.
2. the method for rapid evaluation chip design according to claim 1 and production cost, which is characterized in that the core
Piece uses Digital Analog Hybrid Circuits chip.
3. the method for rapid evaluation chip design according to claim 2 and production cost, which is characterized in that the core
The circuit structure that piece is included includes digital circuit blocks, analog module, I/O circuit module and eeprom memory mould
Block.
4. the method for rapid evaluation chip design according to claim 1 and production cost, which is characterized in that the core
Piece includes five layers of metal layer, and at least one layer of polysilicon layer from top to bottom, is connected between adjacent two layers metal layer by through-hole.
5. the method for rapid evaluation chip design according to claim 4 and production cost, which is characterized in that described five
The metal material of layer metal layer is aluminium, and the through-hole material of connection adjacent two layers metal layer is tungsten.
6. the method for rapid evaluation chip design according to claim 1 and production cost, which is characterized in that the change
It learns corrosion reagent and uses HF: water=1:4.
7. the method for rapid evaluation chip design according to claim 1 and production cost, which is characterized in that described sweeps
Retouching electron microscope is field emission scanning electron microscope.
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