CN109375437B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN109375437B CN109375437B CN201811555513.3A CN201811555513A CN109375437B CN 109375437 B CN109375437 B CN 109375437B CN 201811555513 A CN201811555513 A CN 201811555513A CN 109375437 B CN109375437 B CN 109375437B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/13338—Input devices, e.g. touch panels
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1339—Gaskets; Spacers; Sealing of cells
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
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- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Mathematical Physics (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Human Computer Interaction (AREA)
- Liquid Crystal (AREA)
Abstract
The invention provides a display panel and a display device, comprising a hole digging area and an ESD protection circuit; the ESD protection circuit comprises a conductive ring and a first conductive lead; the conducting ring is arranged around the hole digging area, the conducting ring and the light-shielding metal layer of the thin film transistor in the display panel are arranged on the same layer, and the conducting ring is electrically connected with the grounding wire of the display panel through the first conducting lead, so that static electricity can be released through a static electricity releasing path formed by the conducting ring, the first conducting lead and the grounding wire, and damage to circuit structures and the like around the hole digging area caused by the static electricity is avoided.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
The full screen technology realizes more than 90% of screen occupation ratio by narrow frame or even no frame design. Under the condition that the machine body is not changed, the maximization of the display area is realized, and the display effect is more brilliant. Based on the structural design of the full-face screen, holes need to be dug in the hole digging area of the display panel, and devices such as a camera, a receiver and an inductor are installed in the holes. However, since there is no ESD (Electro-Static discharge) protection circuit in the trench area, the circuit structure and the like around the trench area are easily damaged by Static electricity.
Disclosure of Invention
In view of the above, the present invention provides a display panel and a display device to solve the problem that there is no ESD protection circuit in the hole digging region of the conventional display panel.
In order to achieve the purpose, the invention provides the following technical scheme:
a display panel comprises a hole digging area and an ESD protection circuit;
the ESD protection circuit comprises a conductive ring and a first conductive lead;
the conducting ring is arranged around the hole digging area, the conducting ring and the shading metal layer of the thin film transistor in the display panel are arranged on the same layer, and the conducting ring is electrically connected with the grounding wire of the display panel through the first conducting lead.
A display device comprising a display panel as claimed in any one of the above.
Compared with the prior art, the technical scheme provided by the invention has the following advantages:
according to the display panel and the display device provided by the invention, the ESD protection circuit comprises the conducting ring and the first conducting lead, the conducting ring is arranged around the hole digging area, the conducting ring and the light-shielding metal layer of the thin film transistor in the display panel are arranged on the same layer, and the conducting ring is electrically connected with the grounding wire of the display panel through the first conducting lead, so that static electricity can be released through the static electricity releasing path formed by the conducting ring, the first conducting lead and the grounding wire, and the damage of the static electricity to the circuit structure and the like around the hole digging area is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic top view of a conventional display panel;
fig. 2 is a schematic top view of a display panel according to an embodiment of the present invention;
FIG. 3 is a cross-sectional view of the display panel shown in FIG. 2 along the section line CC';
fig. 4 is a schematic top view illustrating a display panel according to another embodiment of the present invention;
FIG. 5 is a cross-sectional view of the display panel shown in FIG. 4 along the section line CC';
FIG. 6 is a schematic cross-sectional view of the display panel shown in FIG. 4;
FIG. 7 is a schematic cross-sectional view of the display panel shown in FIG. 4;
fig. 8 is a schematic top view illustrating a display panel according to another embodiment of the present invention;
FIG. 9 is a cross-sectional view of the display panel shown in FIG. 8 along the section line CC';
fig. 10 is a schematic top view illustrating a display panel according to another embodiment of the present invention;
FIG. 11 is a cross-sectional view of the display panel shown in FIG. 10 along the section line CC';
FIG. 12 is a schematic cross-sectional view of the display panel shown in FIG. 10;
fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
As described in the background art, after the hole digging region a is disposed in the display region, in order not to affect the normal operation of the data lines, the gate lines, the touch leads, and the like, the data lines, the gate lines, the touch leads, and the like are disposed around the hole digging region, as shown in fig. 1, fig. 1 is a schematic top view structure diagram of a conventional display panel, and the data lines S are disposed around the hole digging region D. However, since there is no ESD protection circuit in the hole D, static electricity accumulated during operation of the data lines, the gate lines, the touch leads, and the like may damage circuit structures and the like around the hole D.
Accordingly, the present invention provides a display panel to overcome the above problems of the prior art, including a hole digging region and an ESD protection circuit;
the ESD protection circuit comprises a conductive ring and a first conductive lead;
the conducting ring is arranged around the hole digging area, the conducting ring and the shading metal layer of the thin film transistor in the display panel are arranged on the same layer, and the conducting ring is electrically connected with the grounding wire of the display panel through the first conducting lead.
According to the display panel and the display device provided by the invention, the ESD protection circuit comprises the conducting ring and the first conducting lead, the conducting ring is arranged around the hole digging area, the conducting ring and the light-shielding metal layer of the thin film transistor in the display panel are arranged on the same layer, and the conducting ring is electrically connected with the grounding wire of the display panel through the first conducting lead, so that static electricity can be released through the static electricity releasing path formed by the conducting ring, the first conducting lead and the grounding wire, and the damage of the static electricity to the circuit structure and the like around the hole digging area is avoided.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, so that the above is the core idea of the present invention, and the above objects, features and advantages of the present invention can be more clearly understood. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a display panel, as shown in fig. 2, fig. 2 is a schematic top view structure diagram of the display panel according to an embodiment of the present invention, the display panel includes a display area 10 and a non-display area 11, and the non-display area 11 includes a hole digging area 110 and a frame area 111. The frame area 11 is disposed around the display area 10, and the hole digging area 110 is located in the display area 10, so that the width of the frame area 111 is reduced by digging a hole in the hole digging area 110 and disposing devices such as a camera, a receiver, an inductor and the like in the hole, thereby realizing a full-screen.
In the embodiment of the invention, as shown in fig. 2, the display panel includes an ESD protection circuit, which includes a conductive ring 20 and a first conductive lead 21. The conductive ring 20 is disposed around the hole digging region 110, the conductive ring 20 is electrically connected to a ground line 22 of the display panel through a first conductive lead 21, and the ground line 22 is electrically connected to a ground terminal of a driving chip of the display panel through a trace.
It should be noted that the grounding line 22 shown in fig. 2 is located in the frame region 111 and disposed around the display region 10, and not only can transmit the static electricity around the hole digging region 110 to the grounding terminal of the driving chip, but also can transmit the static electricity in the display region 10 to the grounding terminal, so as to prevent the static electricity from damaging the structures such as the routing lines or the electrodes of the display region 10. Of course, the invention is not limited thereto, and in other embodiments, the ground line 22 may also be a trace electrically connected to the ground terminal of the driving chip.
Accordingly, the conductive ring 20, the first conductive lead 21 and the ground line 22 form an electrostatic discharge path, and the electrostatic discharge path discharges static electricity around the hole digging region 110, so that the static electricity can be prevented from causing electrostatic damage to structures such as data lines around the hole digging region 110 and devices such as a camera in the hole of the hole digging region 110.
It should be noted that the hole digging region 110 may be a circular region, a square region, a trapezoid region, or the like, and the conductive ring 20 may be a circular ring or a square ring, and in the embodiment of the present invention, only the hole digging region 110 is a circular region, and the conductive ring 20 is a circular ring is taken as an example for description. It should be further noted that the hole digging region 110 may be located at any position of the display panel, and in the embodiment of the present invention, the description is given by taking the example that the hole digging region 110 is located at the upper left corner of the display panel.
As shown in fig. 3, fig. 3 is a schematic cross-sectional structure view of the display panel shown in fig. 2 along a section line CC', and the display panel in the embodiment of the present invention includes an array substrate 3, a color filter substrate 4, and a liquid crystal layer 5 located between the array substrate 3 and the color filter substrate 4. The array substrate 3 includes a first substrate 30, a thin film transistor 31 on the first substrate 30, a gate line 32, a data line 33, a pixel electrode 34, a touch electrode 35, a touch lead 36, and the like. The touch electrode 35 is reused as a common electrode.
In the embodiment of the invention, the thin film transistor 31 includes a gate electrode 31a, a source electrode 31b, a drain electrode 31c and an active layer 31d, and a light-shielding metal layer 37 is disposed between the thin film transistor 31 and the first substrate 30, wherein the light-shielding metal layer 37 is used for blocking light emitted by a light source in the backlight module from being irradiated onto the active layer 31d, which affects the performance of the active layer 31 d. Alternatively, the material of the light-shielding metal layer 37 is metal Mo.
In the embodiment of the present invention, the conductive ring 20 and the light-shielding metal layer 37 are disposed on the same layer, that is, the conductive ring 20 and the light-shielding metal layer 37 are made of the same material and by the same process, so that the conductive ring 20 can release static electricity without affecting the film structure above the conductive ring, which is more beneficial to the application of the ESD protection circuit.
It should be noted that, the same layer arrangement in the embodiment of the present invention means that both are made of the same material and through the same process. Optionally, the ground line 22 and the touch lead 36 are disposed on the same layer, but the invention is not limited thereto, and in other embodiments, the ground line 22 may also be disposed on the same layer as other conductive layers, such as the data line 33.
As shown in fig. 4, fig. 4 is a schematic top view of a display panel according to another embodiment of the present invention, in which the conductive ring 20 includes a first conductive ring 201, a second conductive ring 202 located inside the first conductive ring 201, and a plurality of second conductive leads 203 located between the first conductive ring 201 and the second conductive ring 202, and the second conductive ring 202 is electrically connected to the first conductive ring 201 through the plurality of second conductive leads 203. Also, the first conductive lead 21 is electrically connected to the first conductive loop 201. Based on this, the second conductive ring 202 can transmit the static electricity around the hollowed area 110 to the first conductive ring 201 through the second conductive lead 203, and discharge the static electricity through the first conductive lead 21 and the ground line 22.
Optionally, the radial second conductive leads 203 are located between the first conductive ring 201 and the second conductive ring 202, and the plurality of second conductive leads 203 are uniformly distributed. In general, in the direction Y perpendicular to the display panel, a portion of the data lines 33 are located between the first conductive ring 201 and the second conductive ring 202 (not shown), and compared with the first conductive ring 201 and the second conductive ring 202 being directly contacted and electrically connected, the plurality of second conductive leads 203 are used to electrically connect the first conductive ring 201 and the second conductive ring 202, so as to reduce the coupling capacitance between the conductive ring 20 and the data lines 33 above the conductive ring, so as to prevent the coupling capacitance from affecting the strength of the data signals in the data lines 33 and further affecting the transmission of the data signals. In addition, since the plurality of second conductive leads 203 are connected in parallel, the ground impedance of the conductive ring 20 is small, which is more favorable for electrostatic discharge.
As shown in fig. 4 and fig. 5, fig. 5 is a schematic cross-sectional structure view of the display panel shown in fig. 4 along a section line CC', the non-display region 11 further includes a sealant region 112, the sealant region 112 has a sealant 1120, the sealant region 112 and the sealant 1120 are disposed around the hole digging region 110, and the sealant 1120 is used for blocking liquid crystal in the display panel from entering the hole digging region 110.
In addition, in the direction Y perpendicular to the display panel, the projection of the sealant 1120 covers the projection of the second conductive ring 202, and the projection of the sealant 1120 overlaps with the projection of the traces such as the data line 33, but the projection of the sealant 1120 does not cover the projection of the first conductive ring 201.
Since the projection of the sealant 1120 overlaps with the projection of the data lines 33 and other wirings, the second conductive ring 202 is disposed under the sealant 1120, and static electricity accumulated in the data lines 33 and other wirings under the sealant 1120 can be led to the first conductive ring 201 outside the sealant 1120 through the second conductive ring 202 and then released through the static electricity path, thereby avoiding static electricity damage.
Although the second conductive ring 202 is located right under the sealant 1120, since the second conductive ring 202 and the light-shielding metal layer 37 are disposed on the same layer, planarization processing is performed during the subsequent film layer manufacturing process, so that the film layer on the top of the second conductive ring 202 is not lifted up, and the risk of liquid crystal leakage due to uneven plane at the bottom of the sealant 1120 is avoided.
As shown in fig. 5, in the present embodiment, the first conductive lead 21 is disposed on the same layer as the touch lead 36 of the display panel, and the ground line 22 is also disposed on the same layer as the touch lead 36, so that the first conductive lead 21 and the ground line 22 can be electrically connected by direct contact. Also, the first conductive lead 21 may be electrically connected to the first conductive ring 201 through a via hole, a metal layer where the data line 33 is located, and a metal layer where the gate electrode 31a is located.
Of course, the invention is not limited thereto, and in other embodiments, as shown in fig. 6, fig. 6 is another cross-sectional structure diagram of the display panel shown in fig. 4, the first conductive lead 21 may also be disposed on the same layer as the data line 33, the first conductive lead 21 is electrically connected to the first conductive ring 201 through a via and a metal layer where the gate 31a is located, and the ground line 22 is electrically connected to the first conductive lead 21 through a via.
Alternatively, as shown in fig. 7, fig. 7 is another cross-sectional structure diagram of the display panel shown in fig. 4, the first conductive lead 21 may also be disposed on the same layer as the gate 31a, the first conductive lead 21 is electrically connected to the first conductive ring 201 through a via, and the ground line 22 is electrically connected to the first conductive lead 21 through a metal layer on which the via and the data line 33 are located.
As shown in fig. 8, fig. 8 is a schematic top view of a display panel according to another embodiment of the present invention, and the ESD protection circuit further includes a plurality of third conductive rings 203, where the third conductive rings 203 are disposed around the hole digging regions 110. The plurality of third conductive rings 203 and the plurality of conductive layers located between the second conductive ring 202 and the sealant 1120 are disposed in the same layer in a one-to-one correspondence manner, wherein the plurality of conductive layers include a touch lead layer, a touch electrode layer, a pixel electrode layer, and the like. Also, any one of the third conductive rings 203 is electrically connected to the second conductive ring 202.
Optionally, the third conductive ring 203 is electrically connected to the second conductive ring 202 through a plurality of uniformly distributed via holes 2030, so that static electricity in each conductive layer is conducted to the second conductive ring 202 through the third conductive ring 203, and static electricity is discharged through a static electricity discharge path formed by the second conductive ring 202, the second conductive lead 203, the first conductive ring 201, the first conductive lead 21, and the ground line 22.
Optionally, as shown in fig. 8, any one of the third conductive rings 203 is in a grid shape to ensure light transmittance of a region where the third conductive ring 203 is located, that is, to ensure that the sealant 1120 can be irradiated by the background light, so as to ensure reliable curing of the sealant 1120.
As shown in fig. 9, fig. 9 is a schematic cross-sectional view of the display panel shown in fig. 8 along a section line CC', and projections of any two third conductive rings 203 overlap in a direction Y perpendicular to the display panel; the projection of any one of the third conductive rings 203 covers the projection of the second conductive ring 202, so that the respective third conductive rings 203 are stacked together and electrically connected to the second conductive ring 202 through vias.
Optionally, as shown in fig. 9, the first third conductive ring 203a is disposed on the same layer as the touch lead 36 and electrically connected to the second conductive ring 202 through the via hole, so as to release static electricity of the conductive layer where the touch lead 36 is located; the second third conductive ring 203b is disposed on the same layer as the touch electrode 35, and is electrically connected to the third conductive ring 203a through the via hole, so as to release the static electricity of the conductive layer where the touch electrode 35 is located; the third conductive ring 203c is disposed on the same layer as the pixel electrode 34, and is electrically connected to the third conductive ring 203b through a via hole, so as to discharge static electricity from the conductive layer on which the pixel electrode 34 is disposed. The via hole between the third conductive ring 203a and the second conductive ring 202 penetrates through the film layer where the data line 33 is located and the film layer where the gate electrode 31a is located, and the film layer where the data line 33 is located and the film layer where the gate electrode 31a is located play a role in providing a via hole and a pad layer.
As shown in fig. 9, in the present embodiment, the first conductive lead 21 and the touch lead 36 are disposed on the same layer, the ground line 22 and the data line 33 are disposed on the same layer, the ground line 22 is electrically connected to the first conductive lead 21 through the via hole, and the first conductive lead 21 is electrically connected to the first conductive ring 201 through the via hole and the conductive layer where the data line 22 is located and the conductive layer where the gate 31a is located.
As shown in fig. 10 and 11, fig. 10 is a schematic top view structure of a display panel according to another embodiment of the invention, fig. 11 is a schematic cross-sectional structure of the display panel shown in fig. 10 along a section line CC', the conductive ring 20 is located below the sealant 1120 in the sealant region 112, that is, in a direction Y perpendicular to the display panel, a projection of the sealant 1120 covers a projection of the conductive ring 20, so as to introduce static electricity on structures such as the data line 33 overlapped with the projection of the sealant 1120 to the static electricity discharge path.
As shown in fig. 10 and 11, the first conductive lead 21 includes a first sub-lead 211 and a second sub-lead 212. The first sub-lead 211 is electrically connected to the conductive ring 20 through a via, the second sub-lead 212 is electrically connected to the ground line 22 through a via, and the second sub-lead 212 is electrically connected to the first sub-lead 211 through a via, so as to establish an electrostatic discharge path between the conductive ring 20 and the ground line 22.
The first sub-lead 211 is located in the display region 10 of the display panel, and the second sub-lead 212 and the ground line 22 are located in the non-display region 11, i.e., the frame region 111 of the display panel. Based on this, the conductive layer with better transmittance can be selected to manufacture the first sub-lead 211, so as to reduce the influence of the first sub-lead 211 on the aperture ratio; the conductive layer with the lower impedance is selected to make the second sub-lead 212 to reduce the impedance of the ESD protection circuit.
Alternatively, as shown in fig. 11, the first sub-lead 211 is disposed in the same layer as the active layer 31d in the thin film transistor to reduce the influence of the first sub-lead 211 on the aperture ratio by the active layer 31d having better transmittance than the light-shielding metal layer 37; the second sub-lead 212 is disposed in the same layer as the light-shielding metal layer 37. Of course, the present invention is not limited thereto, and in other embodiments, as shown in fig. 12, fig. 12 is another schematic cross-sectional structure diagram of the display panel shown in fig. 10, and the first sub-lead 211 and the gate electrode 31a in the thin film transistor are disposed in the same layer, so as to reduce the influence of the first sub-lead 211 on the aperture ratio through the gate electrode 31a with better transmittance than the light-shielding metal layer 37; the second sub-lead 212 is disposed in the same layer as the light-shielding metal layer 37.
Of course, the invention is not limited in this regard and in other embodiments, the conductive ring 20 and the ground line 22 may be electrically connected in other ways.
According to the display panel provided by the invention, the ESD protection circuit comprises the conducting ring and the first conducting lead, the conducting ring is arranged around the hole digging area, the conducting ring and the shading metal layer of the thin film transistor in the display panel are arranged on the same layer, and the conducting ring is electrically connected with the grounding wire of the display panel through the first conducting lead, so that static electricity can be released through the static electricity releasing path formed by the conducting ring, the first conducting lead and the grounding wire, and the damage of the static electricity to the circuit structure and the like around the hole digging area is avoided.
The embodiment of the invention also provides a display device which comprises the display panel provided by any one of the above embodiments. As shown in fig. 13, fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present invention, where the display device 100 may be a mobile phone, a computer, a television, an intelligent wearable display device, and the like, and this is not particularly limited in the embodiment of the present invention.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (12)
1. A display panel is characterized by comprising a hole digging area and an ESD protection circuit;
the ESD protection circuit comprises a conductive ring and a first conductive lead;
the conducting ring is arranged around the hole digging region, the conducting ring and the shading metal layer of the thin film transistor in the display panel are arranged on the same layer, and the conducting ring is electrically connected with the grounding wire of the display panel through the first conducting lead, wherein the conducting ring and the shading metal layer are made of the same material and are made by the same process;
the conducting rings comprise a first conducting ring, a second conducting ring positioned in the first conducting ring and a plurality of radial second conducting leads positioned between the first conducting ring and the second conducting ring, the second conducting ring is electrically connected with the first conducting ring through the plurality of radial second conducting leads, and the plurality of second conducting leads are uniformly distributed.
2. The display panel according to claim 1, wherein the display panel comprises a sealant disposed around the hole digging region;
the frame glue is used for blocking liquid crystal in the display panel from flowing into the hole digging region;
and the projection of the frame glue in the direction vertical to the display panel covers the projection of the second conducting ring in the direction vertical to the display panel.
3. The display panel of claim 2, wherein the ESD protection circuit further comprises a plurality of third conductive loops disposed around the perforated area;
the plurality of third conducting rings and the plurality of conducting layers positioned between the second conducting rings and the frame glue are arranged in the same layer in a one-to-one correspondence manner;
the third conductive ring is electrically connected to the second conductive ring.
4. The display panel according to claim 3, wherein the plurality of conductive layers include a touch lead layer, a touch electrode layer, and a pixel electrode layer.
5. The display panel of claim 3, wherein projections of any two of the third conductive loops in a direction perpendicular to the display panel overlap;
the projection of any one of the third conductive rings in the direction perpendicular to the display panel covers the projection of the second conductive ring in the direction perpendicular to the display panel.
6. The display panel of claim 3, wherein any one of the third conductive loops is in a grid shape.
7. The display panel according to any one of claims 1 to 6, wherein the first conductive lead is disposed on the same layer as a touch lead of the display panel;
or the first conductive lead and the grid electrode in the thin film transistor are arranged on the same layer;
or, the first conductive lead and the data line of the display panel are arranged on the same layer.
8. The display panel of claim 1, wherein the first conductive lead comprises a first sub-lead and a second sub-lead;
the first sub-lead is electrically connected with the conductive loop, the second sub-lead is electrically connected with the ground wire, and the second sub-lead is electrically connected with the first sub-lead;
the first sub-lead is located in a display area of the display panel, and the second sub-lead and the grounding line are located in a non-display area of the display panel.
9. The display panel according to claim 8, wherein the first sub-lead is provided in the same layer as an active layer in the thin film transistor;
the second sub-lead and the shading metal layer are arranged on the same layer.
10. The display panel according to claim 8, wherein the first sub-lead is provided in the same layer as a gate electrode in the thin film transistor;
the second sub-lead and the shading metal layer are arranged on the same layer.
11. The display panel of claim 1, wherein the ground line is disposed on a same layer as a data line of the display panel, and the ground line is electrically connected to a ground terminal of a driving chip in the display panel through a trace.
12. A display device comprising the display panel according to any one of claims 1 to 11.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811555513.3A CN109375437B (en) | 2018-12-19 | 2018-12-19 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811555513.3A CN109375437B (en) | 2018-12-19 | 2018-12-19 | Display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109375437A CN109375437A (en) | 2019-02-22 |
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| TWI696988B (en) | 2019-05-02 | 2020-06-21 | 友達光電股份有限公司 | Display panel |
| CN110197843B (en) * | 2019-05-31 | 2021-10-26 | 武汉天马微电子有限公司 | Display panel and display device |
| CN111025734A (en) * | 2019-12-16 | 2020-04-17 | 友达光电（昆山）有限公司 | Display device |
| CN111258456B (en) * | 2020-01-21 | 2022-09-20 | 重庆京东方显示技术有限公司 | Display substrate, manufacturing method thereof and display device |
| CN114730225B (en) | 2020-09-17 | 2023-02-07 | 京东方科技集团股份有限公司 | Touch panel, touch display panel and electronic device |
| CN112947784B (en) * | 2021-02-03 | 2023-02-28 | 武汉华星光电半导体显示技术有限公司 | Touch panel and display device |
| CN113282197B (en) * | 2021-06-10 | 2024-03-15 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN114242736A (en) * | 2021-12-17 | 2022-03-25 | 湖北长江新型显示产业创新中心有限公司 | Display panel and display device |
| CN115547196A (en) * | 2022-09-27 | 2022-12-30 | 武汉天马微电子有限公司 | Display panel and display device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013172092A1 (en) * | 2012-05-17 | 2013-11-21 | Kabushiki Kaisha Toshiba | Display module and electronic apparatus |
| CN106293166A (en) * | 2015-05-14 | 2017-01-04 | 南昌欧菲光科技有限公司 | Contactor control device and electronic equipment |
| CN107664867A (en) * | 2016-07-29 | 2018-02-06 | 株式会社日本显示器 | Display device |
| CN108037608A (en) * | 2018-01-02 | 2018-05-15 | 京东方科技集团股份有限公司 | Array base palte, touch-control display panel and display device |
| CN108873515A (en) * | 2018-06-19 | 2018-11-23 | 厦门天马微电子有限公司 | Display panel and display device |
| CN108873518A (en) * | 2018-06-26 | 2018-11-23 | 厦门天马微电子有限公司 | Display panel and display device |
| CN108873512A (en) * | 2018-06-06 | 2018-11-23 | 厦门天马微电子有限公司 | Display panel and display device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203117594U (en) * | 2012-12-24 | 2013-08-07 | 上海中航光电子有限公司 | Electrostatic guard ring and liquid crystal display panel with same |
| KR102113607B1 (en) * | 2013-08-30 | 2020-05-21 | 엘지디스플레이 주식회사 | Liquid crystal display device and method of fabricating the same |
| CN206301110U (en) * | 2017-01-03 | 2017-07-04 | 京东方科技集团股份有限公司 | Display base plate and display device |
-
2018
- 2018-12-19 CN CN201811555513.3A patent/CN109375437B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013172092A1 (en) * | 2012-05-17 | 2013-11-21 | Kabushiki Kaisha Toshiba | Display module and electronic apparatus |
| CN106293166A (en) * | 2015-05-14 | 2017-01-04 | 南昌欧菲光科技有限公司 | Contactor control device and electronic equipment |
| CN107664867A (en) * | 2016-07-29 | 2018-02-06 | 株式会社日本显示器 | Display device |
| CN108037608A (en) * | 2018-01-02 | 2018-05-15 | 京东方科技集团股份有限公司 | Array base palte, touch-control display panel and display device |
| CN108873512A (en) * | 2018-06-06 | 2018-11-23 | 厦门天马微电子有限公司 | Display panel and display device |
| CN108873515A (en) * | 2018-06-19 | 2018-11-23 | 厦门天马微电子有限公司 | Display panel and display device |
| CN108873518A (en) * | 2018-06-26 | 2018-11-23 | 厦门天马微电子有限公司 | Display panel and display device |
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