CN109374951A - A Synchronous Signal Detection Loop Based on FPGA - Google Patents
A Synchronous Signal Detection Loop Based on FPGA Download PDFInfo
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- CN109374951A CN109374951A CN201811358929.6A CN201811358929A CN109374951A CN 109374951 A CN109374951 A CN 109374951A CN 201811358929 A CN201811358929 A CN 201811358929A CN 109374951 A CN109374951 A CN 109374951A
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- 238000001514 detection method Methods 0.000 title claims abstract description 34
- 230000001360 synchronised effect Effects 0.000 title claims description 10
- 238000005070 sampling Methods 0.000 claims abstract description 14
- 230000003068 static effect Effects 0.000 claims abstract description 14
- 238000006243 chemical reaction Methods 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000002485 combustion reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000013589 supplement Substances 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/0084—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring voltage only
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Abstract
本发明提供了一种基于FPGA的同步信号检测回路，包括用于测量静止变频启动装置SFC输入侧电网电压的电压采集装置，电压采集装置输入端连接SFC，电压采集装置输出端连接同步信号检测板SU的电压信号输入端，SU的同步信号输出端连接主控制板上的现场可编程门阵列FPGA的输入端，FPGA的压采保信号输出端连接SU的压采保信号输入端。FPGA根据同步信号产生压采保信号送至SU，压采保信号用于避免触发SFC网桥侧的可控硅对采样电路产生干扰，当可控硅触发开始时不采集电网电压信号，从而保证同步信号检测的准确性。本发明结构简单，成本低廉，性能可靠，适于大范围推广使用。
The invention provides a synchronization signal detection loop based on FPGA, including a voltage acquisition device for measuring the grid voltage on the SFC input side of a static variable frequency starting device, the input end of the voltage acquisition device is connected to the SFC, and the output end of the voltage acquisition device is connected to a synchronization signal detection board The voltage signal input terminal of the SU and the synchronization signal output terminal of the SU are connected to the input terminal of the field programmable gate array FPGA on the main control board, and the voltage sampling protection signal output terminal of the FPGA is connected to the voltage sampling protection signal input terminal of the SU. The FPGA generates a voltage sampling protection signal according to the synchronization signal and sends it to the SU. The voltage sampling protection signal is used to avoid the interference of the thyristor on the SFC bridge side to the sampling circuit. When the thyristor starts to trigger, the grid voltage signal is not collected, so as to ensure Accuracy of sync signal detection. The invention has the advantages of simple structure, low cost and reliable performance, and is suitable for widespread use.
Description
Technical field
The present invention relates to a kind of synchronization signal detection circuits, more particularly to one kind is for realizing starting of static frequency conversion device
SFC inputs the circuit of the synchronization signal detection of network voltage.
Background technique
Starting of static frequency conversion device SFC is widely used in the fields such as large-scale combustion engine unit and pumped storage machine.It will hair
Motor is used as synchronous motor, provides the power supply of variable voltage and frequency to generator by SFC, while controlling Excitation Adjustment
Device is saved, exciting current appropriate is added to generator amature during startup, to make unit starting.It is defeated to step up SFC
Frequency out, is stepped up rotor speed, to meet the requirement of combustion engine unit raising speed.
The bridge side of starting of static frequency conversion device SFC by Group of Silicon Controlled Rectifier at three phase full bridge controlled rectification circuit, by grid side
AC power source is transformed to DC power supply.When SFC normal output voltage, bridge work is in rectification state, by changing rectifier and trigger
Realize the control to DC voltage and electric current in angle.
The core of bridge control is to generate synchronization signal by measurement grid side ac voltage signal, then further according to same
It walks signal and trigger delay angle generates trigger pulse, trigger three phase full bridge controlled rectification circuit.
Existing sync signal detection apparatus, usually directly send ac voltage signal into master control borad, according to alternating current
It presses through zero point and determines synchronization signal, anti-interference is poor, affects the accuracy of testing result.
Summary of the invention
The technical problem to be solved by the present invention is to how realize the synchronization of starting of static frequency conversion device SFC input network voltage
The accurate detection of signal.
In order to solve the above-mentioned technical problem, the technical solution of the present invention is to provide a kind of synchronization signal detections based on FPGA
Circuit, it is characterised in that: including the voltage collecting device for measuring starting of static frequency conversion device SFC input side network voltage,
Voltage collecting device input terminal connects SFC, and the voltage signal that voltage collecting device output end connects synchronization signal detection plate SU is defeated
Enter end, the input terminal of the on-site programmable gate array FPGA in the synchronous signal output end connection master board of SU, the pressure of FPGA
The pressure for adopting guarantor's signal output end connection SU adopts guarantor's signal input part.
Preferably, the voltage collecting device is voltage transformer.
Preferably, the voltage collecting device is divider resistance.
Preferably, the power grid three-phase alternating voltage signal of the input side of the SFC accesses SU by voltage collecting device；SU
The synchronization signal of the three-phase alternating voltage signal is generated, and the synchronization signal is sent into the FPGA in master board；FPGA
The start pulse signal that the bridge side of SFC is generated according to the synchronization signal and trigger delay angle, drive the bridge side of SFC can
It controls silicon and generates the DC voltage and electric current needed；FPGA adopts information-preserving number also according to synchronization signal generation pressure and send to SU, and pressure is adopted
Information-preserving number, for avoiding the silicon-controlled of triggering SFC bridge side from generating interference to sample circuit, is not adopted when control machines start
Collect mains voltage signal, to guarantee the accuracy of synchronization signal detection.
Preferably, the pressure adopt information-preserving number be point take shielding sampled signal on trigger pulse head, and other times into
Row sampled signal.
Device provided by the invention overcomes the deficiencies in the prior art, synchronizes signal detection by SU, passes through FPGA
Information-preserving number is adopted to pressure to control, enhances the anti-interference of system, realizes starting of static frequency conversion device SFC input power grid electricity
The accurate detection of the synchronization signal of pressure.Apparatus structure is simple, low in cost, reliable performance, is suitable for a wide range of promote the use of.
Detailed description of the invention
Fig. 1 is the synchronization signal detection loop structure schematic diagram provided in this embodiment based on FPGA；
Fig. 2 is that pressure adopts guarantor's signal schematic representation.
Specific embodiment
Present invention will be further explained below with reference to specific examples.
Fig. 1 be the synchronization signal detection loop structure schematic diagram provided in this embodiment based on FPGA, it is described based on
The synchronization signal detection circuit of FPGA includes the voltage acquisition for measuring starting of static frequency conversion device SFC input side network voltage
Device, voltage collecting device input terminal connect starting of static frequency conversion device SFC, and voltage collecting device output end connects synchronization signal
The voltage signal inputs of detection plate SU, the synchronous signal output end of synchronization signal detection plate SU connect the scene in master board
The input terminal of programmable gate array FPGA, the pressure of on-site programmable gate array FPGA, which is adopted, protects signal output end connection synchronization signal inspection
The pressure of drafting board SU adopts guarantor's signal input part.
In the present embodiment, the voltage collecting device for measuring starting of static frequency conversion device SFC input side network voltage is
Voltage transformer pt or divider resistance.
Synchronization signal detection circuit provided in this embodiment based on FPGA is in use, by starting of static frequency conversion device SFC
Input side power grid three-phase alternating voltage signal it is same by the secondary side of voltage transformer pt or divider resistance partial pressure access
Signal detection plate SU is walked, the synchronization signal that synchronization signal detection plate SU generates three-phase alternating voltage signal is sent into master board
On-site programmable gate array FPGA, the touching that on-site programmable gate array FPGA is determined according to the synchronization signal and control algolithm of detection
The start pulse signal that delay angle generates the bridge side of starting of static frequency conversion device SFC is sent out, starting of static frequency conversion device SFC is driven
Bridge side silicon-controlled generation need DC voltage and electric current.On-site programmable gate array FPGA is produced also according to synchronization signal
Raw pressure is adopted information-preserving number and is sent to synchronization signal detection plate SU, and pressure adopts information-preserving number for avoiding the silicon-controlled to adopting of triggering SFC bridge side
Sample circuit generates interference, mains voltage signal is not acquired when control machines start, to ensure that synchronization signal detection
Accuracy.
Wherein, the generation of trigger delay angle is realized by the DSP in master board, according to DC current reference value and actual value
Comparison determine trigger delay angle.
Pressure is adopted information-preserving number and is generated by FPGA, takes shielding sampled signal on trigger pulse head point, and other times carry out
Sampled signal.As shown in Fig. 2, allowing pressure to adopt information-preserving number in head pulse is 0, then synchronization signal detection plate SU is without sampling and to letter
It number is kept；Allowing pressure to adopt information-preserving number in other times is 1, then synchronization signal detection plate SU is sampled.
The above, only presently preferred embodiments of the present invention, not to the present invention in any form with substantial limitation,
It should be pointed out that under the premise of not departing from the method for the present invention, can also be made for those skilled in the art
Several improvement and supplement, these are improved and supplement also should be regarded as protection scope of the present invention.All those skilled in the art,
Without departing from the spirit and scope of the present invention, when made using disclosed above technology contents it is a little more
Dynamic, modification and the equivalent variations developed, are equivalent embodiment of the invention；Meanwhile all substantial technologicals pair according to the present invention
The variation, modification and evolution of any equivalent variations made by above-described embodiment, still fall within the range of technical solution of the present invention
It is interior.
Claims (5)
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| CN1061286A (en) * | 1990-11-05 | 1992-05-20 | 中国科学院武汉岩土力学研究所 | The pile integrity tester that has time function synchronous amplification signal device |
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2018
- 2018-11-15 CN CN201811358929.6A patent/CN109374951B/en active Active
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