CN109374951A - A kind of synchronization signal detection circuit based on FPGA - Google Patents
A kind of synchronization signal detection circuit based on FPGA Download PDFInfo
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- CN109374951A CN109374951A CN201811358929.6A CN201811358929A CN109374951A CN 109374951 A CN109374951 A CN 109374951A CN 201811358929 A CN201811358929 A CN 201811358929A CN 109374951 A CN109374951 A CN 109374951A
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- 238000001514 detection method Methods 0.000 title claims abstract description 34
- 238000006243 chemical reaction Methods 0.000 claims abstract description 14
- 230000003068 static effect Effects 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 230000001360 synchronised effect Effects 0.000 claims abstract description 5
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims abstract description 3
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- 238000005516 engineering process Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/0084—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring voltage only
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Abstract
The present invention provides a kind of synchronization signal detection circuit based on FPGA, including the voltage collecting device for measuring starting of static frequency conversion device SFC input side network voltage, voltage collecting device input terminal connects SFC, the voltage signal inputs of voltage collecting device output end connection synchronization signal detection plate SU, the input terminal of on-site programmable gate array FPGA in the synchronous signal output end connection master board of SU, the pressure that the pressure of FPGA adopts guarantor's signal output end connection SU adopt guarantor's signal input part.FPGA adopts information-preserving number according to synchronization signal generation pressure and send to SU, pressure adopts information-preserving number for avoiding the silicon-controlled of triggering SFC bridge side from generating interference to sample circuit, mains voltage signal is not acquired when control machines start, to guarantee the accuracy of synchronization signal detection.The configuration of the present invention is simple, low in cost, reliable performance are suitable for a wide range of promote the use of.
Description
Technical field
The present invention relates to a kind of synchronization signal detection circuits, more particularly to one kind is for realizing starting of static frequency conversion device
SFC inputs the circuit of the synchronization signal detection of network voltage.
Background technique
Starting of static frequency conversion device SFC is widely used in the fields such as large-scale combustion engine unit and pumped storage machine.It will hair
Motor is used as synchronous motor, provides the power supply of variable voltage and frequency to generator by SFC, while controlling Excitation Adjustment
Device is saved, exciting current appropriate is added to generator amature during startup, to make unit starting.It is defeated to step up SFC
Frequency out, is stepped up rotor speed, to meet the requirement of combustion engine unit raising speed.
The bridge side of starting of static frequency conversion device SFC by Group of Silicon Controlled Rectifier at three phase full bridge controlled rectification circuit, by grid side
AC power source is transformed to DC power supply.When SFC normal output voltage, bridge work is in rectification state, by changing rectifier and trigger
Realize the control to DC voltage and electric current in angle.
The core of bridge control is to generate synchronization signal by measurement grid side ac voltage signal, then further according to same
It walks signal and trigger delay angle generates trigger pulse, trigger three phase full bridge controlled rectification circuit.
Existing sync signal detection apparatus, usually directly send ac voltage signal into master control borad, according to alternating current
It presses through zero point and determines synchronization signal, anti-interference is poor, affects the accuracy of testing result.
Summary of the invention
The technical problem to be solved by the present invention is to how realize the synchronization of starting of static frequency conversion device SFC input network voltage
The accurate detection of signal.
In order to solve the above-mentioned technical problem, the technical solution of the present invention is to provide a kind of synchronization signal detections based on FPGA
Circuit, it is characterised in that: including the voltage collecting device for measuring starting of static frequency conversion device SFC input side network voltage,
Voltage collecting device input terminal connects SFC, and the voltage signal that voltage collecting device output end connects synchronization signal detection plate SU is defeated
Enter end, the input terminal of the on-site programmable gate array FPGA in the synchronous signal output end connection master board of SU, the pressure of FPGA
The pressure for adopting guarantor's signal output end connection SU adopts guarantor's signal input part.
Preferably, the voltage collecting device is voltage transformer.
Preferably, the voltage collecting device is divider resistance.
Preferably, the power grid three-phase alternating voltage signal of the input side of the SFC accesses SU by voltage collecting device；SU
The synchronization signal of the three-phase alternating voltage signal is generated, and the synchronization signal is sent into the FPGA in master board；FPGA
The start pulse signal that the bridge side of SFC is generated according to the synchronization signal and trigger delay angle, drive the bridge side of SFC can
It controls silicon and generates the DC voltage and electric current needed；FPGA adopts information-preserving number also according to synchronization signal generation pressure and send to SU, and pressure is adopted
Information-preserving number, for avoiding the silicon-controlled of triggering SFC bridge side from generating interference to sample circuit, is not adopted when control machines start
Collect mains voltage signal, to guarantee the accuracy of synchronization signal detection.
Preferably, the pressure adopt information-preserving number be point take shielding sampled signal on trigger pulse head, and other times into
Row sampled signal.
Device provided by the invention overcomes the deficiencies in the prior art, synchronizes signal detection by SU, passes through FPGA
Information-preserving number is adopted to pressure to control, enhances the anti-interference of system, realizes starting of static frequency conversion device SFC input power grid electricity
The accurate detection of the synchronization signal of pressure.Apparatus structure is simple, low in cost, reliable performance, is suitable for a wide range of promote the use of.
Detailed description of the invention
Fig. 1 is the synchronization signal detection loop structure schematic diagram provided in this embodiment based on FPGA；
Fig. 2 is that pressure adopts guarantor's signal schematic representation.
Specific embodiment
Present invention will be further explained below with reference to specific examples.
Fig. 1 be the synchronization signal detection loop structure schematic diagram provided in this embodiment based on FPGA, it is described based on
The synchronization signal detection circuit of FPGA includes the voltage acquisition for measuring starting of static frequency conversion device SFC input side network voltage
Device, voltage collecting device input terminal connect starting of static frequency conversion device SFC, and voltage collecting device output end connects synchronization signal
The voltage signal inputs of detection plate SU, the synchronous signal output end of synchronization signal detection plate SU connect the scene in master board
The input terminal of programmable gate array FPGA, the pressure of on-site programmable gate array FPGA, which is adopted, protects signal output end connection synchronization signal inspection
The pressure of drafting board SU adopts guarantor's signal input part.
In the present embodiment, the voltage collecting device for measuring starting of static frequency conversion device SFC input side network voltage is
Voltage transformer pt or divider resistance.
Synchronization signal detection circuit provided in this embodiment based on FPGA is in use, by starting of static frequency conversion device SFC
Input side power grid three-phase alternating voltage signal it is same by the secondary side of voltage transformer pt or divider resistance partial pressure access
Signal detection plate SU is walked, the synchronization signal that synchronization signal detection plate SU generates three-phase alternating voltage signal is sent into master board
On-site programmable gate array FPGA, the touching that on-site programmable gate array FPGA is determined according to the synchronization signal and control algolithm of detection
The start pulse signal that delay angle generates the bridge side of starting of static frequency conversion device SFC is sent out, starting of static frequency conversion device SFC is driven
Bridge side silicon-controlled generation need DC voltage and electric current.On-site programmable gate array FPGA is produced also according to synchronization signal
Raw pressure is adopted information-preserving number and is sent to synchronization signal detection plate SU, and pressure adopts information-preserving number for avoiding the silicon-controlled to adopting of triggering SFC bridge side
Sample circuit generates interference, mains voltage signal is not acquired when control machines start, to ensure that synchronization signal detection
Accuracy.
Wherein, the generation of trigger delay angle is realized by the DSP in master board, according to DC current reference value and actual value
Comparison determine trigger delay angle.
Pressure is adopted information-preserving number and is generated by FPGA, takes shielding sampled signal on trigger pulse head point, and other times carry out
Sampled signal.As shown in Fig. 2, allowing pressure to adopt information-preserving number in head pulse is 0, then synchronization signal detection plate SU is without sampling and to letter
It number is kept；Allowing pressure to adopt information-preserving number in other times is 1, then synchronization signal detection plate SU is sampled.
The above, only presently preferred embodiments of the present invention, not to the present invention in any form with substantial limitation,
It should be pointed out that under the premise of not departing from the method for the present invention, can also be made for those skilled in the art
Several improvement and supplement, these are improved and supplement also should be regarded as protection scope of the present invention.All those skilled in the art,
Without departing from the spirit and scope of the present invention, when made using disclosed above technology contents it is a little more
Dynamic, modification and the equivalent variations developed, are equivalent embodiment of the invention；Meanwhile all substantial technologicals pair according to the present invention
The variation, modification and evolution of any equivalent variations made by above-described embodiment, still fall within the range of technical solution of the present invention
It is interior.
Claims (5)
1. a kind of synchronization signal detection circuit based on FPGA, it is characterised in that: including for measuring starting of static frequency conversion device
The voltage collecting device of SFC input side network voltage, voltage collecting device input terminal connect SFC, voltage collecting device output end
The voltage signal inputs of synchronization signal detection plate SU are connected, the scene in the synchronous signal output end connection master board of SU can
The input terminal of gate array FPGA is programmed, the pressure that the pressure of FPGA adopts guarantor's signal output end connection SU adopts guarantor's signal input part.
2. a kind of synchronization signal detection circuit based on FPGA as described in claim 1, it is characterised in that: the voltage acquisition
Device is voltage transformer.
3. a kind of synchronization signal detection circuit based on FPGA as described in claim 1, it is characterised in that: the voltage acquisition
Device is divider resistance.
4. a kind of synchronization signal detection circuit based on FPGA as described in claim 1, it is characterised in that: the SFC's is defeated
The power grid three-phase alternating voltage signal for entering side accesses SU by voltage collecting device；SU generates the three-phase alternating voltage signal
Synchronization signal, and the synchronization signal is sent into the FPGA in master board；FPGA is according to the synchronization signal and trigger delay
Angle generates the start pulse signal of the bridge side of SFC, the DC voltage and electricity for driving the silicon-controlled generation of the bridge side of SFC to need
Stream；FPGA adopts information-preserving number also according to synchronization signal generation pressure and send to SU, and pressure adopts information-preserving number for avoiding triggering SFC bridge side
It is silicon-controlled to sample circuit generate interference, mains voltage signal is not acquired when control machines start, to guarantee to synchronize
The accuracy of signal detection.
5. a kind of synchronization signal detection circuit based on FPGA as claimed in claim 4, it is characterised in that: the pressure is adopted information-preserving
It number is to take shielding sampled signal on trigger pulse head point, and other times carry out sampled signal.
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| CN201811358929.6A CN109374951B (en) | 2018-11-15 | 2018-11-15 | Synchronous signal detection loop based on FPGA |
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|---|---|---|---|---|
| CN1061286A (en) * | 1990-11-05 | 1992-05-20 | 中国科学院武汉岩土力学研究所 | The pile integrity tester that has time function synchronous amplification signal device |
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2018
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