CN109359075A - A kind of system and server improving server data transport stability - Google Patents
A kind of system and server improving server data transport stability Download PDFInfo
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- CN109359075A CN109359075A CN201811295892.7A CN201811295892A CN109359075A CN 109359075 A CN109359075 A CN 109359075A CN 201811295892 A CN201811295892 A CN 201811295892A CN 109359075 A CN109359075 A CN 109359075A
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- clock
- clock buffer
- buffer
- module
- hard disk
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- 238000011094 buffer selection Methods 0.000 claims description 2
- 230000001934 delay Effects 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 abstract description 19
- 238000000034 method Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
- G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
The invention discloses a kind of systems and server for improving server data transport stability, including Clock generation module, for generating the clock signal of predeterminated frequency and clock signal being sent to CPU and clock buffer；Operational mode selecting module, for the clock module of clock buffer to be adjusted to bypass mode；Clock buffer, for clock signal to be pass-through to the output end of clock buffer from the input terminal of clock buffer and is sent to NVMe hard disk.The clock module of clock buffer is adjusted to bypass mode by the application, so that clock signal can be directly pass-through to its output end from its input terminal after receiving clock signal by clock buffer, it ensure that input clock and the output clock of clock buffer are completely the same, namely the reference clock of CPU and NVMe hard disk is completely the same, the correct acquisition and transmitting for ensuring data in signals transmission, so that data transmission has the Stability and veracity of height.
Description
Technical field
The present invention relates to technical field of data transmission, more particularly to it is a kind of improve server data transport stability be
System and server.
Background technique
In server system, in order to pursue higher performance, faster storage and calculating speed, usually using support PCIe
NVMe (the Non- of (peripheral component interconnect express, high-speed serial bus) agreement
Volatile Memory express, Nonvolatile memory host controller interface specification) hard disk.Since PCIe signal is high
Fast signal has special requirement in track lengths, and the distance walked must not be too far away.But NVMe hard disk link all can under normal conditions
NVMe hard disk then is arrived by plate end cabling, cable, link range is all longer, and signal attenuation ratio is more serious.In order to solve this
Problem increases one for enhancing the retimer chip of signal driving capability on storage chains road, also adaptably increases
One clock buffer, retimer chip and clock buffer are located on retimer board.It is carried out between CPU and NVMe hard disk
When data are transmitted, referenced clock is the clock signal that Clock generation module issues, which is directly given to after issuing
Clock buffer on CPU and retimer board, clock is divided into two parts after clock buffer, respectively enters
Retimer chip and NVMe hard disk, in this way, when carrying out data transmission between CPU and NVMe hard disk, the clock of CPU reference is
The clock of the input of clock buffer, the reference of NVMe hard disk is the output of clock buffer, if it is different to output and input clock
It causes, then exception occurs when will lead to data transmission, long-term accumulated can cause disk or delay machine failure.
Therefore, how to guarantee the input clock of clock buffer it is consistent with output clock height be those skilled in the art's mesh
Preceding problem to be solved.
Summary of the invention
The object of the present invention is to provide a kind of systems and server for improving server data transport stability, it is ensured that letter
The correct acquisition and transmitting of data in number transmission process, so that data transmission has the Stability and veracity of height.
In order to solve the above technical problems, the present invention provides a kind of system for improving server data transport stability, packet
It includes:
Clock generation module, for generate predeterminated frequency clock signal and by the clock signal be sent to CPU and when
Clock buffer；
The operational mode selecting module that output end is connect with the clock module control terminal of the clock buffer is used for institute
The clock module for stating clock buffer is adjusted to bypass mode；
Input terminal is connect with the output end of the Clock generation module, the clock of output end and NVMe hard disk connection is slow
Device is rushed, for the clock signal to be pass-through to the output end of the clock buffer simultaneously from the input terminal of the clock buffer
It is sent to the NVMe hard disk.
Preferably, the Clock generation module is south bridge.
Preferably, the predeterminated frequency is 100Hz.
Preferably, the clock buffer is the clock buffer of model 9DB833；
The operational mode selecting module includes pull down resistor, the first end ground connection of the pull down resistor, the drop-down electricity
The second end of resistance is connect with the operational mode of clock buffer selection pin；
The resistance value of the pull down resistor is less than preset value.
Preferably, the resistance value of the pull down resistor is 4.7k Ω.
In order to solve the above technical problems, the present invention also provides a kind of server, including CPU, NVMe hard disk, further include as
The system of raising server data transport stability described above.
The clock module of clock buffer is adjusted to bypass mode by the application, so that clock buffer is when receiving
Clock signal can be directly pass-through to its output end from its input terminal after clock signal, ensure that clock buffer input clock and
Export that clock is completely the same namely the reference clock of CPU and NVMe hard disk is completely the same, it is ensured that data in signals transmission
It is correct acquisition and transmitting so that data transmission have height Stability and veracity, avoid in transmission process because of error correction
Phenomenon and occupy resource, improve the storage and calculated performance of the readwrite performance and server of hard disk.
Detailed description of the invention
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to institute in the prior art and embodiment
Attached drawing to be used is needed to be briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the invention
Example, for those of ordinary skill in the art, without creative efforts, can also obtain according to these attached drawings
Obtain other attached drawings.
Fig. 1 is a kind of structural schematic diagram of system for improving server data transport stability provided by the invention；
Fig. 2 is a kind of specifically structural representation of system for improving server data transport stability provided by the invention
Figure；
Fig. 3 is the input signal and signal output waveform figure using the clock buffer of pll clock mode；
Fig. 4 is the input signal and signal output waveform figure using the clock buffer of bypass clock module.
Specific embodiment
Core of the invention is to provide a kind of system and server for improving server data transport stability, it is ensured that letter
The correct acquisition and transmitting of data in number transmission process, so that data transmission has the Stability and veracity of height.
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
Fig. 1 is please referred to, Fig. 1 is that a kind of structure of system for improving server data transport stability provided by the invention is shown
It is intended to, which includes:
Clock generation module 1, for generating the clock signal of predeterminated frequency and clock signal being sent to CPU and clock delays
Rush device 3；
The operational mode selecting module 2 that output end is connect with the clock module control terminal of clock buffer 3 is used for clock
The clock module of buffer 3 is adjusted to bypass mode；
The clock buffer 3 that input terminal is connect with the output end of Clock generation module 1, output end and NVMe hard disk connect,
For clock signal to be pass-through to the output end of clock buffer 3 from the input terminal of clock buffer 3 and is sent to NVMe hard disk.
Specifically, clock signal is sent to by Clock generation module 1 simultaneously after the clock signal for generating predeterminated frequency
The input terminal of CPU and clock buffer 3, so that clock signal is consistent on source.2 meeting of operational mode selecting module
The clock module of clock buffer 3 is adjusted to bypass mode in advance, in this way, the input terminal of clock buffer 3 is receiving
Clock signal can be directly transparent to output end after clock signal, to guarantee clock signal in the input terminal of clock buffer 3
It is completely the same with output end, because of error in data caused by clock drift when thoroughly eliminating data transmission.Clock buffer 3 is being incited somebody to action
Clock signal can be sent to NVMe hard disk after being pass-through to its output end from its input terminal by clock signal, ensure that CPU and NVMe
The reference clock of hard disk is completely the same, it is ensured that the correct acquisition and transmitting of data in signals transmission, so that data are transmitted
Stability and veracity with height avoids in transmission process and occupies resource because of error correction phenomenon, improves the reading of hard disk
The storage and calculated performance of write performance and server.
As a kind of preferred embodiment, Clock generation module 1 is south bridge.
Specifically, clock signal is generated using south bridge in the application, it is of course also possible to use other kinds of clock is sent out
Raw module 1 or other kinds of Clock generation module are determined according to the actual situation.As a kind of preferred embodiment,
Predeterminated frequency is 100Hz, it is of course also possible to be other frequencies, is needed according to the data transmission between CPU and NVMe hard disk to set
It is fixed.
As a kind of preferred embodiment, clock buffer 3 is the clock buffer 3 of model 9DB833；
Operational mode selecting module 2 includes pull down resistor, and the first end of pull down resistor is grounded, the second end of pull down resistor with
The operational mode selection pin connection of clock buffer 3；
The resistance value of pull down resistor is less than preset value.
Referring to figure 2., Fig. 2 be it is provided by the invention it is a kind of improve server data transport stability system specifically
Structural schematic diagram.
Specifically, the clock buffer 3 of 9DB833 model is selected in the present embodiment, at this point, connecting by a pull down resistor
It is connected to its BYP_LOBW_HIBW pin, so that the clock module of selected clock buffer 3 is bypass mode.Under guaranteeing
Effect is drawn, the resistance value of pull down resistor here is eligible smaller.As a kind of preferred embodiment, the resistance value of pull down resistor
For 4.7k Ω.Certainly, the resistance value of pull down resistor here can also be the resistance value of other numerical value, meet the needs of the application i.e.
It can.
It should also be noted that, in the prior art when in use clock buffer 3 when would generally select PLL
(PhaseLockedLoop, phaselocked loop) mode, but can be made using this kind of mode
Referring to figure 3. and Fig. 4, Fig. 3 is using the input signals and output signal wave of the clock buffer of pll clock mode
Shape figure, Fig. 4 are the input signal and signal output waveform figure using the clock buffer of bypass clock module.
From figure 3, it can be seen that using pll clock mode clock buffer 3 when, the clock signal at the end CPU is frequency
Range and for NVMe hard disk end is then the fixed frequency of a 99.75MHz in the clock signal of 99.5MHz-100MHz
Rate, causing the rising edge for acquiring data when data are transmitted possibly can not be aligned, (such as the frequency of the clock signal at the end CPU is
99.5Hz), and then cause data transmission fault.Using bypass clock module clock buffer 3 when, by clock buffer 3
Clock module be changed to bypass, the clock signal of input can be pass-through to output end by this mode so that input and output believe
The frequency range of number completely the same namely NVMe hard disk clock signal also in 99.5MHz-100MHz so that CPU and
The frequency range of the clock signal of NVMe hard disk is identical, and the clock signal of the two is at every moment also identical, such as the clock of the two
Signal is at a time 99.5Hz or is simultaneously at a time 99.75Hz simultaneously, finally to pass between CPU and hard disk
The clock referred to when transmission of data is completely the same, realizes the correct acquisition of data.
It further include such as above-mentioned raising server count the present invention also provides a kind of server, including CPU, NVMe hard disk
According to the system of transmission stability.
The above system embodiment please referred to for the introduction of system in server provided by the invention, the application is herein no longer
It repeats.
It should be noted that in the present specification, relational terms such as first and second and the like are used merely to one
A entity or operation with another entity or operate distinguish, without necessarily requiring or implying these entities or operation it
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant are intended to
Cover non-exclusive inclusion, so that the process, method, article or equipment for including a series of elements not only includes those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or setting
Standby intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in the process, method, article or apparatus that includes the element.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (6)
1. a kind of system for improving server data transport stability characterized by comprising
Clock generation module, for generating the clock signal of predeterminated frequency and the clock signal being sent to CPU and clock delays
Rush device；
The operational mode selecting module that output end is connect with the clock module control terminal of the clock buffer, for will be described when
The clock module of clock buffer is adjusted to bypass mode；
The clock buffer that input terminal is connect with the output end of the Clock generation module, output end and NVMe hard disk connect
Device, the output end for the clock signal to be pass-through to the clock buffer from the input terminal of the clock buffer are concurrent
It send to the NVMe hard disk.
2. the system as claimed in claim 1, which is characterized in that the Clock generation module is south bridge.
3. the system as claimed in claim 1, which is characterized in that the predeterminated frequency is 100Hz.
4. system as described in any one of claims 1-3, which is characterized in that the clock buffer is model 9DB833's
Clock buffer；
The operational mode selecting module includes pull down resistor, the first end ground connection of the pull down resistor, the pull down resistor
Second end is connect with the operational mode of clock buffer selection pin；
The resistance value of the pull down resistor is less than preset value.
5. system as claimed in claim 4, which is characterized in that the resistance value of the pull down resistor is 4.7k Ω.
6. a kind of server, which is characterized in that further include as described in any one in claim 1-5 including CPU, NVMe hard disk
The system for improving server data transport stability.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811295892.7A CN109359075A (en) | 2018-11-01 | 2018-11-01 | A kind of system and server improving server data transport stability |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811295892.7A CN109359075A (en) | 2018-11-01 | 2018-11-01 | A kind of system and server improving server data transport stability |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109359075A true CN109359075A (en) | 2019-02-19 |
Family
ID=65343668
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811295892.7A Withdrawn CN109359075A (en) | 2018-11-01 | 2018-11-01 | A kind of system and server improving server data transport stability |
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| Country | Link |
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| CN (1) | CN109359075A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109918329A (en) * | 2019-02-28 | 2019-06-21 | 苏州浪潮智能科技有限公司 | A kind of communication system and communication means configuring Retimer chip |
-
2018
- 2018-11-01 CN CN201811295892.7A patent/CN109359075A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109918329A (en) * | 2019-02-28 | 2019-06-21 | 苏州浪潮智能科技有限公司 | A kind of communication system and communication means configuring Retimer chip |
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Application publication date: 20190219 |