CN109359059A - A method of reducing the erasable number of low power consuming devices Flash - Google Patents
A method of reducing the erasable number of low power consuming devices Flash Download PDFInfo
- Publication number
- CN109359059A CN109359059A CN201811194353.4A CN201811194353A CN109359059A CN 109359059 A CN109359059 A CN 109359059A CN 201811194353 A CN201811194353 A CN 201811194353A CN 109359059 A CN109359059 A CN 109359059A
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- CN
- China
- Prior art keywords
- erasable
- flash
- 0xff
- equal
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 11
- 230000004044 response Effects 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
A method of the erasable number reducing low power consuming devices Flash includes the following steps: that (1) obtains user's addressing space [M, N] of current Flash；(2) the half m=(x+y)/2 of current addressing space is calculated；(3) data of continuous 4 bytes under the address m are obtained；(4) whether the numerical value for judging the data of continuous 4 bytes under the address m is 0xFF, if being all 0xFF, enables y=(x+y)/2, returns to step (2), if being not all 0xFF, judges whether x is equal to y；(5) if x is not equal to y, x=(x+y)/2 is enabled, (2) are returned to step, if x is equal to y, continue to execute step (6)；(6) it determines and needs the erasable section Flash [M, x], carry out erasable operation to erasable section to identified.The present invention only carries out erasable operation to the storage section occupied, promotes response speed.
Description
Technical field
The present invention relates to Flash technology field, especially a kind of side for the erasable number for reducing low power consuming devices Flash
Method.
Background technique
Flash is one kind of storage chip, is often expressed as the meaning of Flash Memory in electronics and semiconductor field
Think, i.e. usually described " flash memory ", is named as Flash EEPROM Memory entirely.For the Flash of many low capacities, need through
It often carries out erasable.In the prior art, frequently with complete erasable erasable mode, i.e., each storage section of Flash is wiped
It writes, and low capacity Flash is usually uniprocessor, uniprocessor needs to be lined up carries out erasable operation one by one, thus causes to ring
Answer speed very slow.
Summary of the invention
The present invention provides a kind of method of erasable number for reducing low power consuming devices Flash, only to the memory block occupied
Between carry out erasable operation, promote response speed.
The present invention provides a kind of method of erasable number for reducing low power consuming devices Flash, includes the following steps:
(1) user's addressing space [M, N] of current Flash is obtained；
(2) the half m=(x+y)/2 of current addressing space is calculated；
(3) data of continuous 4 bytes under the address m are obtained；
(4) whether the numerical value for judging the data of continuous 4 bytes under the address m is 0xFF, if being all 0xFF, enables y=(x+
Y)/2, (2) are returned to step, if being not all 0xFF, judge whether x is equal to y；
(5) if x is not equal to y, x=(x+y)/2 is enabled, (2) are returned to step, if x is equal to y, continue to execute step
(6)；
(6) it determines and needs the erasable section Flash [M, x], carry out erasable operation to erasable section to identified.
Preferably, the M is the start address of addressing space, and the N is the end address of addressing space.
In the present invention, by gradually reducing addressing space, finds the storage section occupied and carry out erasable operation, and it is right
Null value section can greatly promote response speed without erasable operation.
Detailed description of the invention
Fig. 1 is the flow chart of the method for the erasable number of the reduction low power consuming devices Flash of an embodiment of the present invention.
Specific embodiment
Below by specific embodiment combination attached drawing, invention is further described in detail.
The embodiment of the present invention provides a kind of method of erasable number for reducing low power consuming devices Flash, as shown in Figure 1, its
Include the following steps:
(1) user's addressing space [M, N] of current Flash is obtained.
When processor needs to carry out erasable operation to Flash, can poll Flash memory space, to determine seeking for Flash
Location space, or the information data of Flash is read, to determine the addressing space of Flash, which describes Flash's
Read-write frequency, addressing space, the data such as model.It is hereby achieved that the addressing space [M, N] of current Flash.
(2) the half m=(x+y)/2 of current addressing space is calculated.
According to acquired addressing space, addressing space half address position m=(x+y)/2, initial shape are calculated
Under state, m is the half of addressing space, and the subsequent variation with x value and y value also changes therewith.
(3) data of continuous 4 bytes under the address m are obtained.
After having calculated the address m, since the address m, the data in the memory space of 4 bytes are continuously obtained, for after
Continuous step is implemented.
(4) whether the numerical value for judging the data of continuous 4 bytes under the address m is 0xFF, if being all 0xFF, enables y=(x+
Y)/2, (2) are returned to step, if being not all 0xFF, judge whether x is equal to y.
In the case where obtaining the address m after the data of continuous 4 bytes, the whether all 0xFF of these data are judged, i.e. judgement is
No all null values.Since the storage of data is stored backward one by one from start address, it is all 0xFF expression and does not store data,
Need to find the start address for not storing data.If being all 0xFF, y=(x+y)/2 is enabled, reduces the range of lookup, is returned
It executes step (2) and further judges whether x is equal to y if being not all 0xFF.
(5) if x is not equal to y, x=(x+y)/2 is enabled, (2) are returned to step, if x is equal to y, continue to execute step
(6)。
It is x assignment, x=(x+y)/2, and return to step (2) if x is not equal to y.If x is equal to y, illustrate to have looked for
To the start address for not storing data, then step (6) are continued to execute.
(6) it determines and needs the erasable section Flash [M, x], carry out erasable operation to erasable section to identified.
It determines and needs the erasable section Flash [M, x], only carry out erasable operation to erasable section to identified, other
The section Flash is without erasable operation, to effectively reduce erasable number, can greatly promote the response speed of Flash.
Wherein, the M and N of above-mentioned addressing space, respectively indicates are as follows: the M is the start address of addressing space, and the N is
The end address of addressing space.
The above content is specific embodiment is combined, further detailed description of the invention, and it cannot be said that this hair
Bright specific implementation is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs, it is not taking off
Under the premise of from present inventive concept, a number of simple deductions or replacements can also be made.
Claims (2)
1. a kind of method for the erasable number for reducing low power consuming devices Flash, which comprises the steps of:
(1) user's addressing space [M, N] of current Flash is obtained；
(2) the half m=(x+y)/2 of current addressing space is calculated；
(3) data of continuous 4 bytes under the address m are obtained；
(4) whether the numerical value for judging the data of continuous 4 bytes under the address m is 0xFF, if being all 0xFF, enable y=(x+y)/
2, (2) are returned to step, if being not all 0xFF, judge whether x is equal to y；
(5) if x is not equal to y, x=(x+y)/2 is enabled, (2) are returned to step, if x is equal to y, continue to execute step (6)；
(6) it determines and needs the erasable section Flash [M, x], carry out erasable operation to erasable section to identified.
2. according to the method described in claim 1, it is characterized by:
The M is the start address of addressing space, and the N is the end address of addressing space.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811194353.4A CN109359059A (en) | 2018-10-15 | 2018-10-15 | A method of reducing the erasable number of low power consuming devices Flash |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811194353.4A CN109359059A (en) | 2018-10-15 | 2018-10-15 | A method of reducing the erasable number of low power consuming devices Flash |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109359059A true CN109359059A (en) | 2019-02-19 |
Family
ID=65349291
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811194353.4A Pending CN109359059A (en) | 2018-10-15 | 2018-10-15 | A method of reducing the erasable number of low power consuming devices Flash |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109359059A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6222779B1 (en) * | 1998-04-24 | 2001-04-24 | Kabushiki Kaisha Toshiba | Semiconductor storage device with automatic write/erase function |
| CN1567367A (en) * | 2003-07-04 | 2005-01-19 | 上海华园微电子技术有限公司 | Memory construction of smart card and control method thereof |
| US20060171213A1 (en) * | 2005-01-18 | 2006-08-03 | Stmicroelectronics S.R.L. | Control of voltages during erase and re-program operations of memory cells |
| US20150161040A1 (en) * | 2013-12-09 | 2015-06-11 | Silicon Motion, Inc. | Data-storage device and data erasing method |
| CN104820641A (en) * | 2015-04-16 | 2015-08-05 | 上海冉能自动化科技有限公司 | Method for reducing FLASH erasure frequency |
| CN106293532A (en) * | 2016-08-10 | 2017-01-04 | 广东佳禾声学科技有限公司 | A kind of Flash data storage method |
-
2018
- 2018-10-15 CN CN201811194353.4A patent/CN109359059A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6222779B1 (en) * | 1998-04-24 | 2001-04-24 | Kabushiki Kaisha Toshiba | Semiconductor storage device with automatic write/erase function |
| CN1567367A (en) * | 2003-07-04 | 2005-01-19 | 上海华园微电子技术有限公司 | Memory construction of smart card and control method thereof |
| US20060171213A1 (en) * | 2005-01-18 | 2006-08-03 | Stmicroelectronics S.R.L. | Control of voltages during erase and re-program operations of memory cells |
| US20150161040A1 (en) * | 2013-12-09 | 2015-06-11 | Silicon Motion, Inc. | Data-storage device and data erasing method |
| CN104820641A (en) * | 2015-04-16 | 2015-08-05 | 上海冉能自动化科技有限公司 | Method for reducing FLASH erasure frequency |
| CN106293532A (en) * | 2016-08-10 | 2017-01-04 | 广东佳禾声学科技有限公司 | A kind of Flash data storage method |
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| PB01 | Publication | ||
| PB01 | Publication | ||
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190219 |
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| RJ01 | Rejection of invention patent application after publication |