CN109358978A - A kind of NAND FLASH error control method based on polarization code and metadata information - Google Patents
A kind of NAND FLASH error control method based on polarization code and metadata information Download PDFInfo
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- CN109358978A CN109358978A CN201810962407.0A CN201810962407A CN109358978A CN 109358978 A CN109358978 A CN 109358978A CN 201810962407 A CN201810962407 A CN 201810962407A CN 109358978 A CN109358978 A CN 109358978A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
Abstract
The present invention provides a kind of NAND FLASH error control method based on polarization code and metadata information, is related to technical field of information storage.Information sequence is first subjected to CRC coding, obtain CRC code word, then the metadata information stored in NAND FLASH as information sequence, it integrates CRC code word and metadata information obtains information bit to be encoded, carry out Polar coding, obtain Polar code word, polarisation channel where metadata information in Polar code word is divided into and freezes bit channel, a new Polar code word is obtained, is punchinged to the code word, the high code rate Polar code suitable for NAND FLASH is constructed.The present invention solves the technical issues of NAND FLASH that Polar code word in the prior art is not directly adaptable to use any page capacity.The invention has the following beneficial effects: improving the error-correcting performance of NAND FLASH error correction procedure.
Description
Technical field
The present invention relates to technical field of information storage, more particularly, to a kind of poor to NAND FLASH using polarization code realization
The method of mistake control.
Background technique
With the increase of NAND FLASH storage density, there is mistake when executing write-in, read operation to NAND FLASH
Probability can also increase therewith, therefore NAND FLASH needs to guarantee using error correcting code the reliability of storing data.It is Chinese special
Sharp application publication number CN103218271A, data of publication of application on 07 24th, 2013, entitled " a kind of data error-correcting method and dress
Set " application for a patent for invention file, disclose the method and apparatus that the data read in a kind of NAND Flash carry out error correction.Side
Method includes: that the N kind verification data of requested data and the requested date are read from memory；Wherein, N is greater than 1
Positive integer, and N kind verification data be capable of error correction data bits it is different；According to N kind verification data error correction digit by less to
More sequences successively carries out error correction to requested data using verification data not of the same race, in using N kind verification data
A kind of verification data error correction completed to requested data, or until using the most verification data of error correction digit to requested
Correcting data error failure.This method needs to generate N kind verification data, and this N kind verification data require to be stored in NAND
In FLASH, but it is not that each data can all be used, will cause the waste of NAND FLASH memory space in this way.Polar code
(polarization code) has fixed coding structure and lower encoding and decoding complexity, therefore has received widespread attention, in NAND
In FLASH, other than storing relevant information data, dedicated Flash File System (Flash is also stored
Translation Layer, FTL) and the information such as logical physical address of cache, these data informations are referred to as metadata letter
Breath, metadata information be for encoder and decoder it is known, Polar code encode during can use first number
It is believed that cease to improve error-correcting performance, but the coding mode of Polar code determines that it is not directly adaptable to use any page capacity
NAND FLASH, because the code length of Polar code is 2 power, and NAND FLASH page capacity is not 2 power, in order to make
Polar code is suitable for the NAND FLASH of any page capacity, needs to construct a kind of code-rate-compatible and has more preferable error-correcting performance
Polar code scheme.
Summary of the invention
In order to solve the technology that Polar code word in the prior art is not directly adaptable to use the NAND FLASH of any page capacity
Problem, the present invention provides a kind of NAND FLASH error control method based on polarization code and metadata information, for improving
The error-correcting performance of NAND FLASH error correction procedure.
The technical scheme is that a kind of Error Control side NAND FLASH based on polarization code and metadata information
Method: step 1: the information sequence that length is kbits is subjected to CRC coding, the CRC check factor of a rbits is added, obtains
CRC code word；Step 2: the free ratio that the metadata information stored in CRC code word and NAND FLASH forms Polar code word is integrated
Spy, is denoted as payload, and the total length of payload is K；Step 3: setting the number of polarisation channel as N, to N number of polarisation channel into
Row reliablity estimation, and be arranged successively according to sequence from big to small, the higher preceding K serial number of reliability is selected, by free ratio
Before spy is sequentially mapped to according to the sequence of metadata information after first CRC code word in the corresponding polarisation channel of K serial number, carry out
Polar coding, obtains Polar code word (N, K)；Step 4: in the free bit of Polar code (N, K) select Q reliability compared with
Low channel constructs a new Polar code, is denoted as (N, K-Q) as bit is freezed；Step 5: to the Polar of neotectonics
Code (N, K-Q) is punchinged, and the Polar code (N suitable for NAND FLASH is constructed1, K-Q) and store to NAND FLASH
In, and the error probability of each polarisation channel is set as Pe (ui)；Step 6: it is read from the Flash page that NAND FLASH is specified
The Polar code for taking storage is inserted into corresponding value at corresponding position, obtains word to be decoded according to the information of the bit chiseled out
y1 N(N,K-Q)；Step 7: with CA-SCL decoding algorithm to word y to be decoded1 N(N, K-Q) decoding, obtains coding sequenceStep
Eight: from coding sequenceThe information sequence of the middle kbits for taking out most original.
Preferably, the metadata information stored in NAND FLASH is contained for encoder and decoding in step 2
It is known dedicated Flash File System and logical physical address mapping information for device.
Preferably, remaining N-K polarisation channel transmission is to freeze bit in step 3.
Preferably, the error probability for freezing bit channel chiseled out meets in step 5:
Preferably, in step 5, Polar code (N1, K-Q) and it is stored in NAND FLASH, CRC code word is stored in NAND
The data field of FLASH, remaining bit storage of freezing is in the redundant area of NAND FLASH.
Compared with prior art, the beneficial effects of the present invention are: using NAND FLASH intrinsic metadata information as
The a part for inputting information data carries out Polarization Coding, in the channel transmission metadata information as bit channel is freezed, leads to
Crossing, which reduces code rate, achievees the purpose that promote decoding error-correcting performance.In addition, first carrying out CRC volume to the information sequence for really needing transmission
Code is carrying out Polar coding, by carrying out CRC check to the sequence after decoding during CA-SCL decoding, can pick out
Not only meet CRC check but also met the lesser optimal decoding path of path measurements value, and also reach the mesh for promoting decoding error-correcting performance
's.
Detailed description of the invention
Attached drawing 1 is flow chart of the present invention；
Attached drawing 2 is the composed structure schematic diagram of information bit to be encoded；
Attached drawing 3 is the distribution map of channel reliablity estimation；
Attached drawing 4 is the composed structure schematic diagram of Polar code word；
Attached drawing 5 is the composed structure schematic diagram of low bit- rate Polar code word；
Attached drawing 6 is the composed structure schematic diagram of the high code rate Polar code word suitable for NAND FLASH.
Specific embodiment
Below with reference to the embodiments and with reference to the accompanying drawing the technical solutions of the present invention will be further described.
Embodiment 1:
As shown in figures 1 to 6, a kind of NAND FLASH error control method based on polarization code and metadata information, step 1: will
Length is the information sequence M { m of k bits1,m2,K,mkCRC coding is carried out, the CRC check factor of a rbits is added, is obtained
CRC code word.
Step 2: it can use metadata information during Polar code coding to improve error-correcting performance, NAND
It is known dedicated Flash file system that the metadata information stored in FLASH, which contains for encoder and decoder,
System and logical physical address mapping information.The logical physical address mapping information stored in NAND FLASH (is denoted as LBA, length
Degree is k ' bits) and dedicated FTL information (being denoted as SUP, length is k ' bits) as a part of input information, and total length is denoted as
Q, wherein Q=k '+k " integrates the free bit that CRC code word, LBA and SUP form Polar code word, is denoted as payload,
The total length of payload is K, wherein K=k+r+Q, as shown in Figure 2.
Step 3: the number of polarisation channel is set as N.Using the reliability of Gaussian approximation estimation channel, and according to from big
It is arranged successively to small sequence, the higher preceding K serial number of reliability is selected, by free bit according to metadata after first CRC code word
Before the sequence of information is sequentially mapped in the corresponding polarisation channel of K serial number, remaining N-K polarisation channel transmission is to freeze
Bit, wherein the higher error probability for indicating channel of the reliability of channel is smaller, as shown in Figure 3.The output of this step is to compile
The original bit u of code1 N, to u1 NCarry out Polar coding.Coding mode are as follows: x1 N=u1 NGN, wherein GNFor the generation square of polarization code
Battle array,BNFor bit reversal matrix, RNFor odd even reorder matrix.Bit position is freezed in expression,It indicates certainly
By the position of bit, it isSupplementary set,For the symbol list entries of encoder, x1 N@{x1,x2,L,xNIt is to compile
Sequence after code, is denoted as (N, K), wherein N is the total length of Polar code word, and K is the total length of information sequence, code rate R1=
The Polar codeword structure of K/N, generation are as shown in Figure 4.
Step 4: in the free bit A@{ a of Polar code (N, K)1,a2,L,aKA reliably highly lower (mistake of middle selection Q
Accidentally probability is larger) channel as bit is freezed, construct a new Polar code, be denoted as (N, K-Q).Newly-generated low bit- rate
Polar codeword structure is as shown in Figure 5.Wherein,Bit position is freezed in expression,Indicate free bit position, code rate R2=(K-Q)/N.
Step 5: in order to obtain the high code rate Polar code for being suitable for NAND FLASH, to Polar code (N, the K- of neotectonics
Q it) punchinges.If the error probability of each polarisation channel is Pe (ui), then the error probability for freezing bit channel chiseled out is full
Foot:The error probability for freezing bit channel chiseled out is minimum value, constructs and is suitable for
Polar code (the N of NAND FLASH1, K-Q), code rate R3=(K-Q)/N1, wherein needing to dig the number of bits gone is N-N1, such as
Shown in Fig. 6.The code word is stored in the specified Flash page of NAND FLASH, wherein CRC code word storage to NAND
The data field of FLASH, remaining bit storage of freezing is in the redundant area of NAND FLASH.
Step 6: the Polar code (N of storage is read from the Flash page that NAND FLASH is specified1,K-Q).According to chisel
The information of the bit fallen is inserted into corresponding value at corresponding position.The bit chiseled out in step 5 is actually not
Transmission, but receiving end these puncture bits channels can be considered as capacity be 0 channel, that is, puncture bits can be considered as by
It transmits, the channel for being only 0 in capacity.So can be in the N-N chiseled out1It is filled at the position of a bit corresponding
Value, i.e., N-N1A polarisation channel fills metadata information according to the descending arrangement of reliability, preceding Q polarisation channel, remaining
Polarisation channel fill 0, obtain word y to be decoded1 N(N, K-Q), R2=(K-Q)/N.
Step 7: with CA-SCL decoding algorithm to word y to be decoded1 N(N, K-Q) decoding, obtains coding sequence
Step 8: from coding sequenceThe information sequence of the middle kbits for taking out most original
It is illustrated below with reference to model MT29F128G08CBCAB chip:
MT29F128G08CBCAB chip total capacity is (128G+9728M) bits, and every is divided into 2048 pieces, and every piece is divided into 512
Page, every page includes the data field 16kByte capacity and 1216Byte redundancy size.If directlying adopt a page capacity (16k+1216)
For Byte as code length, then memory capacity needed for coding and decoding is excessive, therefore splits into (16k+1216) Byte in the present embodiment
512 sections, the redundant area of every section of data field and 16bits that will be assigned to 256bits, i.e., every section needs to construct (272,256)
Polar code word, then writes into page together.
Step 1: the information sequence M { m for being 240bits to length1,m2,K,m240Use g (D)=D16+D15+D2+ 1
Generator polynomial carries out CRC coding, that is, adds the CRC check factor of a 16bits, obtain CRC code word.
Step 2: the logical physical address mapping information (being denoted as LBA) and dedicated FTL information stored in NAND FLASH
(being denoted as SUP) LBA and SUP and is all made of 4 i.e. 32bits of byte in the present embodiment as a part of input information to remember
Record, total length Q are equal to 64bits, integrate the free bit that CRC code word, LBA and SUP form Polar code word, are denoted as payload,
The total length of payload is 320bits.
Step 3: being 320bits according to the total length of payload, it is assumed that N is greater than the minimum 2 to payload total length
Power, i.e. N takes 512.First with the reliability of Gaussian approximation estimation channel, and successively arranged according to sequence from big to small
Column, select higher preceding 320 serial numbers of reliability, by free bit according to metadata information after first CRC code word sequence successively
It is mapped in the corresponding polarisation channel of preceding 320 serial numbers, remaining 192 polarisation channels transmission is to freeze bit.This step
Output be coding original bit u1 N, to u1 NCarry out Polar coding.Coding mode are as follows: x1 N=u1 NGN, wherein GNFor pole
Change the generator matrix of code,BNFor bit reversal matrix, RNSquare is reset for odd even
Battle array.Bit position is freezed in expression,Table
The position for showing free bit isSupplementary set,For the symbol list entries of encoder, x1 N@{x1,x2,L,xN}
For the sequence after coding, it is denoted as (512,320), code rate 0.625.
Step 4: in the free bit A@{ a of Polar code1,a2,L,aK64 lower (error probabilities of reliability of middle selection
It is larger) channel construct a new Polar code them as bit channel is freezed, be denoted as (512,320-64), code rate
It is 0.5, whereinBit position is freezed in expression,Indicate free bit position.
Step 5: it punchinges to the Polar code (512,320-64) of neotectonics.Selection 240 can in freezing bit
By spend higher (error probability is smaller) bit channel chisel out, construct suitable for NAND FLASH Polar code (272,256,
240), wherein 240 indicate to need to dig the number of bits gone, NAND FLASH then is arrived in Polar code (272,256,240) storage
In specified Flash page, the position of storage is determined by LBA.At this point, in NAND FLASH data field store be 256bits
CRC code word, redundant area storage is 16bits the bit that freezes, i.e. check bit, neotectonics suitable for NAND FLASH's
The code rate of Polar code word is 0.941.
Step 6: reading the Polar code (272,256,240) of storage from the Flash page that NAND FLASH is specified,
According to the information of 240 bits chiseled out, corresponding value is inserted at corresponding position, i.e., 240 polarisation channels according to can
By spending descending arrangement, preceding 64 polarisation channels fill metadata information, and remaining polarisation channel fills 0, obtains to be decoded
Word y1 N(512,256), code rate at this time are 0.5.
Step 7: using CA-SCL decoding algorithm to code word y1 NIt is decoded, obtains coding sequence
Step 8: from coding sequenceThe information sequence of the middle 240bits for taking out most original
Claims (5)
1. a kind of NAND FLASH error control method based on polarization code and metadata information, which is characterized in that include the following:
Step 1: the information sequence that length is kbits is subjected to CRC coding, the CRC check factor of a rbits is added, obtains CRC
Code word；Step 2: integrating the free bit that the metadata information stored in CRC code word and NAND FLASH forms Polar code word,
It is denoted as payload, the total length of payload is K；Step 3: the number of polarisation channel is set as N, carrying out to N number of polarisation channel can
Estimate by degree, and be arranged successively according to sequence from big to small, selects the higher preceding K serial number of reliability, free bit is pressed
It is sequentially mapped in the corresponding polarisation channel of preceding K serial number according to the sequence of metadata information after first CRC code word, carries out Polar volume
Code, obtains Polar code word (N, K)；Step 4: the lower letter of Q reliability is selected in the free bit of Polar code (N, K)
Road constructs a new Polar code, is denoted as (N, K-Q) as bit is freezed；Step 5: to the Polar code of neotectonics (N,
K-Q it) punchinges, constructs the Polar code (N suitable for NAND FLASH1, K-Q) and store into NAND FLASH, and set
The error probability of each polarisation channel is Pe (ui)；Step 6: storage is read from the Flash page that NAND FLASH is specified
Polar code be inserted into corresponding value at corresponding position, obtain word y to be decoded according to the information of the bit chiseled out1 N(N,K-
Q)；Step 7: with CA-SCL decoding algorithm to word y to be decoded1 N(N, K-Q) decoding, obtains coding sequenceStep 8: from translating
Code sequenceThe information sequence of the middle kbits for taking out most original.
2. a kind of NAND FLASH error control method based on polarization code and metadata information according to claim 1,
It is characterized by: the metadata information stored in NAND FLASH contains for encoder and decoder in step 2
It is known dedicated Flash File System and logical physical address mapping information.
3. a kind of NAND FLASH error control method based on polarization code and metadata information according to claim 1,
It is characterized by: remaining N-K polarisation channel transmission is to freeze bit in step 3.
4. a kind of NAND FLASH error control method based on polarization code and metadata information according to claim 1,
It is characterized by: the error probability for freezing bit channel chiseled out meets in step 5:
5. a kind of NAND FLASH error control method based on polarization code and metadata information according to claim 1,
It is characterized by: in step 5, Polar code (N1, K-Q) and it is stored in NAND FLASH, CRC code word is stored in NAND FLASH
Data field, remaining bit storage of freezing is in the redundant area of NAND FLASH.
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