CN109347352A - Cascade converter submodule capacitor voltage balance control method - Google Patents
Cascade converter submodule capacitor voltage balance control method Download PDFInfo
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- CN109347352A CN109347352A CN201811394442.3A CN201811394442A CN109347352A CN 109347352 A CN109347352 A CN 109347352A CN 201811394442 A CN201811394442 A CN 201811394442A CN 109347352 A CN109347352 A CN 109347352A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
- H02M7/4835—Converters with outputs that each can have more than two voltages levels comprising two or more cells, each including a switchable capacitor, the capacitors having a nominal charge voltage which corresponds to a given fraction of the input voltage, and the capacitors being selectively connected in series to determine the instantaneous output voltage
Abstract
The present invention provides a kind of cascade converter submodule capacitor voltage balance control methods, comprising: determines the asynchronous switch periods division mode of each submodule in cascade converter；The capacitance voltage disturbance quantity of each submodule is ranked up trigger pulse in the cascade converter being calculated according to sampling；The capacitance voltage for the cascade converter submodule that sampling obtains is ranked up；Calculate cascade converter submodule capacitor voltage degree of unbalancedness；Finally the trigger pulse of cascade converter submodule is redistributed.The present invention is suitable for various cascade converters and its corresponding operating condition, can efficiently realize the balance control of submodule capacitor voltage, realize simple and have preferable counterbalance effect.
Description
Technical field
The present invention relates to power electronics fields, and in particular, to a kind of cascade converter submodule capacitor voltage
Balance control method.
Background technique
Cascade converter has good expandable type and preferable output characteristics, be widely used in various,
High-power transformation of electrical energy occasion, such as flexible DC transmission, reactive power compensator, energy storage, generation of electricity by new energy, motor driven
Deng.Since cascade converter operating condition is complicated, charge-discharge energy, loss and capacitance of submodule capacitor etc. are had differences, and are easy
Cause each submodule capacitor voltage uneven, reduce the output performance of cascade converter, even resulted in when serious system without
Method securely and reliably works, it is therefore necessary to be balanced control to capacitance voltage.
Modulator approach suitable for cascade converter mainly has nearest level to approach modulation (NLC), phase-shifting carrier wave pulsewidth tune
Make (CPS-PWM) and carrier wave stacking pulsewidth modulation modulation (PD-PWM).Compared to NLC modulation and PD-PWM modulation, CPS-
The modulation of PWM phase-shifting carrier wave has the advantages such as the switching frequency of better harmonic characterisitic, faster response speed and fixation, extensive
Using especially in the relatively small number of cascade converter application of number of modules.
It is broadly divided at present suitable for the submodule capacitor voltage balance control technology of CPS-PWM phase-shifting carrier wave modulator approach
Two kinds:
1. increasing external circuit
This method is by constructing public direct current or ac bus and external balance circuit, by the capacitor of all submodules
Voltage accesses common bus, to realize submodule capacitor voltage autobalance.But each submodule requires to increase additionally
Hardware circuit, so that the cost of device increases.
2. trim voltage modulating wave
The additional components that this method is obtained by capacitance voltage equalized feedback control loop are superimposed upon current control and return
The balance control of capacitance voltage is realized on the voltage modulated wave that road generates.But the additional components of superposition, it will lead to modulating wave
Distortion, influences the output performance of device；Due to not specific mathematical model, the parameter tuning of capacitance voltage feedback controller compared with
It is difficult；On the other hand, since each submodule requires to configure individual voltage balancing control device, the hardware requirement of controller increases
Height, when cascade converter submodule number increases, the complexity of control also be will increase.
Summary of the invention
For the defects in the prior art, the object of the present invention is to provide a kind of cascade converter submodule capacitor voltages
Efficient balance control method.
A kind of cascade converter submodule capacitor voltage balance control method provided according to the present invention, comprising:
Determine the asynchronous switch periods division mode of each submodule in cascade converter；
According to the asynchronous switch periods division mode of submodule each in the cascade converter, joined accordingly
Amount sampling calculates, and obtains the capacitance voltage disturbance quantity of each submodule, and to each submodule in the cascade converter
Capacitance voltage disturbance quantity is ranked up；
Capacitance voltage obtained is calculated according to submodule parameter each in cascade converter sampling, to the grade
The capacitance voltage of each submodule is ranked up in connection type current transformer；
According to preset Rule of judgment, the trigger pulse of each submodule in the cascade converter is divided again
Match；Wherein, the preset Rule of judgment includes: each submodule capacitor voltage disturbance quantity ranking results, each submodule
The ranking results of capacitance voltage, the capacitance voltage degree of unbalancedness of submodule, appointing in the difference of submodule capacitor voltage disturbance quantity
One or appoint multiple groups close.
Optionally it is determined that in cascade converter each submodule asynchronous switch periods division mode, comprising:
Assuming that using phase-shifting carrier wave modulation cascade converter a bridge arm in, include N number of cascade submodule, it is adjacent
Cascade submodule carrier wave phase angle difference be 2 π/N, a submodule is arbitrarily chosen from N number of cascade submodule as first
Module is denoted as Tri using the carrier wave of the first module as reference carrier1, the phase shifting angle for defining the first module is 0；Phase is successively stagnant
Carrier wave corresponding to N-1 module of 2 π/N is denoted as Tri respectively afterwards2、Tri3、…、TriN；Voltage corresponding to each submodule
Modulating wave is denoted as u respectivelym1、um2、…、umN, the corresponding voltage modulated coefficient of each submodule is denoted as d1、d2、…、dN；Bridge arm electricity
The input current of stream or submodule is denoted as Iarm；The capacitance voltage of each submodule is denoted as u respectivelyc1、uc2、…、ucN；Definition is each
The switch periods for the corresponding submodule that time of the submodule respectively between the two neighboring peak value of carrier wave is；Wherein, each submodule
The switch periods of block are synchronous or asynchronous.
Optionally, it according to the asynchronous switch periods division mode of submodule each in the cascade converter, carries out
Corresponding parameter sampling calculates, and obtains the capacitance voltage disturbance quantity of each submodule, and to each in the cascade converter
The capacitance voltage disturbance quantity of submodule is ranked up, comprising:
When the carrier wave corresponding to each submodule is to reach to peak value or trough, sampling obtains the parameter number of each submodule
According to, and each submodule capacitor voltage disturbance quantity is obtained by calculation；
The capacitance voltage disturbance quantity of any two submodule in more same bridge arm, and determine the row of capacitance voltage disturbance quantity
Sequence defines Pertur_iFor the capacitance voltage disturbance quantity of i-th of submodule；Pertur_jFor the capacitance voltage disturbance of j-th of submodule
Amount；1≤i < j≤N, N are the quantity that same bridge arm cascades submodule；
Work as PErtur_i-Pertur_jWhen >=0, the sequence of submodule capacitor voltage disturbance quantity is regular from big to small in same bridge arm are as follows:
Pertur_1≥Pertur_2≥Pertur_3≥…≥Pertur_N
Work as PErtur_i-Pertur_jWhen≤0, the sequence of submodule capacitor voltage disturbance quantity is regular from small to large in same bridge arm are as follows:
Pertur_1≤Pertur_2≤Pertur_3≤…≤Pertur_N。
Optionally, capacitance voltage obtained is calculated according to submodule parameter each in cascade converter sampling,
The capacitance voltage of each submodule in the cascade converter is ranked up, comprising:
To uc1_sam、uc2_sam、…、ucN_samCarry out ascending or descending order arrangement；Wherein, uc1_samFor the electricity of the 1st submodule
Hold voltage sample value, uc2_samFor the capacitance voltage sampled value of the 2nd submodule, ucN_samFor the capacitance voltage of n-th submodule
Sampled value, wherein subscript 1,2 ..., the serial number that N is submodule.
Optionally, according to preset Rule of judgment, to the trigger pulse of each submodule in the cascade converter
Before being redistributed, further includes:
According to the cascade converter submodule parametric data, the capacitor electricity of the cascade converter submodule is calculated
Press degree of unbalancedness；Wherein, the capacitance voltage degree of unbalancedness D of the cascade converter submoduleeg_unbalCalculation formula it is as follows:
Deg_unbal=MAX { uc1_sam~ucN_sam}?MIN{uc1_sam~ucN_sam}；
Wherein: MAX { } expression is maximized, and MIN { } expression is minimized.
Optionally, according to preset Rule of judgment, to the trigger pulse of each submodule in the cascade converter into
Row is redistributed, comprising:
Define the voltage modulated coefficient d of i-th of submoduleiWith carrier wave TriiGenerate i-th of trigger pulse Swi, same bridge arm
The trigger pulse of interior N number of cascade submodule is denoted as respectively: Sw1、Sw2、…、SwN；
Weight is carried out to the trigger pulse of each submodule in the cascade converter using following any or multimode
New distribution:
Mode one:
When the switch periods of first submodule start,
Calculate Dperturi-perturj(t)=Pertur_i(t)-Pertur_j(t), wherein 1≤i < j≤N, N are grade in a bridge arm
Join the quantity of submodule；
Calculate Dperturi-perturj(t-T1)=Pertur_i(t-T1)-Pertur_j(t-T1), wherein 1≤i < j≤N, N are one
The quantity of cascade submodule in bridge arm；T1For sampling period, T1=Ts/ 2 or T1=Ts；TsFor switch periods；Dperturi-perturj
It (t) is the difference of i-th of submodule and j-th of submodule capacitor voltage disturbance quantity in current sample period, Pertur_iIt (t) is to work as
The capacitance voltage disturbance quantity of i-th of submodule, P in the preceding sampling periodertur_jIt (t) is j-th of submodule in current sample period
Capacitance voltage disturbance quantity, Dperturi-perturj(t-T1) it was i-th of submodule and j-th of submodule in a upper sampling period
The difference of capacitance voltage disturbance quantity, Pertur_i(t-T1) disturbed for the capacitance voltage of i-th of submodule in a upper sampling period
Amount, Pertur_j(t-T1) be a upper sampling period in j-th of submodule capacitance voltage disturbance quantity；
Seek SIGN { Dperturi-perturjAnd SIGN { D (t) }perturi-perturj(t-T1), in which: SIGN { } indicates symbol
Function；When operand x > 0 in bracket, then SIGN { x }=1；Work as x=0, then SIGN { x }=0；When x < 0, then SIGN { x }=-
1；
If SIGN { Dperturi-perturj(t)}*SIGN{Dperturi-perturj(t-T1)}≥0；Then current PRF is kept to distribute
Mode；Symbol * indicates multiplying；
If SIGN { Dperturi-perturj(t)}*SIGN{Dperturi-perturj(t-T1) < 0, and SIGN { Dperturi-perturj
(t)}>0；Then according to the sequence of submodule capacitor voltage, by Sw1、Sw2、…、SwNIt is sequentially allocated to capacitance voltage most down to highest
Submodule；
If SIGN { Dperturi-perturj(t)}*SIGN{Dperturi-perturj(t-T1) < 0, and SIGN { Dperturi-perturj
(t)}<0；Then according to the sequence of submodule capacitor voltage, by Sw1、Sw2、…、SwNBe sequentially allocated be up to capacitance voltage it is minimum
Submodule；
Mode two:
When the switch periods of first submodule start,
Calculate Dperturi-perturj(t)=Pertur_i(t)-Pertur_j(t), wherein 1≤i < j≤N, N are grade in a bridge arm
Join the quantity of submodule；
Calculate Dperturi-perturj(t-T1)=Pertur_i(t-T1)-Pertur_j(t-T1), wherein 1≤i < j≤N, N are one
The quantity of cascade submodule in bridge arm；
Seek SIGN { Dperturi-perturjAnd SIGN { D (t) }perturi-perturj(t-T1)}；
Seek ABS { Pertur_1(t)-Pertur_N(t) }, in which: ABS { } indicates ABS function；When operand in bracket
X >=0, then ABS { x }=x；When x < 0, then ABS { x }=- x；
Set Pertur_ref, Pertur_refFor the threshold value of given capacitance voltage disturbance quantity difference；
If ABS { Pertur_1(t)-Pertur_N(t)}≥Pertur_refAnd SIGN { Dperturi-perturj(t)}*SIGN
{Dperturi-perturj(t-T1) < 0 and SIGN { Dperturi-perturj(t)}>0；It, will then according to the sequence of submodule capacitor voltage
Sw1、Sw2、…、SwNIt is sequentially allocated to capacitance voltage most down to highest submodule；
If ABS { Pertur_1(t)-Pertur_N(t)}≥Pertur_refAnd SIGN { Dperturi-perturj(t)}*SIGN
{Dperturi-perturj(t-T1) < 0 and SIGN { Dperturi-perturj(t)}<0；It, will then according to the sequence of submodule capacitor voltage
Sw1、Sw2、…、SwNIt is sequentially allocated and is up to minimum submodule to capacitance voltage；
Mode three:
When the switch periods of first submodule start,
Calculate Dperturi-perturj(t)=Pertur_i(t)-Pertur_j(t), wherein 1≤i < j≤N, N are grade in a bridge arm
Join the quantity of submodule；
Calculate Dperturi-perturj(t-T1)=Pertur_i(t-T1)-Pertur_j(t-T1), wherein 1≤i < j≤N, N are one
The quantity of cascade submodule in bridge arm；
Seek SIGN { Dperturi-perturjAnd SIGN { D (t) }perturi-perturj(t-T1)}；
Set Deg_unbal_ref, Deg_unbal_refFor given capacitance voltage degree of unbalancedness threshold value；Deg_unbalFor submodule electricity
Hold voltage unbalance factor；
If Deg_unbal≥Deg_unbal_refAnd SIGN { Dperturi-perturj(t)}*SIGN{Dperturi-perturj(t-T1) < 0 and
SIGN{Dperturi-perturj(t)}>0；Then according to the sequence of submodule capacitor voltage, by Sw1、Sw2、…、SwNIt is sequentially allocated to electricity
Hold voltage most down to highest submodule；
If Deg_unbal≥Deg_unbal_refAnd SIGN { Dperturi-perturj(t)}*SIGN{Dperturi-perturj(t-T1) < 0 and
SIGN{Dperturi-perturj(t)}<0；Then according to the sequence of submodule capacitor voltage, by Sw1、Sw2、…、SwNIt is sequentially allocated to electricity
Hold voltage and is up to minimum submodule.
Optionally, according to preset Rule of judgment, to the trigger pulse of each submodule in the cascade converter into
Row is redistributed, comprising: passes through any in exchange carrier, exchange voltage modulated coefficient, exchange carrier and voltage modulated coefficient
Or appoint various ways, the trigger pulse of each submodule is redistributed.
Optionally, the trigger pulse of each submodule in the cascade converter is redistributed, submodule
Trigger pulse to redistribute the period include: a switch periods, multiple switch period, according to degree of unbalancedness or/and disturbance quantity
Several identified revocable switch periods.
Optionally, the switch periods of each submodule start from respectively corresponding carrier wave in the cascade converter
At peak value or peak valley, end at the next peak value or peak valley of respectively corresponding carrier wave.Compared with prior art, the present invention has
It is following the utility model has the advantages that
Cascade converter submodule capacitor voltage balance control method provided by the invention, can be adapted for various unsteady flows
Device operating condition；Reaction speed is fast, can efficiently and accurately realize the balance control to submodule capacitor voltage, have preferable
Portfolio effect；Balance route algorithm is simple, and does not need by complicated external circuit and additional closed loop controller.
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, other feature of the invention,
Objects and advantages will become more apparent upon:
Fig. 1 is the modular multilevel cascade converter (MMC) using half-bridge structure submodule of the embodiment of the present invention
Structural schematic diagram；U indicates submodule output voltage, u in Fig. 1_ap1~u_apNRespectively indicate the defeated of each submodule of bridge arm in A phase
Voltage out, u_an1~u_anNRespectively indicate the output voltage of each submodule of A phase lower bridge arm, iarm_apIndicate the bridge of bridge arm in A phase
Arm electric current, iarm_bpIndicate the bridge arm current of bridge arm in B phase, iarm_cpIndicate the bridge arm current of bridge arm in C phase, iarm_anTable
Show the bridge arm current of A phase lower bridge arm, iarm_bnIndicate the bridge arm current of B phase lower bridge arm, iarm_cnIndicate the bridge arm electricity of C phase lower bridge arm
Stream, IdcThe electric current of DC bus, V are flowed through in expressiondcIndicate DC bus-bar voltage；
Fig. 2 is the submodule capacitor voltage balance control method schematic diagram of the embodiment of the present invention；T in Fig. 2ri1~TriNRespectively
Indicate the corresponding carrier wave of each submodule, um1~umNRespectively indicate the corresponding voltage modulated wave of each submodule, d1~dNRespectively
Indicate the voltage modulated coefficient of each submodule, IarmIndicate bridge arm current, Iarm_sam1~Iarm_samNRespectively indicate each submodule
The bridge arm current sampled value of block, Pertur_1~Pertur_NRespectively indicate the capacitance voltage disturbance quantity of each submodule, uc1~ucNPoint
The capacitance voltage of each submodule, u are not indicatedc1_sam~ucN_samThe capacitance voltage sampled value of each submodule is respectively indicated,
Deg_unbalIndicate submodule capacitor voltage degree of unbalancedness；
Fig. 3 is submodule switch periods definition each in the same bridge arm under conventional carrier phase shift modulation and divides signal
Figure；
Fig. 4 is each submodule switch periods definition and division schematic diagram in the same bridge arm of the embodiment of the present invention；
Fig. 5 is each emulation submodule capacitor voltage disturbance quantity sequence and calculated in the same bridge arm of the embodiment of the present invention
Result figure；Pertur1~Pertur 4Indicate the capacitance voltage disturbance quantity of each submodule, Dpertur1-pertur 4Indicate first submodule
The difference of block and the last one submodule capacitor voltage disturbance quantity；
When Fig. 6 (a) is that balance control is not added in submodule in the same bridge arm of the embodiment of the present invention, capacitor voltage balance control
Simulation result diagram；
When Fig. 6 (b) is that submodule adds balance to control in the same bridge arm of the embodiment of the present invention, capacitor voltage balance control is imitative
True result figure.
Specific embodiment
The present invention is described in detail combined with specific embodiments below.Following embodiment will be helpful to the technology of this field
Personnel further understand the present invention, but the invention is not limited in any way.It should be pointed out that the ordinary skill of this field
For personnel, without departing from the inventive concept of the premise, several changes and improvements can also be made.These belong to the present invention
Protection scope.
The embodiment of the present invention provide it is a kind of using phase-shifting carrier wave modulation cascade converter bridge arm in submodule capacitor
Voltage balancing control method.Submodule capacitor electricity in the cascade converter bridge arm using phase-shifting carrier wave modulation in the present embodiment
Pressure balance control method can be applied in half-bridge, bridge-type modular multi-level converter (Modular Multilevel
Converter, MMC) and cascade h-bridge converter (Cascaded H-Bridge Converter, CHB) submodule electricity
Hold in voltage balancing control.
Fig. 1 is the structure of the modular multi-level converter (MMC) using half-bridge structure submodule of the embodiment of the present invention
Schematic diagram, as shown in Figure 1.In the modular multi-level converter of Fig. 1, comprising having 4 in each bridge arm there are six bridge arm
A submodule (SMn1~SMnN), rated power 10MW, each bridge arm is made of 4 sub-module cascades.Each submodule electricity
The reference value for holding voltage is 2000V, carrier frequency 1000Hz, total DC bus-bar voltage are 8000V, alternating current net side line voltage peak
Value is 2400V, fundamental frequency 50Hz, and the method proposed can be used in but be not limited to half-bridge, bridge-type MMC, D type or Y type grade
Join in the cascade converters such as H bridge.Fig. 2 is the submodule capacitor voltage balance control method schematic diagram of the embodiment of the present invention.Such as Fig. 2
Shown, the method specifically includes following link:
Link 1: the division mode of submodule switch periods is determined；
Traditional phase-shifting carrier wave is modulated, the phase shifting angle of each submodule carrier wave successively differs in one bridge arm of current transformer
It is any to choose one in bridge arm for 2 π/N (rad/s) (N is not consider under redundancy condition, the cascade submodule number of institute in bridge arm)
A submodule as module 1, corresponding to carrier wave as reference carrier, be denoted as Tri1, defining its phase shifting angle is 0；Phase according to
Carrier wave corresponding to secondary lag N-1 module of 2 π/N is denoted as Tri respectively2、Tri3、…、TriN.In conventional carrier phase shift modulation
The synchronous switch period divide as shown in figure 3, including 4 submodules, S in the same bridge arm of the cascade converter in Fig. 3W1~
SW4Indicate the corresponding switching pulse of 4 submodules, TSWSwitch periods are indicated, as shown in figure 3, all submodules in same bridge arm
Switch periods start simultaneously at, terminate simultaneously.Asynchronous switch periods divide as shown in figure 4, each in the method for the invention
The switch periods of module all start from respectively to the peak value of corresponding carrier wave at, end at next peak value of carrier wave.Therefore,
The switch periods of each module do not start simultaneously at and while terminating, the switch periods initial time difference of two neighboring module
1/N switch periods, finish time also differ 1/N switch periods.
When the carrier wave corresponding to each submodule is to reach to peak value or at trough, each submodule is obtained by sampling
Capacitance voltage, and submodule capacitor voltage disturbance quantity is calculated by sampling.
Submodule capacitor voltage disturbance quantity calculates 2 times in an asynchronous switch periods:
1st time: after the completion of sampling at the carrier peak value of n-th module, calculating the capacitance voltage disturbance of each submodule
Amount, the calculation method of the capacitance voltage disturbance quantity of i-th of submodule are as follows:
Pertur_ip=dip*Iarm_samip
2nd time: after the completion of sampling at the carrier wave trough of n-th module, calculating the capacitance voltage disturbance of each submodule
Amount, the capacitance voltage disturbance quantity of i-th of submodule are as follows:
Pertur_iv=div*Iarm_samiv
Link 2: the sequence of submodule capacitor voltage disturbance quantity；
Submodule capacitor voltage disturbance quantity in same bridge arm is ranked up, first submodule and last height are chosen
Module calculates its disturbance quantity and asks poor,
Work as Dpertur1-perturN=PErtur_1p-Pertur_NpWhen >=0, capacitance voltage disturbance quantity is arranged in available same bridge arm
Sequence rule is from big to small are as follows:
Pertur_1p≥Pertur_2p≥Pertur_3p≥…≥Pertur_Np
Work as Dpertur1-perturN=PErtur_1p-Pertur_NpWhen≤0, capacitance voltage disturbance quantity is arranged in available same bridge arm
Sequence rule is from small to large are as follows:
Pertur_1p≤Pertur_2p≤Pertur_3p≤…≤Pertur_Np
It can be concluded that according to Pertur_1pWith Pertur_NpDifference it is positive and negative, each submodule in same bridge arm can be directly obtained
The ranking results of block capacitance voltage disturbance quantity do not need to belong to static ordering by sort algorithm.
The sort method for the submodule capacitor voltage disturbance quantity that sampled value at carrier wave trough is calculated is same as above, herein
It repeats no more.
Submodule capacitor voltage disturbance quantity calculates as shown in Figure 5 with the simulation result of sequence.
Link 3: submodule capacitor voltage sequence is calculated with degree of unbalancedness.
The sequence of capacitance voltage and degree of unbalancedness calculate and update 2 times in an asynchronous switch periods bridge arm:
1st time: after the completion of sampling at the carrier peak value of n-th module, to uc1_samp、uc2_samp、…、ucN_sampIt carries out
Sequence, computational submodule capacitance voltage degree of unbalancedness are as follows:
Deg_unbal=MAX { uc1_samp~ucN_samp}?MIN{uc1_samp~ucN_samp}
2nd time: after the completion of sampling at the carrier wave trough of n-th module, to uc1_samv、uc2_samv、…、ucN_samvIt carries out
Sequence, computational submodule capacitance voltage degree of unbalancedness are as follows:
Deg_unbal=MAX { uc1_samv~ucN_samv}?MIN{uc1_samv~ucN_samv}
Wherein, Deg_unbalSubmodule capacitor voltage degree of unbalancedness in the same bridge arm obtained for simulation calculation
Link 4: submodule trigger pulse is redistributed.
When the switch periods of first submodule start, first module disturbance quantity is disturbed with the last one submodule
Momentum carries out asking poor calculating, compares resulting difference Dpertur1-perturN(t) the difference D calculated with the last timepertur1-perturN(t-
Ts/ 2) positive and negative whether identical.
If Dpertur1-perturN(t)*Dpertur1-perturN(t-Ts/2)≥0；Then keep current PRF allocation plan.
If Dpertur1-perturN(t)*Dpertur1-perturN(t-Ts/ 2) < 0 and Dpertur1-perturN(t)>0；
Then submodule capacitor voltage is ranked up, and by Sw1、Sw2、…、SwNIt is sequentially allocated to capacitance voltage most down to most
High submodule；
If Dpertur1-perturN(t)*Dpertur1-perturN(t-Ts/ 2) < 0 and Dpertur1-perturN(t)<0；
Then submodule capacitor voltage is ranked up, and by Sw1、Sw2、…、SwNIt is sequentially allocated and is up to most to capacitance voltage
Low submodule；
The simulation result of submodule capacitor voltage balance control is as shown in Figure 6.It can be seen that being added after balance control, son
Module capacitance voltage has obtained good control, and submodule capacitor voltage degree of unbalancedness reduces.Simultaneously it can be seen that capacitance voltage
Degree of unbalancedness can be good at characterizing the degree of divergence of capacitance voltage.
The present invention is suitable for various cascade converters and its corresponding operating condition, can realize quickly to sub- module capacitance electricity
The balance of pressure controls, and has preferable portfolio effect；Balance route algorithm is simple, and does not need by complicated external circuit.
Specific embodiments of the present invention are described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, those skilled in the art can make a variety of changes or modify within the scope of the claims, this not shadow
Ring substantive content of the invention.In the absence of conflict, the feature in embodiments herein and embodiment can any phase
Mutually combination.
Claims (9)
1. a kind of cascade converter submodule capacitor voltage balance control method characterized by comprising
Determine the asynchronous switch periods division mode of each submodule in cascade converter；
According to the asynchronous switch periods division mode of submodule each in the cascade converter, carries out corresponding parameter and adopt
Sample calculates, and obtains the capacitance voltage disturbance quantity of each submodule, and to the capacitor of each submodule in the cascade converter
Voltage disturbance amount is ranked up；
Capacitance voltage obtained is calculated according to submodule parameter each in cascade converter sampling, to the cascade connection type
The capacitance voltage of each submodule is ranked up in current transformer；
According to preset Rule of judgment, the trigger pulse of each submodule in the cascade converter is redistributed；
Wherein, the preset Rule of judgment includes: the capacitor of each submodule capacitor voltage disturbance quantity ranking results, each submodule
The ranking results of voltage, the capacitance voltage degree of unbalancedness of submodule, any in the difference of submodule capacitor voltage disturbance quantity or
Person appoints multiple groups to close.
2. cascade converter submodule capacitor voltage balance control method according to claim 1, which is characterized in that really
Determine the asynchronous switch periods division mode of each submodule in cascade converter, comprising:
Assuming that using phase-shifting carrier wave modulation cascade converter a bridge arm in, include N number of cascade submodule, adjacent grade
The phase angle difference for joining submodule carrier wave is 2 π/N, a submodule is arbitrarily chosen from N number of cascade submodule as the first module,
Using the carrier wave of the first module as reference carrier, it is denoted as Tri1, the phase shifting angle for defining the first module is 0；Phase successively lag 2 π/
Carrier wave corresponding to the N-1 module of N is denoted as Tri respectively2、Tri3、…、TriN；Voltage modulated wave corresponding to each submodule
It is denoted as u respectivelym1、um2、…、umN, the corresponding voltage modulated coefficient of each submodule is denoted as d1、d2、…、dN；Bridge arm current or son
The input current of module is denoted as Iarm；The capacitance voltage of each submodule is denoted as u respectivelyc1、uc2、…、ucN；Define each submodule
The switch periods for the corresponding submodule that time between the two neighboring peak value of respective carrier wave is；Wherein, each submodule is opened
Close cycle synchronisation or asynchronous.
3. cascade converter submodule capacitor voltage balance control method according to claim 1, which is characterized in that root
According to the asynchronous switch periods division mode of each submodule in the cascade converter, corresponding parameter sampling meter is carried out
It calculates, obtains the capacitance voltage disturbance quantity of each submodule, and to the capacitance voltage of each submodule in the cascade converter
Disturbance quantity is ranked up, comprising:
When the carrier wave corresponding to each submodule is to reach to peak value or trough, sampling obtains the parametric data of each submodule, and
Each submodule capacitor voltage disturbance quantity is obtained by calculation；
The capacitance voltage disturbance quantity of any two submodule in more same bridge arm, and determine the sequence of capacitance voltage disturbance quantity,
Define Pertur_iFor the capacitance voltage disturbance quantity of i-th of submodule；Pertur_jFor the capacitance voltage disturbance quantity of j-th of submodule；1
≤ i < j≤N, N are the quantity that same bridge arm cascades submodule；
Work as PErtur_i-Pertur_jWhen >=0, the sequence of submodule capacitor voltage disturbance quantity is regular from big to small in same bridge arm are as follows:
Pertur_1≥Pertur_2≥Pertur_3≥…≥Pertur_N
Work as PErtur_i-Pertur_jWhen≤0, the sequence of submodule capacitor voltage disturbance quantity is regular from small to large in same bridge arm are as follows:
Pertur_1≤Pertur_2≤Pertur_3≤…≤Pertur_N。
4. cascade converter submodule capacitor voltage balance control method according to claim 1, which is characterized in that root
Capacitance voltage obtained is calculated according to submodule parameter each in cascade converter sampling, to the cascade converter
In the capacitance voltage of each submodule be ranked up, comprising:
To uc1_sam、uc2_sam、…、ucN_samCarry out ascending or descending order arrangement；Wherein, uc1_samFor the capacitor electricity of the 1st submodule
Press sampled value, uc2_samFor the capacitance voltage sampled value of the 2nd submodule, ucN_samIt is sampled for the capacitance voltage of n-th submodule
Value, wherein subscript 1,2 ..., the serial number that N is submodule.
5. cascade converter submodule capacitor voltage balance control method according to claim 4, which is characterized in that
According to preset Rule of judgment, before being redistributed to the trigger pulse of each submodule in the cascade converter,
Further include:
According to the cascade converter submodule parametric data, the capacitance voltage of the cascade converter submodule is calculated not
The degree of balance；Wherein, the capacitance voltage degree of unbalancedness D of the cascade converter submoduleeg_unbalCalculation formula it is as follows:
Deg_unbal=MAX { uc1_sam~ucN_sam}?MIN{uc1_sam~ucN_sam}；
Wherein: MAX { } expression is maximized, and MIN { } expression is minimized.
6. cascade converter submodule capacitor voltage balance control method according to claim 1, which is characterized in that root
According to preset Rule of judgment, the trigger pulse of each submodule in the cascade converter is redistributed, comprising:
Define the voltage modulated coefficient d of i-th of submoduleiWith carrier wave TriiGenerate i-th of trigger pulse Swi, N number of in same bridge arm
The trigger pulse of cascade submodule is denoted as respectively: Sw1、Sw2、…、SwN；
The trigger pulse of each submodule in the cascade converter is divided again using following any or multimode
Match:
Mode one:
When the switch periods of first submodule start,
Calculate Dperturi-perturj(t)=Pertur_i(t)-Pertur_j(t), wherein 1≤i < j≤N, N are cascade in a bridge arm
The quantity of module；
Calculate Dperturi-perturj(t-T1)=Pertur_i(t-T1)-Pertur_j(t-T1), wherein 1≤i < j≤N, N are a bridge arm
The quantity of interior cascade submodule；T1For sampling period, T1=Ts/ 2 or T1=Ts；TsFor switch periods；Dperturi-perturj(t)
For the difference of i-th of submodule and j-th of submodule capacitor voltage disturbance quantity in current sample period, Pertur_iIt (t) is current
The capacitance voltage disturbance quantity of i-th of submodule, P in sampling periodertur_jIt (t) is j-th of submodule in current sample period
Capacitance voltage disturbance quantity, Dperturi-perturj(t-T1) it was i-th of submodule and j-th of submodule electricity in a upper sampling period
Hold the difference of voltage disturbance amount, Pertur_i(t-T1) be a upper sampling period in i-th of submodule capacitance voltage disturbance quantity,
Pertur_j(t-T1) be a upper sampling period in j-th of submodule capacitance voltage disturbance quantity；
Seek SIGN { Dperturi-perturjAnd SIGN { D (t) }perturi-perturj(t-T1), in which: SIGN { } indicates sign function；
When operand x > 0 in bracket, then SIGN { x }=1；Work as x=0, then SIGN { x }=0；When x < 0, then SIGN { x }=- 1；
If SIGN { Dperturi-perturj(t)}*SIGN{Dperturi-perturj(t-T1)}≥0；Then keep the current PRF method of salary distribution；
Symbol * indicates multiplying；
If SIGN { Dperturi-perturj(t)}*SIGN{Dperturi-perturj(t-T1) < 0, and SIGN { Dperturi-perturj(t)}>0；
Then according to the sequence of submodule capacitor voltage, by Sw1、Sw2、…、SwNIt is sequentially allocated to capacitance voltage most down to highest submodule
Block；
If SIGN { Dperturi-perturj(t)}*SIGN{Dperturi-perturj(t-T1) < 0, and SIGN { Dperturi-perturj(t)}<0；
Then according to the sequence of submodule capacitor voltage, by Sw1、Sw2、…、SwNIt is sequentially allocated and is up to minimum submodule to capacitance voltage
Block；
Mode two:
When the switch periods of first submodule start,
Calculate Dperturi-perturj(t)=Pertur_i(t)-Pertur_j(t), wherein 1≤i < j≤N, N are cascade in a bridge arm
The quantity of module；
Calculate Dperturi-perturj(t-T1)=Pertur_i(t-T1)-Pertur_j(t-T1), wherein 1≤i < j≤N, N are a bridge arm
The quantity of interior cascade submodule；
Seek SIGN { Dperturi-perturjAnd SIGN { D (t) }perturi-perturj(t-T1)}；
Seek ABS { Pertur_1(t)-Pertur_N(t) }, in which: ABS { } indicates ABS function；When operand x in bracket >=
0, then ABS { x }=x；When x < 0, then ABS { x }=- x；
Set Pertur_ref, Pertur_refFor the threshold value of given capacitance voltage disturbance quantity difference；
If ABS { Pertur_1(t)-Pertur_N(t)}≥Pertur_refAnd SIGN { Dperturi-perturj(t)}*SIGN{Dperturi-perturj
(t-T1) < 0 and SIGN { Dperturi-perturj(t)}>0；Then according to the sequence of submodule capacitor voltage, by Sw1、Sw2、…、SwNAccording to
Sub-distribution is to capacitance voltage most down to highest submodule；
If ABS { Pertur_1(t)-Pertur_N(t)}≥Pertur_refAnd SIGN { Dperturi-perturj(t)}*SIGN{Dperturi-perturj
(t-T1) < 0 and SIGN { Dperturi-perturj(t)}<0；Then according to the sequence of submodule capacitor voltage, by Sw1、Sw2、…、SwNAccording to
Sub-distribution is up to minimum submodule to capacitance voltage；
Mode three:
When the switch periods of first submodule start,
Calculate Dperturi-perturj(t)=Pertur_i(t)-Pertur_j(t), wherein 1≤i < j≤N, N are cascade in a bridge arm
The quantity of module；
Calculate Dperturi-perturj(t-T1)=Pertur_i(t-T1)-Pertur_j(t-T1), wherein 1≤i < j≤N, N are a bridge arm
The quantity of interior cascade submodule；
Seek SIGN { Dperturi-perturjAnd SIGN { D (t) }perturi-perturj(t-T1)}；
Set Deg_unbal_ref, Deg_unbal_refFor given capacitance voltage degree of unbalancedness threshold value；Deg_unbalFor submodule capacitor electricity
Press degree of unbalancedness；
If Deg_unbal≥Deg_unbal_refAnd SIGN { Dperturi-perturj(t)}*SIGN{Dperturi-perturj(t-T1) < 0 and SIGN
{Dperturi-perturj(t)}>0；Then according to the sequence of submodule capacitor voltage, by Sw1、Sw2、…、SwNIt is sequentially allocated and gives capacitor electricity
Pressure is most down to highest submodule；
If Deg_unbal≥Deg_unbal_refAnd SIGN { Dperturi-perturj(t)}*SIGN{Dperturi-perturj(t-T1) < 0 and SIGN
{Dperturi-perturj(t)}<0；Then according to the sequence of submodule capacitor voltage, by Sw1、Sw2、…、SwNIt is sequentially allocated and gives capacitor electricity
Pressure is up to minimum submodule.
7. cascade converter submodule capacitor voltage balance control method according to claim 1, which is characterized in that root
According to preset Rule of judgment, the trigger pulse of each submodule in the cascade converter is redistributed, comprising: logical
Any or various ways in exchange carrier, exchange voltage modulated coefficient, exchange carrier and voltage modulated coefficient are crossed, to each
The trigger pulse of submodule is redistributed.
8. cascade converter submodule capacitor voltage balance control method according to claim 1, which is characterized in that right
The trigger pulse of each submodule in the cascade converter is redistributed, and the trigger pulse of submodule is redistributed
Period includes: a switch periods, multiple switch period, if revocable according to determined by degree of unbalancedness or/and disturbance quantity
Dry switch periods.
9. cascade converter submodule capacitor voltage balance control method according to claim 1 to 8,
Be characterized in that, in the cascade converter switch periods of each submodule start from respectively corresponding carrier wave peak value or
At peak valley, end at the next peak value or peak valley of respectively corresponding carrier wave.
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| CN111965468A (en) * | 2020-04-26 | 2020-11-20 | 上海交通大学 | Current control method of cascade submodule working condition simulation system suitable for NLC |
| CN115328236A (en) * | 2022-08-10 | 2022-11-11 | 上海交通大学 | Thermal balance control method and system for submodule capacitor of cascade energy storage converter |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111965468A (en) * | 2020-04-26 | 2020-11-20 | 上海交通大学 | Current control method of cascade submodule working condition simulation system suitable for NLC |
| CN111965468B (en) * | 2020-04-26 | 2021-08-03 | 上海交通大学 | Current control method of cascade submodule working condition simulation system suitable for NLC |
| CN115328236A (en) * | 2022-08-10 | 2022-11-11 | 上海交通大学 | Thermal balance control method and system for submodule capacitor of cascade energy storage converter |
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