CN109345442A - A kind of lucky imaging system of FPGA and method based on Ethernet transmission - Google Patents
A kind of lucky imaging system of FPGA and method based on Ethernet transmission Download PDFInfo
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- CN109345442A CN109345442A CN201811082832.7A CN201811082832A CN109345442A CN 109345442 A CN109345442 A CN 109345442A CN 201811082832 A CN201811082832 A CN 201811082832A CN 109345442 A CN109345442 A CN 109345442A
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- 230000006870 function Effects 0.000 claims description 16
- 238000011161 development Methods 0.000 claims description 13
- 238000012546 transfer Methods 0.000 claims description 3
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
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Abstract
The present invention relates to a kind of lucky imaging systems of FPGA and method based on Ethernet transmission, belong to technical field of image processing.The present invention sends image data to the Ethernet chip of FPGA by the gigabit Ethernet at the end PC, and by FIFO transition, received image data is saved in DDR3 memory module.Subsequent FPGA reads out image data from DDR3 memory module, and obtains the maximum value of each image by comparing, and the maximum value compared is saved.Then, by the way that these maximum values sort to find 1% best image of effect.Finally, these resulting image registrations are superimposed, obtain an artificial synthesized image and this image is passed back into host computer by Ethernet chip, while being shown by VGA module, facilitate observation.It is above exactly the transmission and treatment process of whole system, entire treatment process can have greatly improved in speed relative to traditional lucky image processing method.
Description
Technical field
The present invention relates to a kind of lucky imaging systems of FPGA and method based on Ethernet transmission, belong to image processing techniques
Field and electronic system technology field.
Background technique
Gigabit Ethernet is to propose for 1997, the local area network communication specification to get the Green Light for 1998.Develop by now, gigabit
Ethernet has obtained greatly universal.Although the technology of ten thousand mbit ethernets is also mature, at present for popularization degree
It is nothing like gigabit Ethernet.The design is also allowed for using gigabit Ethernet and is equipped on many ASTRONOMICAL CCD cameras
It is gigabit ethernet interface.In addition, the high speed of gigabit Ethernet and the characteristic of full duplex also meet the requirement of the design very much.?
Realize that the transmit-receive technology of Ethernet is also very mature on FPGA, exactly, Ethernet is the main side of FPGA data transmission
One of formula.And in the various communication protocols of Ethernet, this system has selected speed fast and the simple udp protocol of control.
Lucky imaging technique is to solve a kind of post-processing technology that atmospheric noise is interfered and come into being.Specifically
It is a series of image that a small amount of high quality is selected in short exposed images, then these images are registrated and are superimposed is subsequent
Processing technique.It can be more clear by the image that this technical treatment comes out, facilitate observation, compared to using astronomical telescope
Shooting, expense are much lower.However the defect of this post-processing technology is must to complete it to selected astronomical target observation
Gained image is handled again afterwards, this, which allows for astronomer, can not know real time information about captured image, so that
In cannot find the problem of being likely to occur in observation process in time, and make high-speed decision.The method for solving the problems, such as this is to change
Into algorithm, increase the processing capacity of hardware, lucky imaging technique is changed in real time or quasi real time.It is used on PC compared to traditional
For matlab does the mode of serial process by CPU, FPGA has the characteristics that concurrency and flexibility, moreover it is possible to provide it is powerful and
Row computing capability and memory bandwidth.And it is current, one of main application fields of FPGA are exactly image procossing.In addition, this project is most
Big breakthrough is to realize semi-real time processing.If necessary, as long as in this engineering with minor modifications, will be sent to originally by PC
The image data of FPGA becomes camera to be connected on FPGA, and the image taken is transmitted directly to FPGA and is handled, i.e.,
It may be implemented to handle in real time.
Summary of the invention
It is luckily imaged the technical problem to be solved by the present invention is the present invention provides a kind of FPGA based on Ethernet transmission and is
System and method, for solve in existing PC machine using the lucky imaging speed of MATLAB progress slow, existing FPGA luckily at
As system image data source transmission speed is excessively slow and the problem of cannot handling in real time.
The technical scheme is that: a kind of lucky imaging system of FPGA based on Ethernet transmission, including host computer, FPGA
Development board, VGA display；FPGA development board includes ethernet module, fifo module, DDR3 writes data module, DDR3 reads data
Module, DDR3 memory module, lucky imaging algorithm processing module, VGA display module；
The host computer is used to send the images to the ethernet module of FPGA development board by the udp protocol of gigabit Ethernet；
The ethernet module is for transferring data to fifo module after receiving the image data that host computer is sent and connecing
It receives the image data sent after lucky imaging algorithm processing module processing and returns to host computer；
Image data of the fifo module for coming transmitted by transition ethernet module is simultaneously sent to DDR3 and writes data module；
The DDR3 writes data module and is used to receive the image data transmitted from ethernet module by fifo module, and will
These data are saved in DDR3 memory module；
The DDR3 data reading module by the image data in DDR3 memory module for reading out and being sent to lucky imaging
Algorithm processing module is handled；
The DDR3 memory module is for storing the image data that fifo module transmits；
The lucky imaging algorithm processing module selects picture for receiving the image in DDR3 memory module and handling it
Maximum preceding 1% image of plain value simultaneously carries out being registrated superimposed high-definition picture and is sent to VGA display module, Ethernet mould
Block；
The VGA display module is for driving VGA display to lucky imaging algorithm processing module treated high resolution graphics
As data are shown, VGA display is for showing high resolution image data.
The host computer is using the PC for having gigabit Ethernet transmission-receiving function or the camera with Ethernet interface；It is described with
Too net module uses RTL8211EG ethernet PHY chip.
A kind of lucky imaging method of FPGA based on Ethernet transmission, specific step is as follows for the method:
Step1, first host computer send the images to the ethernet module of FPGA development board by the udp protocol of gigabit Ethernet；
Step2, ethernet module transfer data to fifo module after receiving the image data that host computer is sent；
The image data that comes transmitted by Step3, fifo module transition ethernet module is simultaneously sent to DDR3 and writes data module；
Step4, DDR3 write data module and receive the image data that transmits from ethernet module by fifo module, and by this
A little data are saved in DDR3 memory module；
Image data in DDR3 memory module is read out and is sent to lucky imaging and calculated by Step5, DDR3 data reading module
Method processing module is handled；
Step6, lucky imaging algorithm processing module receive the image in DDR3 memory module and handle it, select pixel
It is worth maximum preceding 1% image and carrying out and is registrated that superimposed high-definition picture is sent to ethernet module and VGA shows mould
Block；
Step7, ethernet module receive the image data sent after lucky imaging algorithm processing module processing and return to
Position machine；
Step8, VGA display module drive VGA display to lucky imaging algorithm processing module treated high-definition picture
Data are shown.
The working principle of the invention is:
The ethernet module is made of Ethernet receiving module and sending module.Wherein, on the left of Ethernet receiving module such as Fig. 3
Image that is shown, being sended over for receiving host computer, and image is saved in DDR3 memory module by fifo module.?
In receive process, ethernet module first receives lead code, if lead code is correct, the MAC Address of target is continued to, if MAC
Address is correct, then receives remaining IP TYPE, virtual packet header, UDP port number and long data packet.These data receivers finish
Afterwards, the data that Bao Wenzhong comes are exactly real image data, at this point, these image datas can be received FIFO by this system
In module.Ethernet sending module be then after entire lucky imaging algorithm processing module carries out the process of image procossing,
Host computer is sent by resulting result.The transmission flow of Ethernet first sends lead code and retransmits MAC as shown in the right side Fig. 3
Address, IP TYPE, virtual packet header, UDP port number, long data packet and real image data (i.e. processing result).
The DDR3 memory module, function are the caching received all images data of Ethernet, and when needed, for choosing
Module and registration module provide data.
The data that the ethernet module is transmitted to DDR3 memory module have to be transitioned into DDR3 storage by fifo module
Module because by the data that the udp protocol of gigabit Ethernet is sent be send in the form of data packet it is past.In one packet
The data in face can not be saved directly in DDR3 memory module, and with this, this system plays a transitional function using fifo module.
The DDR3 memory module, its significance lies in that being mentioned to carry out the comparison of pixel maximum and carrying out subsequent processing
For data；Due to the data of Ethernet be FPGA core core is sent to by data packet form, so, compare maximum value just not
It can be carried out simultaneously during receiving data.In conclusion this system data are first stored in DDR3 memory module again according to
Secondary reading is compared.
The host computer can be using the PC for being mounted with Ethernet transmission-receiving function software, the ethernet module, function
It is to realize the image data for receiving and sending over from host computer, data is sent to DDR3 memory module by fifo module, and
And after the completion of entire lucky imaging algorithm processing module, image is returned into host computer by ethernet module.It therefore, should be with
Too net module can be subdivided into again sends and receivees two modules.
The lucky imaging algorithm processing module is selected for receiving the image in DDR3 memory module and handling it
It maximum preceding 1% image of pixel value and carries out being registrated superimposed high-definition picture and is sent to VGA display module, ether out
Net module.
The lucky imaging algorithm processing module by selecting three module, registration module and laminating module modules to form, and
Module is being selected to be subdivided into two submodules again, i.e. maximum gradation value solves module and maximum gradation value sorting module.
The maximum gradation value selected in module solves module, and function is the image reading being saved in DDR3
Come, and be compared all pixels value of the image one by one, to find out the maximum gradation value of every frame image and save it in piece
It is used in interior RAM for sequence.During the resume module, to judge whether pixel data meets registration to maximum gradation value position
The requirement set.Meet, then saves the pixel value in the corresponding address space of RAM；It is unsatisfactory for, then it is empty in the corresponding address RAM
Between middle deposit and the zero of the maximum gradation value same bits digit.In addition, saving every frame image maximum gradation value into RAM
When, simultaneously by where the maximum gradation value picture numbers and location parameter be stored in RAM appropriate address space together, with
Convenient for sorting module use.
The maximum gradation value sorting module selected in module, function are to the maximum ash being stored in ram in slice
Angle value is ranked up, and saves required maximum gradation value and its relevant information.It is every to take out a maximum gray scale in sequencer procedure
After value, to judge whether the maximum gradation value read at this time is the pixel value for being drained through sequence and having saved.If so, keeping upper one to delay
The pixel Value Data deposited is constant；Otherwise, if current pixel value is greater than a upper pixel value for caching, change the pixel value of caching
Data are current the greater.Every wheel that carried out compares, and saves the pixel value of a current cache.According to said method it is ranked up,
Until meeting the number of pixels to be taken out.At the same time, picture numbers and maximum can be issued after the completion of selecting module to work
The signal of gray value locations is to start registration module work.
Registration module in the lucky imaging algorithm processing module, function be with select obtained in module maximum ash
Picture numbers and its location parameter, calculate and want truncated picture first address where angle value, are then sent to DDR3 and read data
Module uses to read corresponding image pixel value from DRR3 memory module for laminating module.
Laminating module in the lucky imaging algorithm processing module, function are all images that will be selected and be registrated
Be superimposed, but each pixel of the image sequentially enters buffer 1 when handling first frame image, after the completion of store again from
It is sequential read out in buffer 1, while the respective pixel with initial value for 0 superimposed image is successively added；It is equivalent to first frame image
It directly is cached to buffer 3, is prepared for superposition next time.Each pixel of first frame image successively from buffer 3 cache into
While entering buffer 2, second each pixel of frame image is also successively being cached into buffer 1, when buffer 1 and buffer 2 simultaneously
After completing caching, then is cached after the pixel in two buffers is sequential read out and is added simultaneously and enter buffer 3.Side according to this
Formula, all image superpositions that will be selected.Last resulting superimposed image is exactly the high-definition picture rebuild, it be temporarily stored in it is slow
In storage 3, its reading pixel-by-pixel is stored in corresponding position again after read output signal arrives.
The VGA driver module, function are to show that equipment (such as liquid crystal or CRT monitor) prepares for external VGA
Image data drives so that system is handled the display that obtained final Reconstructing High is exported to fpga chip
Unit.
The beneficial effects of the present invention are: the present invention carries out lucky imaging in speed with MATLAB on PC
Deficiency, provide it is a kind of based on Ethernet transmission the lucky imaging system of FPGA and its implementation, with realize on FPGA
Lucky Imaging processing techniques are carried out, and are communicated with Ethernet, transmission speed is promoted.This system not only improves lucky imaging
The processing speed of technology, also the real-time processing to be luckily imaged lays a solid foundation；
Present invention incorporates Ethernets to transmit data, and compared to data are read from memory device, speed is improved very much.This
Outside, the present invention overcomes traditional CPU+MATLAB to a certain extent and handles that lucky imaging algorithm speed is excessively slow and resource distribution
The king-sized disadvantage of demand has pushed the development of lucky imaging technique real time implementation.The present invention has rational design, is skillfully constructed, in real time
Property is good, there is certain application value in astronomical images processing field.
Detailed description of the invention
Fig. 1 is system block diagram of the invention；
Fig. 2 is FPGA control block diagram of the invention；
Fig. 3 is ethernet module control block diagram of the invention.
Specific embodiment
In the following with reference to the drawings and specific embodiments, the invention will be further described.
Embodiment 1: as shown in Figure 1-3, a kind of lucky imaging system of FPGA based on Ethernet transmission, including host computer,
FPGA development board, VGA display；FPGA development board includes ethernet module, fifo module, DDR3 writes data module, DDR3 is read
Data module, DDR3 memory module, lucky imaging algorithm processing module, VGA display module；
The host computer is used to send the images to the ethernet module of FPGA development board by the udp protocol of gigabit Ethernet；
The ethernet module is for transferring data to fifo module after receiving the image data that host computer is sent and connecing
It receives the image data sent after lucky imaging algorithm processing module processing and returns to host computer；
Image data of the fifo module for coming transmitted by transition ethernet module is simultaneously sent to DDR3 and writes data module；
The DDR3 writes data module and is used to receive the image data transmitted from ethernet module by fifo module, and will
These data are saved in DDR3 memory module；
The DDR3 data reading module by the image data in DDR3 memory module for reading out and being sent to lucky imaging
Algorithm processing module is handled；
The DDR3 memory module is for storing the image data that fifo module transmits；
The lucky imaging algorithm processing module selects picture for receiving the image in DDR3 memory module and handling it
Maximum preceding 1% image of plain value simultaneously carries out being registrated superimposed high-definition picture and is sent to VGA display module, Ethernet mould
Block；
The VGA display module is for driving VGA display to lucky imaging algorithm processing module treated high resolution graphics
As data are shown, VGA display is for showing high resolution image data.
The host computer is using the PC for having gigabit Ethernet transmission-receiving function or the camera with Ethernet interface；It is described with
Too net module uses RTL8211EG ethernet PHY chip.
A kind of lucky imaging method of FPGA based on Ethernet transmission, specific step is as follows for the method:
Step1, first host computer send the images to the ethernet module of FPGA development board by the udp protocol of gigabit Ethernet；
Step2, ethernet module transfer data to fifo module after receiving the image data that host computer is sent；
The image data that comes transmitted by Step3, fifo module transition ethernet module is simultaneously sent to DDR3 and writes data module；
Step4, DDR3 write data module and receive the image data that transmits from ethernet module by fifo module, and by this
A little data are saved in DDR3 memory module；
Image data in DDR3 memory module is read out and is sent to lucky imaging and calculated by Step5, DDR3 data reading module
Method processing module is handled；
Step6, lucky imaging algorithm processing module receive the image in DDR3 memory module and handle it, select pixel
It is worth maximum preceding 1% image and carrying out and is registrated that superimposed high-definition picture is sent to ethernet module and VGA shows mould
Block；
Step7, ethernet module receive the image data sent after lucky imaging algorithm processing module processing and return to
Position machine；
Step8, VGA display module drive VGA display to lucky imaging algorithm processing module treated high-definition picture
Data are shown.
The working principle of the invention is:
The ethernet module is made of Ethernet receiving module and sending module.Wherein, on the left of Ethernet receiving module such as Fig. 3
Image that is shown, being sended over for receiving host computer, and image is saved in DDR3 memory module by fifo module.?
In receive process, ethernet module first receives lead code, if lead code is correct, the MAC Address of target is continued to, if MAC
Address is correct, then receives remaining IP TYPE, virtual packet header, UDP port number and long data packet.These data receivers finish
Afterwards, the data that Bao Wenzhong comes are exactly real image data, at this point, these image datas can be received FIFO by this system
In module.Ethernet sending module be then after entire lucky imaging algorithm processing module carries out the process of image procossing,
Host computer is sent by resulting result.The transmission flow of Ethernet first sends lead code and retransmits MAC as shown in the right side Fig. 3
Address, IP TYPE, virtual packet header, UDP port number, long data packet and real image data (i.e. processing result).
The DDR3 memory module, function are the caching received all images data of Ethernet, and when needed, for choosing
Module and registration module provide data.
The data that the ethernet module is transmitted to DDR3 memory module have to be transitioned into DDR3 storage by fifo module
Module because by the data that the udp protocol of gigabit Ethernet is sent be send in the form of data packet it is past.In one packet
The data in face can not be saved directly in DDR3 memory module, and with this, this system plays a transitional function using fifo module.
The DDR3 memory module, its significance lies in that being mentioned to carry out the comparison of pixel maximum and carrying out subsequent processing
For data；Due to the data of Ethernet be FPGA core core is sent to by data packet form, so, compare maximum value just not
It can be carried out simultaneously during receiving data.In conclusion this system data are first stored in DDR3 memory module again according to
Secondary reading is compared.
The host computer can be using the PC for being mounted with Ethernet transmission-receiving function software, the ethernet module, function
It is to realize the image data for receiving and sending over from host computer, data is sent to DDR3 memory module by fifo module, and
And after the completion of entire lucky imaging algorithm processing module, image is returned into host computer by ethernet module.It therefore, should be with
Too net module can be subdivided into again sends and receivees two modules.
The lucky imaging algorithm processing module is selected for receiving the image in DDR3 memory module and handling it
It maximum preceding 1% image of pixel value and carries out being registrated superimposed high-definition picture and is sent to VGA display module, ether out
Net module.
Specific embodiments of the present invention are explained in detail above in conjunction with attached drawing, but the present invention is not limited to above-mentioned realities
Example is applied, it within the knowledge of a person skilled in the art, can also be without departing from the purpose of the present invention
Various changes can be made.
Claims (3)
1. it is a kind of based on Ethernet transmission the lucky imaging system of FPGA, it is characterised in that: including host computer, FPGA development board,
VGA display；FPGA development board include ethernet module, fifo module, DDR3 write data module, DDR3 data reading module,
DDR3 memory module, lucky imaging algorithm processing module, VGA display module；
The host computer is used to send the images to the ethernet module of FPGA development board by the udp protocol of gigabit Ethernet；
The ethernet module is for transferring data to fifo module after receiving the image data that host computer is sent and connecing
It receives the image data sent after lucky imaging algorithm processing module processing and returns to host computer；
Image data of the fifo module for coming transmitted by transition ethernet module is simultaneously sent to DDR3 and writes data module；
The DDR3 writes data module and is used to receive the image data transmitted from ethernet module by fifo module, and will
These data are saved in DDR3 memory module；
The DDR3 data reading module by the image data in DDR3 memory module for reading out and being sent to lucky imaging
Algorithm processing module is handled；
The DDR3 memory module is for storing the image data that fifo module transmits；
The lucky imaging algorithm processing module selects picture for receiving the image in DDR3 memory module and handling it
Maximum preceding 1% image of plain value simultaneously carries out being registrated superimposed high-definition picture and is sent to VGA display module, Ethernet mould
Block；
The VGA display module is for driving VGA display to lucky imaging algorithm processing module treated high resolution graphics
As data are shown, VGA display is for showing high resolution image data.
2. the FPGA lucky imaging system according to claim 1 based on Ethernet transmission, it is characterised in that: described upper
Machine is using the PC for having gigabit Ethernet transmission-receiving function or the camera with Ethernet interface；The ethernet module uses
RTL8211EG ethernet PHY chip.
3. a kind of lucky imaging method of FPGA based on Ethernet transmission, it is characterised in that: specific step is as follows for the method:
Step1, first host computer send the images to the ethernet module of FPGA development board by the udp protocol of gigabit Ethernet；
Step2, ethernet module transfer data to fifo module after receiving the image data that host computer is sent；
The image data that comes transmitted by Step3, fifo module transition ethernet module is simultaneously sent to DDR3 and writes data module；
Step4, DDR3 write data module and receive the image data that transmits from ethernet module by fifo module, and by this
A little data are saved in DDR3 memory module；
Image data in DDR3 memory module is read out and is sent to lucky imaging and calculated by Step5, DDR3 data reading module
Method processing module is handled；
Step6, lucky imaging algorithm processing module receive the image in DDR3 memory module and handle it, select pixel
It is worth maximum preceding 1% image and carrying out and is registrated that superimposed high-definition picture is sent to ethernet module and VGA shows mould
Block；
Step7, ethernet module receive the image data sent after lucky imaging algorithm processing module processing and return to
Position machine；
Step8, VGA display module drive VGA display to lucky imaging algorithm processing module treated high-definition picture
Data are shown.
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