CN109343642A - A kind of offbeat form voltage-reference with overheat protector - Google Patents

A kind of offbeat form voltage-reference with overheat protector Download PDF

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Publication number
CN109343642A
CN109343642A CN201811462883.2A CN201811462883A CN109343642A CN 109343642 A CN109343642 A CN 109343642A CN 201811462883 A CN201811462883 A CN 201811462883A CN 109343642 A CN109343642 A CN 109343642A
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China
Prior art keywords
coupled
resistance
collector
base stage
transistor
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CN201811462883.2A
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Chinese (zh)
Inventor
杨燕
何林峰
陈娇
赵健雄
熊挺
王滨
陈霞
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Chengdu University of Information Technology
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Chengdu University of Information Technology
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Priority to CN201811462883.2A priority Critical patent/CN109343642A/en
Publication of CN109343642A publication Critical patent/CN109343642A/en
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/569—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses a kind of offbeat form voltage-reference with overheat protector, including high-accuracy hysteresis overheat protector detection circuit, power supply judgement supply circuit and offbeat form Low Drift Temperature benchmark source generating circuit.Offbeat form voltage-reference with overheat protector, utilize the innovation of structure, the detection circuit of overheat protector is introduced at the power supply of a reference source, the working condition of reference source circuit is accurately controlled by high-accuracy hysteresis overheat protector detection circuit, to protect circuit work within the scope of normal temperature, and during generating reference voltage, the reference voltage of zero-temperature coefficient is generated using unconventional circuit structure, even if the same triode is the generation for participating in positive temperature coefficient, also assist in the generation of negative temperature coefficient, and it is compensated and is adjusted with a zener diode, while guaranteeing overheat protector characteristic, also ensure that a reference source has high-performance.

Description

A kind of offbeat form voltage-reference with overheat protector
Technical field
The present invention relates to the reference source circuits of integrated circuit fields, more specific to be still not exclusively to a kind of band excess temperature The offbeat form voltage reference source circuit of protection.
Background technique
Reference source circuit is widely used in national defence, industry, civilian each as component part particularly important in integrated circuit A field, effect be export a stabilization, it is accurate, with temperature big drift do not occur, occur with the variation of backend load Fluctuation, extension not at any time and the power supply changed.It is divided into reference voltage source and reference current source according to the type difference of output, And the application of reference voltage source is more universal.Due to the development of electronic information industry, from artificial intelligence (Artificial Intelligence, AI), embedded development to system on chip (System on Chip, SoC), various cutting edge technologies all with collection It is closely related at circuit design.And reference source circuit is as one of module mostly important in IC system, not only it is needed The amount of asking increases steadily, and simultaneously for indices such as its performance parameters, more stringent requirements are proposed.But it is normally producing and using In, circuit normal work can generate a large amount of thermal energy, cause the temperature of chip and circuit board to increase, so that chip and circuit work It is abnormal, be easy to cause the serious errors such as operation mistake, logical value confusion, result even in chip and burn, cause not it is contemplated that Loss.Existing a reference source when chip temperature is excessively high, still can normal power supply, cause the constant temperature of chip to rise, work as temperature Degree rises to a certain degree, leads to wafer damage, to damage entire circuit.And a reference source is the power supply of entire chip, in base A temperature sensing circuit is introduced at quasi- source, can be very good the operating temperature for controlling entire chip, when temperature is more than predetermined value, A reference source stops power supply, and circuit stops working, and when chip temperature drops in normal range (NR), a reference source generates reference voltage again For chip circuit power supply, circuit is worked normally.More loads will not be brought to the power consumption of entire chip in this way, and can be played very Good temperature control action.For overheat protector, if overheat protector is triggered, if not having when chip temperature reaches set temperature There is temperature hysteresis, can resume work immediately once temperature is lower than setting, overheat protector then and once again be triggered, in this way, finally The temperature for only resulting in chip is maintained always near overheat protector temperature, can not really be realized after triggering overheat protector, Make chip cooling technique, just resume work, the work of prolonged periods will lead to chip internal circuits under hot operation state Unpredictable failure, so as to lead to the paralysis of whole system.If being re-introduced into a cooling recovery, in temperature In the design of protection, it is necessary to which a lowest temperature is low for ensuring to be down to when the temperature of chip from high temperature as recovery temperature Resume work when warm, and this temperature is not triggered when chip temperature is from low-temperature-rise to high temperature.The triggering temperature of overheat protector Section between degree and recovery temperature, as temperature hysteresis.The existing current stage, usual way is to pass through heat at external power supply The input of quick resistance control external power supply, can not realize integrated this purpose well.And temperature coefficient, as judge base The most important index of quasi- source circuit performance quality is always that professional studies improved direction.How rationally, accurately to temperature Degree detect and accurately control the generation of Low Drift Temperature a reference source reference voltage, is the problem that those skilled in the art face. One of solution to the problems described above is exactly to access temperature sensing circuit in benchmark source generating circuit, is led to directly in a reference source Excess temperature detects the generation for being accurately controlled reference voltage.It accurately generates power supplying control signal and generation one is high performance low Temperature drift reference voltage is one of those skilled in the art's problems faced.
Summary of the invention
In view of one or more problems in the prior art, the present invention provides a kind of unconventional knot with overheat protector Structure voltage-reference, comprising:
High-accuracy hysteresis overheat protector detection circuit has the first power input, third power input, enabled output End, the first power input terminate the first positive supply, and third power input ground connection, enabling output end is next stage circuit There is provided one makes to can control signal with sluggish, be used to detect whole reference source circuit whether excess temperature and one band of output it is sluggish Make can control signal；
Power supply adjudicates supply circuit, has second source input terminal, enabled receiving end, power supply output end, second source Input the second positive supply of termination, enabled receiving end reception upper level output makes can control signal, under power supply output end is Primary circuit provides voltage, is used to receive making to can control signal and judging whether it disconnects to next stage for upper level offer Power supply；
Offbeat form Low Drift Temperature benchmark source generating circuit has power supply receiving end, third power input, a reference source defeated Outlet, power supply receiving end receive the voltage of upper level output, third power output end ground connection, the output of benchmark source output terminal Reference voltage signal, offbeat form Low Drift Temperature benchmark source generating circuit are simultaneously participated in using the same transistor and generate positive temperature Coefficient and negative temperature coefficient, and positive temperature coefficient is compensated using a zener diode, reach zero-temperature coefficient.
The high-accuracy hysteresis overheat protector detection circuit, comprising:
First PMOS tube, has grid, source electrode and drain electrode, and source electrode is coupled to the first power input；
Second PMOS tube, has grid, source electrode and drain electrode, and source electrode is coupled to the first power input and the first PMOS tube Source electrode, grid are coupled to the first PMOS tube grid；
First operational amplifier, has reverse side, in-phase end and output end, and output end is coupled to the grid of the first PMOS tube The grid of pole and the second PMOS tube；
First PNP bipolar junction transistor, has collector, base stage and emitter, and emitter is coupled to the first PMOS tube Drain electrode and the first operational amplifier reverse side, base stage be coupled to the first PNP bipolar junction transistor collector and third electricity Source input terminal, collector are coupled to the base stage and third power input of the first PNP bipolar junction transistor；
First resistor has a first end and a second end, and first end is coupled to the drain electrode and the first operation of the second PMOS tube Amplifier in-phase end；
2nd PNP bipolar junction transistor, has collector, base stage and emitter, and emitter is coupled to first resistor Second end, base stage are coupled to the base stage of the first PNP bipolar junction transistor, the collector of the first PNP bipolar junction transistor, second The collector and third power input of PNP bipolar junction transistor, collector are coupled to the base of the first PNP bipolar junction transistor Pole, the collector of the first PNP bipolar junction transistor, the 2nd PNP bipolar junction transistor base stage and third power input；
Third PMOS tube, has grid, source electrode and drain electrode, and source electrode is coupled to the source electrode of the first PMOS tube, the 2nd PMOS The source electrode of pipe and the first power input, grid are coupled to the grid of the first PMOS tube, the grid of the second PMOS tube and first The output end of operational amplifier；
Second resistance has a first end and a second end, and first end is coupled to the drain electrode of third PMOS tube, second end coupling It is connected to the base stage of the first PNP bipolar junction transistor, collector, the 2nd PNP bipolar junction transistor of the first PNP bipolar junction transistor Base stage, the 2nd PNP bipolar junction transistor collector and third power input；
4th PMOS tube, has grid, source electrode and drain electrode, and source electrode is coupled to the source electrode of the first PMOS tube, the 2nd PMOS The source electrode of pipe, the source electrode of third PMOS tube and the first power input, grid are coupled to the grid of the first PMOS tube, second The grid of the grid of PMOS tube, the output end of the first operational amplifier and third PMOS tube；
5th PMOS tube, has grid, source electrode and drain electrode, and source electrode is coupled to the source electrode of the first PMOS tube, the 2nd PMOS The source electrode of pipe, the source electrode of third PMOS tube, the 4th PMOS tube source level and the first power input, grid is coupled to first The grid of PMOS tube, the grid of the second PMOS tube, the output end of the first operational amplifier, the grid of third PMOS tube and the 4th The grid of PMOS tube；
3rd resistor has a first end and a second end, and first end is coupled to the drain electrode of the 4th PMOS tube；
4th resistance, has a first end and a second end, and first end is coupled to the second end of 3rd resistor, second end coupling It is connected to the base stage of the first PNP bipolar junction transistor, collector, the 2nd PNP bipolar junction transistor of the first PNP bipolar junction transistor Base stage, the collector of the 2nd PNP bipolar junction transistor, the second end of second resistance and third power input；
5th resistance, has a first end and a second end, and first end is coupled to the drain electrode of the 5th PMOS tube；
6th resistance, has a first end and a second end, and first end is coupled to the second end of the 5th resistance, second end coupling It is connected to the base stage of the first PNP bipolar junction transistor, collector, the 2nd PNP bipolar junction transistor of the first PNP bipolar junction transistor Base stage, the collector of the 2nd PNP bipolar junction transistor, the second end of second resistance, the second end of the 4th resistance and third electricity Source input terminal；
Second operational amplifier, has in-phase end, reverse side and output end, and in-phase end is coupled to the second of 3rd resistor The first end at end and the 4th resistance, reverse side are coupled to the drain electrode of third PMOS tube and the first end of second resistance；
Third operational amplifier, has in-phase end, reverse side and output end, and in-phase end is coupled to the leakage of third PMOS tube Pole, the first end of second resistance and second operational amplifier reverse side, reverse side is coupled to the second end of the 5th resistance With the first end of the 6th resistance；
First phase inverter, has input terminal and output end, and input terminal is coupled to the output end of second operational amplifier；
Second phase inverter, has input terminal and output end, and input terminal is coupled to the output end of third operational amplifier；
First basic RS filpflop, has S input terminal, R input and Q output, and R input is coupled to the first reverse phase The output end of device, the end S are coupled to the output end of the second phase inverter, and Q output is coupled to enabled output end.
The power supply adjudicates supply circuit, comprising:
7th resistance, has a first end and a second end, and first end is coupled to second source input terminal；
6th PMOS tube, there is grid, source electrode and drain electrode, and source electrode is coupled to the second end of the 7th resistance, grid coupling To enabled receiving end, drain electrode is coupled to power supply output end.
The offbeat form Low Drift Temperature benchmark source generating circuit, comprising:
8th resistance, has a first end and a second end, and first end is coupled to power supply receiving end；
9th resistance, has a first end and a second end, and first end is coupled to the second end of the 8th resistance；
First NPN bipolar transistor, has collector, emitter and base stage, and collector is coupled to the 9th resistance Second end, base stage are coupled to the second end of the 9th resistance and the collector of the first NPN bipolar transistor；
Second NPN bipolar transistor, has collector, emitter and base stage, and collector is coupled to power supply receiving end With the first end of the 8th resistance, base stage is coupled to the emitter of the first NPN bipolar transistor；
First zener diode, has a first end and a second end, and first end is coupled to the first NPN bipolar transistor The base stage of emitter and the second NPN bipolar transistor, second end are coupled to third power input；
Tenth resistance, has a first end and a second end, and first end is coupled to the second end and the 9th resistance of the 8th resistance First end；
Eleventh resistor has a first end and a second end, and first end is coupled to the second end of the tenth resistance；
3rd PNP bipolar junction transistor, has collector, emitter and base stage, and emitter is coupled to eleventh resistor Second end, base stage is coupled to the emitter of the second NPN bipolar transistor, and collector is coupled to third power input With the second end of the first zener diode；
Twelfth resistor has a first end and a second end, first end be coupled to power supply receiving end, the 8th resistance first The collector at end and the second NPN bipolar transistor；
Thirteenth resistor has a first end and a second end, first end be coupled to power supply receiving end, the 8th resistance first It holds, the first end of the collector of the second NPN bipolar transistor and twelfth resistor；
4th PNP bipolar junction transistor, has collector, emitter and base stage, and emitter is coupled to twelfth resistor Second end；
5th PNP bipolar junction transistor, has collector, emitter and base stage, and emitter is coupled to thirteenth resistor Second end, base stage is coupled to the base stage of the 4th PNP bipolar junction transistor, and collector is coupled to the 4th ambipolar crystalline substance of PNP The base stage of the base stage of body pipe and the 5th PNP bipolar junction transistor；
6th PNP bipolar junction transistor has collector, emitter and base stage, and it is bipolar that emitter is coupled to the 4th PNP The collector of transistor npn npn, collector are coupled to the base stage of the 6th PNP bipolar junction transistor；
7th PNP bipolar junction transistor has collector, emitter and base stage, and it is bipolar that emitter is coupled to the 4th PNP The collector of the base stage of transistor npn npn, the base stage of the 5th PNP bipolar junction transistor and the 5th PNP bipolar junction transistor, base stage It is coupled to the base stage of the 6th PNP bipolar junction transistor and the collector of the 6th PNP bipolar junction transistor；
8th NPN bipolar transistor has collector, emitter and base stage, and it is bipolar that collector is coupled to the 6th PNP The base stage of the base stage of transistor npn npn, the collector of the 6th PNP bipolar junction transistor and the 7th PNP bipolar junction transistor, base stage It is coupled to the second end of the tenth resistance and the first end of eleventh resistor；
9th NPN bipolar transistor has collector, emitter and base stage, and it is bipolar that collector is coupled to the 8th NPN The emitter of transistor npn npn, base stage are coupled to the emitter and the 3rd PNP bipolar junction transistor of the second NPN bipolar transistor Base stage；
Tenth NPN bipolar transistor has collector, emitter and base stage, and it is bipolar that collector is coupled to the 7th PNP The collector of transistor npn npn, base stage are coupled to the emitter of the second NPN bipolar transistor, the 3rd PNP bipolar junction transistor Base stage and the 9th NPN bipolar transistor base stage；
14th resistance, has a first end and a second end, and first end is coupled to the transmitting of the second NPN bipolar transistor Pole, the base stage of the 3rd PNP bipolar junction transistor, the base stage of the 9th NPN bipolar transistor and the tenth NPN bipolar transistor Base stage, second end are coupled to the emitter of the 9th NPN bipolar transistor；
15th resistance, has a first end and a second end, and first end is coupled to the transmitting of the 9th NPN bipolar transistor The second end of pole and the 14th resistance, second end be coupled to third power input, the first zener diode second end and The collector of 3rd PNP bipolar junction transistor；
11st NPN bipolar transistor has collector, emitter and base stage, and it is bis- that collector is coupled to the tenth NPN The emitter of bipolar transistor, emitter are coupled to third power input, the second end of the first zener diode, third The second end of the collector of PNP bipolar junction transistor and the 15th resistance；
16th resistance, has a first end and a second end, and first end is coupled to the transmitting of the 9th NPN bipolar transistor Pole, the second end of the 14th resistance and the 15th resistance first end, second end is coupled to benchmark source output terminal；
12nd NPN bipolar transistor, has collector, emitter and base stage, and collector is coupled to power supply and receives End, the first end of the 8th resistance, the collector of the second NPN bipolar transistor, the first end of twelfth resistor and the 13rd electricity The first end of resistance, base stage be coupled to the emitter of the second NPN bipolar transistor, the 3rd PNP bipolar junction transistor base stage, Base stage, the base stage of the tenth NPN bipolar transistor and the first end of the 14th resistance of 9th NPN bipolar transistor；
Second zener diode, has a first end and a second end, and first end couples the 12nd NPN bipolar transistor Emitter；
17th resistance, has a first end and a second end, and first end is coupled to the second end of the second zener diode, Second end is coupled to the base stage of the 11st NPN bipolar transistor；
18th resistance, has a first end and a second end, and first end is coupled to the base of the 11st NPN bipolar transistor The second end of pole and the 17th resistance, second end are coupled to third power input, the second end of the first zener diode, Collector, the second end of the 15th resistance and the emitter of the 11st NPN bipolar transistor of three PNP bipolar junction transistors；
First capacitor has a first end and a second end, and first end is coupled to benchmark source output terminal and the 16th resistance Second end, second end are coupled to third power input, the second end of the first zener diode, the 3rd PNP bipolar transistor The collector of pipe, the second end of the 15th resistance, the emitter of the 11st NPN bipolar transistor and the 18th resistance second End.
First operational amplifier, second operational amplifier and the third operational amplifier, which is characterized in that use PMOS is as input to the two-level operating amplifier of pipe.
The resistance value R3 of the 3rd resistor, the 4th resistance R4, the 5th resistance resistance value R5 and the 6th resistance resistance Value R6 substantially meets R3+R4=R5+R6, i.e. the sum of resistance value of the resistance value of 3rd resistor and the 4th resistance is equal to the 5th resistance Resistance value and the 6th resistance the sum of resistance value.
The high-accuracy hysteresis overheat protector detection circuit passes through second operational amplifier, third operational amplifier, the The operation of one phase inverter, the second phase inverter and the first rest-set flip-flop, generation is the signal with lagging characteristics.
The eleventh resistor, the 3rd PNP bipolar junction transistor, the 8th NPN bipolar transistor and the 9th NPN are bipolar Transistor npn npn constitutes a feedback loop, for maintaining the stabilization of benchmark source generating circuit.
The 4th PNP bipolar junction transistor, the 5th PNP bipolar junction transistor, the 6th PNP bipolar junction transistor, The breadth length ratio of seven PNP bipolar junction transistors is equal.
11st NPN bipolar transistor generates negative temperature coefficient, the 9th NPN bipolar transistor and 11st NPN bipolar transistor collective effect generates positive temperature coefficient.
A kind of offbeat form voltage-reference with overheat protector provided by the invention, allows to change in very little amplitude In the case where production technology, using the improvement and innovation of structure, the inspection of an overheat protector is introduced at the power supply of a reference source Slowdown monitoring circuit accurately controls the work of reference source circuit by the enable signal of the output of high-accuracy hysteresis overheat protector detection circuit Make state, so that the work of very effective protection circuit is within the scope of normal temperature；And during generating reference voltage, The reference voltage of zero-temperature coefficient is generated using unconventional mode, even if the same triode is to participate in positive temperature coefficient It generates, also assists in the generation of negative temperature coefficient, and compensated and adjusted with a zener diode, be effectively reduced circuit Chip design cost is greatly saved in the area of practical domain.The voltage-reference for solving currently existing technology works non- The technical problem that the harsh environment of normal temperature causes circuit to damage.
Detailed description of the invention
The specific embodiment that the present invention will be described in detail below with reference to the accompanying drawings, wherein identical appended drawing reference indicates identical Component or feature.
Fig. 1 shows a kind of offbeat form voltage-reference with overheat protector proposed according to an embodiment of the present invention Module diagram；
Fig. 2 shows the high-accuracy hysteresis overheat protector detection circuit schematic diagrames proposed according to an embodiment of the present invention；
Fig. 3 shows the power supply judgement supply circuit schematic diagram proposed according to an embodiment of the present invention；
Fig. 4 shows the offbeat form Low Drift Temperature benchmark source generating circuit signal proposed according to an embodiment of the present invention Figure；
Fig. 5 shows a kind of offbeat form voltage-reference with overheat protector proposed according to an embodiment of the present invention Temperature coefficient emulates schematic diagram.
Specific embodiment
Specific embodiment below represents exemplary embodiment of the present invention, and substantially merely illustrative explanation rather than Limitation.In the following description, in order to provide a thorough understanding of the present invention, a large amount of specific details are elaborated.However, for ability Domain those of ordinary skill it is evident that: these specific details are not required for the present invention.In other instances, In order to avoid obscuring the present invention, well known circuit, material or method are not specifically described.
In the description, it is specific described in the embodiment to refer to that " one embodiment " or " embodiment " means to combine Feature, structure or characteristic are included at least one embodiment of the present invention.Term " in one embodiment " is in specification In each position occur not all referring to identical embodiment, nor mutually exclusive other embodiments or variable implementing Example.All features disclosed in this specification or disclosed all methods or in the process the step of, in addition to mutually exclusive feature And/or other than step, it can combine in any way.In addition, it should be understood by one skilled in the art that provided herein Diagram is provided to the purpose of explanation, and diagram is not necessarily drawn to scale.It should be appreciated that when claiming " element " " connection To " or when " coupled " to another element, it, which can be, is directly connected or coupled to another element or there may be intermediary elements. On the contrary, intermediary element is not present when claiming element " being directly connected to " or " being directly coupled to " another element.Identical attached drawing mark Note indicates identical element.It when title " element " " reception " a certain signal, can make directly to receive, switch, electricity can also be passed through Resistance, level displacement shifter, signal processing unit etc. receive.Term "and/or" used herein includes that one or more correlations are listed Project any and all combinations.
A kind of offbeat form voltage reference source module with overheat protector that Fig. 1 is proposed according to an embodiment of the present invention Schematic diagram, comprising: high-accuracy hysteresis overheat protector detection circuit, power supply adjudicate supply circuit, offbeat form Low Drift Temperature benchmark Source generating circuit.
The high-accuracy hysteresis overheat protector detection circuit has the first power input (VDD1), third power input (GND), enabled output end are held, the first power input terminates the first positive supply, and third power input ground connection enables defeated Outlet provides one for next stage circuit to be made to can control signal (Signl_EN) with sluggish, is used to detect whole a reference source electricity Road whether excess temperature and output one band sluggishness make can control signal；The power supply adjudicates supply circuit, has second source defeated Enter end (VDD2), enabled receiving end, power supply output end, second source input the second positive supply of termination enables to receive termination That receives upper level output makes can control signal, and output end of powering provides operating voltage (Power) for next stage circuit, is used for Making to can control signal and judging whether it disconnects the power supply to next stage for upper level offer is provided；The offbeat form low temperature Benchmark source generating circuit is floated, there is power supply receiving end, third power input (GND), benchmark source output terminal (Vref), power supply Receiving end receives the voltage of upper level output, third power output end ground connection, benchmark source output terminal outputting reference voltage letter Number, offbeat form Low Drift Temperature benchmark source generating circuit is simultaneously participated in using the same transistor and generates positive temperature coefficient and subzero temperature Coefficient is spent, and compensates positive temperature coefficient using a zener diode, reaches zero-temperature coefficient.
The high-accuracy hysteresis overheat protector detection circuit schematic diagram that Fig. 2 is proposed according to an embodiment of the present invention, comprising: the One PMOS tube (M1), the second PMOS tube (M2), the first operational amplifier (OP1), the first PNP bipolar junction transistor (Q1), first Resistance (R1), the 2nd PNP bipolar junction transistor (Q2), third PMOS tube (M3), second resistance (R2), the 4th PMOS tube (M4), 5th PMOS tube (M5), 3rd resistor (R3), the 4th resistance (R4), the 5th resistance (R5), the 6th resistance (R6), the second operation are put Big device (OP2), third operational amplifier (OP3), the first phase inverter (INV1), the second phase inverter (INV2), the first basic RS touching It sends out device (RS1).
High-accuracy hysteresis overheat protector detection circuit, comprising: the first PMOS tube (M1) has grid, source electrode and drain electrode, Source electrode is coupled to the first power input；Second PMOS tube (M2), has grid, source electrode and drain electrode, and source electrode is coupled to first Power input and the first PMOS tube source electrode, grid are coupled to the first PMOS tube grid；First operational amplifier (OP1), tool There are reverse side, in-phase end and output end, output end is coupled to the grid of the first PMOS tube and the grid of the second PMOS tube；First PNP bipolar junction transistor (Q1), have collector, base stage and emitter, emitter be coupled to the first PMOS tube drain electrode and First operational amplifier reverse side, base stage are coupled to the collector and third power input of the first PNP bipolar junction transistor, Its collector is coupled to the base stage and third power input of the first PNP bipolar junction transistor；First resistor (R1) has first End and second end, first end are coupled to drain electrode and the first operational amplifier in-phase end of the second PMOS tube；2nd PNP is ambipolar Transistor (Q2), has collector, base stage and emitter, and emitter is coupled to the second end of first resistor, base stage coupling To the base stage of the first PNP bipolar junction transistor, the collector of the first PNP bipolar junction transistor, the 2nd PNP bipolar junction transistor Collector and third power input, it is ambipolar that collector is coupled to the base stage of the first PNP bipolar junction transistor, the first PNP The collector of transistor, the base stage of the 2nd PNP bipolar junction transistor and third power input；Third PMOS tube (M3), has Grid, source electrode and drain electrode, source electrode are coupled to the source electrode of the first PMOS tube, the source electrode of the second PMOS tube and the first power input End, grid are coupled to the output end of the grid of the first PMOS tube, the grid of the second PMOS tube and the first operational amplifier；Second Resistance (R2), has a first end and a second end, and first end is coupled to the drain electrode of third PMOS tube, and second end is coupled to first The base stage of PNP bipolar junction transistor, the collector of the first PNP bipolar junction transistor, the 2nd PNP bipolar junction transistor base stage, The collector and third power input of 2nd PNP bipolar junction transistor；4th PMOS tube (M4) has grid, source electrode and leakage Pole, it is defeated that source electrode is coupled to the source electrode of the first PMOS tube, the source electrode of the second PMOS tube, the source electrode of third PMOS tube and the first power supply Enter end, grid is coupled to the grid of the first PMOS tube, the grid of the second PMOS tube, the output end of the first operational amplifier and the The grid of three PMOS tube；5th PMOS tube (M5), has grid, source electrode and drain electrode, and source electrode is coupled to the source of the first PMOS tube Pole, the source electrode of the second PMOS tube, the source electrode of third PMOS tube, the 4th PMOS tube source level and the first power input, grid Be coupled to the grid of the first PMOS tube, the grid of the second PMOS tube, the output end of the first operational amplifier, third PMOS tube grid The grid of pole and the 4th PMOS tube；3rd resistor (R3), has a first end and a second end, and first end is coupled to the 4th PMOS tube Drain electrode；4th resistance (R4), has a first end and a second end, and first end is coupled to the second end of 3rd resistor, and second End is coupled to the base stage of the first PNP bipolar junction transistor, the collector of the first PNP bipolar junction transistor, the 2nd ambipolar crystalline substance of PNP The base stage of body pipe, the collector of the 2nd PNP bipolar junction transistor, the second end of second resistance and third power input；5th Resistance (R5), has a first end and a second end, and first end is coupled to the drain electrode of the 5th PMOS tube；6th resistance (R6), has First end and second end, first end are coupled to the second end of the 5th resistance, and second end is coupled to the first PNP bipolar transistor The base stage of pipe, the collector of the first PNP bipolar junction transistor, the base stage of the 2nd PNP bipolar junction transistor, the 2nd PNP are ambipolar The collector of transistor, the second end of second resistance, the second end and third power input of the 4th resistance；Second operation amplifier Device (OP2), has in-phase end, reverse side and output end, and in-phase end is coupled to the second end and the 4th resistance of 3rd resistor First end, reverse side are coupled to the drain electrode of third PMOS tube and the first end of second resistance；Third operational amplifier (OP3), With in-phase end, reverse side and output end, in-phase end is coupled to the drain electrode of third PMOS tube, the first end of second resistance and The reverse side of two operational amplifiers, reverse side are coupled to the second end of the 5th resistance and the first end of the 6th resistance；First Phase inverter (INV1), has input terminal and output end, and input terminal is coupled to the output end of second operational amplifier；Second reverse phase Device (INV2), has input terminal and output end, and input terminal is coupled to the output end of third operational amplifier；First basic RS touching It sends out device (RS1), there is S input terminal, R input and Q output, R input is coupled to the output end of the first phase inverter, S End is coupled to the output end of the second phase inverter, and Q output is coupled to enabled output end.
Wherein, first operational amplifier, second operational amplifier and third operational amplifier, using PMOS conduct Input the two-level operating amplifier to pipe；The resistance value of the resistance value R3 of the 3rd resistor, the 4th resistance R4, the 5th resistance The resistance value R6 of R5 and the 6th resistance substantially meet R3+R4=R5+R6, the i.e. resistance value of the resistance value of 3rd resistor and the 4th resistance The sum of be equal to the 5th resistance resistance value and the 6th resistance the sum of resistance value；The high-accuracy hysteresis overheat protector detection circuit is logical The operation of second operational amplifier, third operational amplifier, the first phase inverter, the second phase inverter and the first rest-set flip-flop is crossed, is produced Raw is the signal with lagging characteristics.
For high-accuracy hysteresis overheat protector detection circuit, we are utilized by a common basic PTAT a reference source Voltage numerical value at different temperatures that it is exported is different, voltage PTAT a reference source exported using the principle of electric resistance partial pressure into The appropriate tap of row forms the upper and lower bound of overheat protector triggering temperature.And 3rd resistor, the 4th resistance, the 5th in Fig. 2 Suitable voltage value is arranged in resistance, the 6th resistance, meets relationship R3+R4=R5+R6, the i.e. resistance value of 3rd resistor and the 4th resistance The sum of resistance value be equal to the resistance value of the 5th resistance and the sum of the resistance value of the 6th resistance, guaranteed with this in the same bias voltage and same Under one power input voltage, the current value of two branches is almost equal, guarantees the accuracy of sampling.In amplifier output end and RS Trigger input is inserted into phase inverter, mainly carries out shaping to the output of operational amplifier, do binaryzation to the output of amplifier Processing shortens amplifier and exported rising edge/failing edge temperature range, while preventing the output because of amplifier just in threshold voltage Near, cause trigger to fall into indefinite state, generation is accidentally turned over.When it triggers overheat protector, enable signal exports high potential, normal work When making, enable signal output is low potential.
Power supply that Fig. 3 is proposed according to an embodiment of the present invention adjudicates supply circuit schematic diagram, comprising: the 7th resistance, the Six PMOS tube.
The power supply adjudicates supply circuit, comprising: the 7th resistance (R7) has a first end and a second end, first end coupling It is connected to second source input terminal；6th PMOS tube (M6), there is grid, source electrode and drain electrode, and source electrode is coupled to the of the 7th resistance Two ends, grid are coupled to enabled receiving end, and drain electrode is coupled to power supply output end.
Supply circuit is adjudicated for power supply, we are by the Characteristics Control that is connected when its grid low potential of PMOS tube to next The power supply of grade circuit.It is defeated to the grid of the 6th PMOS tube when high-accuracy hysteresis overheat protector detection circuit triggers overheat protector Enter a high potential, then the 6th PMOS tube turns off, and stops the power supply to next stage circuit.When temperature is restored in normal range When, the conducting of the 6th PMOS tube continues as the power supply of rear stage circuit.
The offbeat form Low Drift Temperature benchmark source generating circuit schematic diagram that Fig. 4 is proposed according to an embodiment of the present invention, packet Include: the 8th resistance (R8), the 9th resistance (R9), the first NPN bipolar transistor (Q1), the second NPN bipolar transistor (Q2), First zener diode (D1), the tenth resistance (R10), eleventh resistor (R11), the 3rd PNP bipolar junction transistor (Q3), the tenth Two resistance (R12), thirteenth resistor (R13), the 4th PNP bipolar junction transistor (Q4), the 5th PNP bipolar junction transistor (Q5), 6th PNP bipolar junction transistor (Q6), the 7th PNP bipolar junction transistor (Q7), the 8th NPN bipolar transistor (Q8), the 9th NPN bipolar transistor (Q9), the tenth NPN bipolar transistor (Q10), the 14th resistance (R14), the 15th resistance (R15), 11st NPN bipolar transistor (Q11), the 16th resistance (R16), the 12nd NPN bipolar transistor (Q12), second are surely Press diode (D2), the 17th resistance (R17), the 18th resistance (R18), first capacitor (C1).
Offbeat form Low Drift Temperature offbeat form Low Drift Temperature benchmark source generating circuit, comprising: the 8th resistance (R8) has First end and second end, first end are coupled to power supply receiving end；9th resistance (R9), has a first end and a second end, the One end is coupled to the second end of the 8th resistance；First NPN bipolar transistor (Q1) has collector, emitter and base stage, Collector is coupled to the second end of the 9th resistance, and base stage is coupled to the second end and the first NPN bipolar transistor of the 9th resistance The collector of pipe；Second NPN bipolar transistor (Q2), has collector, emitter and base stage, and collector is coupled to power supply The first end of receiving end and the 8th resistance, base stage are coupled to the emitter of the first NPN bipolar transistor；First pressure stabilizing, two pole It manages (D1), has a first end and a second end, first end is coupled to the emitter and the 2nd NPN of the first NPN bipolar transistor The base stage of bipolar junction transistor, second end are coupled to third power input；Tenth resistance (R10) has first end and the Two ends, first end are coupled to the second end of the 8th resistance and the first end of the 9th resistance；Eleventh resistor (R11) has the One end and second end, first end are coupled to the second end of the tenth resistance；3rd PNP bipolar junction transistor (Q3) has current collection Pole, emitter and base stage, emitter are coupled to the second end of eleventh resistor, and base stage is coupled to the 2nd ambipolar crystalline substance of NPN The emitter of body pipe, collector are coupled to the second end of third power input and the first zener diode；Twelfth resistor (R12), it has a first end and a second end, it is bis- that first end is coupled to power supply receiving end, the first end of the 8th resistance and the 2nd NPN The collector of bipolar transistor；Thirteenth resistor (R13), has a first end and a second end, and first end is coupled to power supply and receives End, the first end of the 8th resistance, the collector of the second NPN bipolar transistor and the first end of twelfth resistor；4th PNP is bis- Bipolar transistor (Q4), has collector, emitter and base stage, and emitter is coupled to the second end of twelfth resistor；5th PNP bipolar junction transistor (Q5) has collector, emitter and base stage, and emitter is coupled to the second end of thirteenth resistor, Its base stage is coupled to the base stage of the 4th PNP bipolar junction transistor, and collector is coupled to the base stage of the 4th PNP bipolar junction transistor With the base stage of the 5th PNP bipolar junction transistor；6th PNP bipolar junction transistor (Q6) has collector, emitter and base stage, Its emitter is coupled to the collector of the 4th PNP bipolar junction transistor, and collector is coupled to the 6th PNP bipolar junction transistor Base stage；7th PNP bipolar junction transistor (Q7) has collector, emitter and base stage, and it is bis- that emitter is coupled to the 4th PNP The collector of the base stage of bipolar transistor, the base stage of the 5th PNP bipolar junction transistor and the 5th PNP bipolar junction transistor, base Pole is coupled to the base stage of the 6th PNP bipolar junction transistor and the collector of the 6th PNP bipolar junction transistor；8th NPN is ambipolar Transistor (Q8), has collector, emitter and base stage, and collector is coupled to the base stage of the 6th PNP bipolar junction transistor, the The collector of six PNP bipolar junction transistors and the base stage of the 7th PNP bipolar junction transistor, base stage are coupled to the of the tenth resistance The first end at two ends and eleventh resistor；9th NPN bipolar transistor (Q9) has collector, emitter and base stage, collection Electrode is coupled to the emitter of the 8th NPN bipolar transistor, and base stage is coupled to the emitter of the second NPN bipolar transistor With the base stage of the 3rd PNP bipolar junction transistor；Tenth NPN bipolar transistor (Q10) has collector, emitter and base stage, Its collector is coupled to the collector of the 7th PNP bipolar junction transistor, and base stage is coupled to the hair of the second NPN bipolar transistor The base stage of emitter-base bandgap grading, the base stage of the 3rd PNP bipolar junction transistor and the 9th NPN bipolar transistor；14th resistance (R14), tool There is first end and second end, first end is coupled to the emitter of the second NPN bipolar transistor, the 3rd PNP bipolar transistor The base stage of the base stage of pipe, the base stage of the 9th NPN bipolar transistor and the tenth NPN bipolar transistor, second end are coupled to The emitter of 9th NPN bipolar transistor；15th resistance (R15), has a first end and a second end, first end is coupled to The emitter of 9th NPN bipolar transistor and the second end of the 14th resistance, second end be coupled to third power input, The collector of the second end of first zener diode and the 3rd PNP bipolar junction transistor；11st NPN bipolar transistor (Q11), there is collector, emitter and base stage, collector is coupled to the emitter of the tenth NPN bipolar transistor, sends out Emitter-base bandgap grading be coupled to third power input, the second end of the first zener diode, the 3rd PNP bipolar junction transistor collector and The second end of 15th resistance；16th resistance (R16), has a first end and a second end, and it is bis- that first end is coupled to the 9th NPN The first end of the emitter of bipolar transistor, the second end of the 14th resistance and the 15th resistance, second end are coupled to benchmark Source output terminal；12nd NPN bipolar transistor (Q12), has collector, emitter and base stage, and collector is coupled to confession Electric receiving end, the first end of the 8th resistance, the collector of the second NPN bipolar transistor, the first end of twelfth resistor and The first end of 13 resistance, base stage are coupled to the emitter of the second NPN bipolar transistor, the 3rd PNP bipolar junction transistor Base stage, the base stage of the 9th NPN bipolar transistor, the base stage of the tenth NPN bipolar transistor and the 14th resistance first End；Second zener diode (D2), has a first end and a second end, and first end couples the 12nd NPN bipolar transistor Emitter；17th resistance (R17), has a first end and a second end, and first end is coupled to the second of the second zener diode End, second end are coupled to the base stage of the 11st NPN bipolar transistor；18th resistance (R18) has first end and second End, first end are coupled to the base stage of the 11st NPN bipolar transistor and the second end of the 17th resistance, second end coupling To third power input, the second end of the first zener diode, the collector of the 3rd PNP bipolar junction transistor, the 15th electricity The emitter of the second end of resistance and the 11st NPN bipolar transistor；First capacitor (C1), has a first end and a second end, First end is coupled to the second end of benchmark source output terminal and the 16th resistance, and second end is coupled to third power input, The second end of one zener diode, the collector of the 3rd PNP bipolar junction transistor, the second end of the 15th resistance, the 11st NPN The second end of the emitter of bipolar junction transistor and the 18th resistance.
Wherein, the eleventh resistor, the 3rd PNP bipolar junction transistor, the 8th NPN bipolar transistor and the 9th NPN bipolar transistor constitutes a feedback loop, can maintain the stabilization of benchmark source generating circuit；4th PNP is bis- Bipolar transistor, the 5th PNP bipolar junction transistor, the 6th PNP bipolar junction transistor, the width of the 7th PNP bipolar junction transistor are long Than being equal；11st NPN bipolar transistor generates negative temperature coefficient, the 9th NPN bipolar transistor Positive temperature coefficient is generated with the 11st NPN bipolar transistor collective effect.
When starting power supply for offbeat form Low Drift Temperature benchmark source generating circuit power supply, we make following procedure point Analysis: the moment of power supply, R8 to R9 has immediate current, and the base stage of Q1 and collector are in same current potential, then Q1 pipe can be opened. D1 is zener diode, and effect is that voltage is maintained to a higher current potential.For the emitter and supply voltage phase of Q2 Connection, and base voltage be equal to Q1 pipe emitter voltage, it is evident that have very slave power input to the emitter voltage of Q1 pipe Big pressure drop, therefore the collector voltage of Q2 pipe is greater than base voltage, Q2 pipe is opened.The base stage of Q9 and Q10 has biased electrical at this time Pressure, and then built-in current mirror is started to work.After stable working state, we change the branch by adjusting the resistance value of R10 and R11 The electric current on road allows the base voltage of Q3 pipe to stablize, and at this point for Q2, base voltage is lower than emitter voltage, and then Q2 pipe is disconnected It opens, start-up circuit stops working.And the input voltage Jing Guo R8, R10 and R1 pressure drop provides one for the portion of transistor of current mirror A more stable bias voltage, makes its normal work.
By start-up circuit, current mirror is started to work, and R12 and R13 are to adjust resistance, can be by adjusting R12's and R13 The operating current of size change current mirror.Q4, Q5, Q6, Q7 wilson current mirror each other, it is ensured that the consistency of branch current.And Q3, Q8, Q9, R11 constitute a feedback loop.When the electric current of current mirror is slightly bigger than normal, lead to the V of Q8BEBecome larger, and then leads Q8 base voltage is caused to reduce.The corresponding decline of corresponding R11 electric current, makes the V of Q3BEBecome smaller, so that feedback arrives the base stage of Q9, makes on Q9 Emitter current reduce.To maintain the stabilization of current mirror.
For offbeat form Low Drift Temperature benchmark source generating circuit, we analyze Q11 and R18 we it follows that
VBE11=U18 (1)
U18 is the pressure drop on R18, and for R17:
U17=I1×R17 (2)
I1 is the electric current of Q12, D2, R17, R18 branch road, and then we are it can be concluded that pressure drop on R17 are as follows:
Size in view of adjusting resistance as far as possible cannot be too big, and otherwise chip area will increase, so D2 is introduced, balance temperature Coefficient is spent, while playing the role of a protection circuit.Then we can represent the base voltage of Q9, Q10 are as follows:
VB9=VB10=U18+U1+UBR2 (4)
UBR2 be the tube voltage drop of the second zener diode.(1), (2) and (3) is substituted into (4), is obtained:
We analyze Q9 again, base stage and the directly poor V of emitterBE, still can be equal the transmitting of Q9 Pole tension looks at the output voltage of a reference source, then:
Vref=VE9=VB9-VBE9 (6)
By (5) and (6) simultaneous, obtain:
And in observation type (7), there are two VBESubtract each other, that is, Δ V occursBE, produce a positive temperature coefficient.It enables again:
ΔVBE=VBE11-VBE9 (8)
(8) are substituted into (7), are obtained:
By (9), show that a reference source obtains the poor Δ V containing an emitter base voltage in output voltageBEWith a crystalline substance The emitter base voltage V of body pipeBE, the two is by adjusting the resistance value size of R17, R18, in certain proportion generation one zero The a reference source of temperature coefficient.
A kind of offbeat form voltage reference source temperature with overheat protector that Fig. 5 is proposed according to an embodiment of the present invention Coefficient emulates schematic diagram.
The second source input terminal that the example introduces is 5.2V, and negative supply is ground, and by obtaining parameter in Fig. 2, highest is defeated Voltage is 3.31417V, minimum output voltage 3.30892V out, and at 25 DEG C, output voltage 3.30954V.Pass through meter It calculates, temperature coefficient is 8.81ppm/ DEG C, and the temperature of the high performance a reference source with over-temperature protection of high target in the market is fully achieved Spend coefficient index.
In this disclosure used quantifier "one", "an" etc. be not excluded for plural number." first " in text, " Two " etc. are merely represented in the sequencing occurred in the description of embodiment, in order to distinguish like." first ", " second " exist Appearance in claims is only for the purposes of the fast understanding to claim rather than in order to be limited.Right is wanted Any appended drawing reference in book is asked to should be construed as the limitation to range.

Claims (10)

1. a kind of offbeat form voltage-reference with overheat protector, comprising:
High-accuracy hysteresis overheat protector detection circuit has the first power input, third power input, enabled output end, Its first power input terminates the first positive supply, third power input ground connection, and enabled output end mentions for next stage circuit For one make to can control signal with sluggish, be used to detect whole reference source circuit whether one band sluggishness of excess temperature and output Make to can control signal；
Power supply adjudicates supply circuit, has second source input terminal, enabled receiving end, power supply output end, second source input The second positive supply is terminated, enabled receiving end reception upper level output makes can control signal, and power supply output end is next stage Circuit provides voltage, is used to receive making to can control signal and judging whether it disconnects the confession to next stage for upper level offer Electricity；
Offbeat form Low Drift Temperature benchmark source generating circuit has power supply receiving end, third power input, a reference source output End, power supply receiving end receive the voltage of upper level output, third power output end ground connection, and benchmark source output terminal exports base Quasi- voltage signal, offbeat form Low Drift Temperature benchmark source generating circuit are simultaneously participated in using the same transistor and generate positive temperature system Several and negative temperature coefficient, and positive temperature coefficient is compensated using a zener diode, reach zero-temperature coefficient.
2. a kind of offbeat form voltage-reference with overheat protector according to claim 1, which is characterized in that described High-accuracy hysteresis overheat protector detection circuit, comprising:
First PMOS tube, has grid, source electrode and drain electrode, and source electrode is coupled to the first power input；
Second PMOS tube, has grid, source electrode and drain electrode, and source electrode is coupled to the first power input and the first PMOS tube source Pole, grid are coupled to the first PMOS tube grid；
First operational amplifier, have reverse side, in-phase end and output end, output end be coupled to the first PMOS tube grid and The grid of second PMOS tube；
First PNP bipolar junction transistor, has collector, base stage and emitter, and emitter is coupled to the leakage of the first PMOS tube Pole and the first operational amplifier reverse side, base stage be coupled to the first PNP bipolar junction transistor collector and third power supply it is defeated Enter end, collector is coupled to the base stage and third power input of the first PNP bipolar junction transistor；
First resistor has a first end and a second end, and first end is coupled to drain electrode and the first operation amplifier of the second PMOS tube Device in-phase end；
2nd PNP bipolar junction transistor, has collector, base stage and emitter, and emitter is coupled to the second of first resistor End, base stage are coupled to collector, the 2nd PNP of the base stage of the first PNP bipolar junction transistor, the first PNP bipolar junction transistor The collector and third power input of bipolar junction transistor, collector be coupled to the first PNP bipolar junction transistor base stage, The base stage and third power input of the collector of first PNP bipolar junction transistor, the 2nd PNP bipolar junction transistor；
Third PMOS tube, has grid, source electrode and drain electrode, and source electrode is coupled to the source electrode of the first PMOS tube, second PMOS tube Source electrode and the first power input, grid are coupled to the grid of the first PMOS tube, the grid of the second PMOS tube and the first operation The output end of amplifier；
Second resistance has a first end and a second end, and first end is coupled to the drain electrode of third PMOS tube, and second end is coupled to The base stage of first PNP bipolar junction transistor, the collector of the first PNP bipolar junction transistor, the 2nd PNP bipolar junction transistor base Pole, the 2nd PNP bipolar junction transistor collector and third power input；
4th PMOS tube, has grid, source electrode and drain electrode, and source electrode is coupled to the source electrode of the first PMOS tube, second PMOS tube Source electrode, the source electrode of third PMOS tube and the first power input, grid are coupled to the grid of the first PMOS tube, the second PMOS tube Grid, the output end of the first operational amplifier and the grid of third PMOS tube；
5th PMOS tube, has grid, source electrode and drain electrode, and source electrode is coupled to the source electrode of the first PMOS tube, second PMOS tube Source electrode, the source electrode of third PMOS tube, the 4th PMOS tube source level and the first power input, grid is coupled to the first PMOS tube Grid, the grid of the second PMOS tube, the output end of the first operational amplifier, the grid of third PMOS tube and the 4th PMOS tube Grid；
3rd resistor has a first end and a second end, and first end is coupled to the drain electrode of the 4th PMOS tube；
4th resistance, has a first end and a second end, and first end is coupled to the second end of 3rd resistor, and second end is coupled to The base stage of first PNP bipolar junction transistor, the collector of the first PNP bipolar junction transistor, the 2nd PNP bipolar junction transistor base Pole, the collector of the 2nd PNP bipolar junction transistor, the second end of second resistance and third power input；
5th resistance, has a first end and a second end, and first end is coupled to the drain electrode of the 5th PMOS tube；
6th resistance, has a first end and a second end, and first end is coupled to the second end of the 5th resistance, and second end is coupled to The base stage of first PNP bipolar junction transistor, the collector of the first PNP bipolar junction transistor, the 2nd PNP bipolar junction transistor base Pole, the collector of the 2nd PNP bipolar junction transistor, the second end of second resistance, the second end of the 4th resistance and third power supply are defeated Enter end；
Second operational amplifier, have in-phase end, reverse side and output end, in-phase end be coupled to 3rd resistor second end and The first end of 4th resistance, reverse side are coupled to the drain electrode of third PMOS tube and the first end of second resistance；
Third operational amplifier, have in-phase end, reverse side and output end, in-phase end be coupled to third PMOS tube drain electrode, The first end of second resistance and the reverse side of second operational amplifier, reverse side are coupled to the second end and of the 5th resistance The first end of six resistance；
First phase inverter, has input terminal and output end, and input terminal is coupled to the output end of second operational amplifier；
Second phase inverter, has input terminal and output end, and input terminal is coupled to the output end of third operational amplifier；
First basic RS filpflop, has S input terminal, R input and Q output, and R input is coupled to the first phase inverter Output end, the end S are coupled to the output end of the second phase inverter, and Q output is coupled to enabled output end.
3. a kind of offbeat form voltage-reference with overheat protector according to claim 1, which is characterized in that described Power supply adjudicates supply circuit, comprising:
7th resistance, has a first end and a second end, and first end is coupled to second source input terminal；
6th PMOS tube has grid, source electrode and drain electrode, and source electrode is coupled to the second end of the 7th resistance, and grid, which is coupled to, to be made Energy receiving end, drain electrode are coupled to power supply output end.
4. a kind of offbeat form voltage-reference with overheat protector according to claim 1, which is characterized in that described Offbeat form Low Drift Temperature benchmark source generating circuit, comprising:
8th resistance, has a first end and a second end, and first end is coupled to power supply receiving end；
9th resistance, has a first end and a second end, and first end is coupled to the second end of the 8th resistance；
First NPN bipolar transistor, has collector, emitter and base stage, and collector is coupled to the second of the 9th resistance End, base stage are coupled to the second end of the 9th resistance and the collector of the first NPN bipolar transistor；
Second NPN bipolar transistor, has collector, emitter and base stage, and collector is coupled to power supply receiving end and the The first end of eight resistance, base stage are coupled to the emitter of the first NPN bipolar transistor；
First zener diode, has a first end and a second end, and first end is coupled to the transmitting of the first NPN bipolar transistor The base stage of pole and the second NPN bipolar transistor, second end are coupled to third power input；
Tenth resistance, has a first end and a second end, first end be coupled to the 8th resistance second end and the 9th resistance One end；
Eleventh resistor has a first end and a second end, and first end is coupled to the second end of the tenth resistance；
3rd PNP bipolar junction transistor, has collector, emitter and base stage, and emitter is coupled to the of eleventh resistor Two ends, base stage are coupled to the emitter of the second NPN bipolar transistor, and collector is coupled to third power input and The second end of one zener diode；
Twelfth resistor has a first end and a second end, first end be coupled to power supply receiving end, the 8th resistance first end and The collector of second NPN bipolar transistor；
Thirteenth resistor has a first end and a second end, first end be coupled to power supply receiving end, the 8th resistance first end, The collector of second NPN bipolar transistor and the first end of twelfth resistor；
4th PNP bipolar junction transistor, has collector, emitter and base stage, and emitter is coupled to the of twelfth resistor Two ends；
5th PNP bipolar junction transistor, has collector, emitter and base stage, and emitter is coupled to the of thirteenth resistor Two ends, base stage are coupled to the base stage of the 4th PNP bipolar junction transistor, and collector is coupled to the 4th PNP bipolar junction transistor Base stage and the 5th PNP bipolar junction transistor base stage；
6th PNP bipolar junction transistor, has collector, emitter and base stage, and emitter is coupled to the 4th ambipolar crystalline substance of PNP The collector of body pipe, collector are coupled to the base stage of the 6th PNP bipolar junction transistor；
7th PNP bipolar junction transistor, has collector, emitter and base stage, and emitter is coupled to the 4th ambipolar crystalline substance of PNP The collector of the base stage of body pipe, the base stage of the 5th PNP bipolar junction transistor and the 5th PNP bipolar junction transistor, base stage coupling To the base stage of the 6th PNP bipolar junction transistor and the collector of the 6th PNP bipolar junction transistor；
8th NPN bipolar transistor, has collector, emitter and base stage, and collector is coupled to the 6th ambipolar crystalline substance of PNP The base stage of the base stage of body pipe, the collector of the 6th PNP bipolar junction transistor and the 7th PNP bipolar junction transistor, base stage coupling To the second end of the tenth resistance and the first end of eleventh resistor；
9th NPN bipolar transistor, has collector, emitter and base stage, and collector is coupled to the 8th ambipolar crystalline substance of NPN The emitter of body pipe, base stage are coupled to the emitter of the second NPN bipolar transistor and the base of the 3rd PNP bipolar junction transistor Pole；
Tenth NPN bipolar transistor, has collector, emitter and base stage, and collector is coupled to the 7th ambipolar crystalline substance of PNP The collector of body pipe, base stage are coupled to the base of the emitter of the second NPN bipolar transistor, the 3rd PNP bipolar junction transistor The base stage of pole and the 9th NPN bipolar transistor；
14th resistance, has a first end and a second end, first end be coupled to the second NPN bipolar transistor emitter, Base stage, the base stage of the 9th NPN bipolar transistor and the base of the tenth NPN bipolar transistor of 3rd PNP bipolar junction transistor Pole, second end are coupled to the emitter of the 9th NPN bipolar transistor；
15th resistance, has a first end and a second end, first end be coupled to the 9th NPN bipolar transistor emitter and The second end of 14th resistance, second end are coupled to the second end and third of third power input, the first zener diode The collector of PNP bipolar junction transistor；
11st NPN bipolar transistor has collector, emitter and base stage, and it is ambipolar that collector is coupled to the tenth NPN The emitter of transistor, it is bis- that emitter is coupled to third power input, the second end of the first zener diode, the 3rd PNP The second end of the collector of bipolar transistor and the 15th resistance；
16th resistance, has a first end and a second end, first end be coupled to the 9th NPN bipolar transistor emitter, The second end of 14th resistance and the first end of the 15th resistance, second end are coupled to benchmark source output terminal；
12nd NPN bipolar transistor, has collector, emitter and base stage, and collector is coupled to power supply receiving end, the The first end of eight resistance, the collector of the second NPN bipolar transistor, the first end of twelfth resistor and thirteenth resistor One end, base stage are coupled to the emitter of the second NPN bipolar transistor, the base stage of the 3rd PNP bipolar junction transistor, the 9th The first end of the base stage of NPN bipolar transistor, the base stage of the tenth NPN bipolar transistor and the 14th resistance；
Second zener diode, has a first end and a second end, and first end couples the transmitting of the 12nd NPN bipolar transistor Pole；
17th resistance, has a first end and a second end, and first end is coupled to the second end of the second zener diode, and second End is coupled to the base stage of the 11st NPN bipolar transistor；
18th resistance, has a first end and a second end, first end be coupled to the 11st NPN bipolar transistor base stage and The second end of 17th resistance, second end are coupled to third power input, the second end of the first zener diode, third The emitter of the collector of PNP bipolar junction transistor, the second end of the 15th resistance and the 11st NPN bipolar transistor；
First capacitor has a first end and a second end, and first end is coupled to the second of benchmark source output terminal and the 16th resistance End, second end are coupled to third power input, the second end of the first zener diode, the 3rd PNP bipolar junction transistor Collector, the second end of the 15th resistance, the emitter of the 11st NPN bipolar transistor and the second end of the 18th resistance.
5. a kind of offbeat form voltage-reference with overheat protector according to claim 2, which is characterized in that described The first operational amplifier, second operational amplifier and third operational amplifier, which is characterized in that using PMOS as input pair The two-level operating amplifier of pipe.
6. a kind of offbeat form voltage-reference with overheat protector according to claim 2, which is characterized in that described 3rd resistor resistance value R3, the 4th resistance R4, the resistance value R5 of the 5th resistance and the resistance value R6 of the 6th resistance, substantially, Meet R3+R4=R5+R6, i.e. resistance value and sixth of the sum of the resistance value of the resistance value of 3rd resistor and the 4th resistance equal to the 5th resistance The sum of resistance value of resistance.
7. a kind of offbeat form voltage-reference with overheat protector according to claim 2, which is characterized in that described High-accuracy hysteresis overheat protector detection circuit pass through second operational amplifier, third operational amplifier, the first phase inverter, second The operation of phase inverter and the first rest-set flip-flop, generation is the signal with lagging characteristics.
8. a kind of offbeat form voltage-reference with overheat protector according to claim 4, which is characterized in that described Eleventh resistor, the 3rd PNP bipolar junction transistor, the 8th NPN bipolar transistor and the 9th NPN bipolar transistor constitute One feedback loop, for maintaining the stabilization of benchmark source generating circuit.
9. a kind of offbeat form voltage-reference with overheat protector according to claim 4, which is characterized in that described The 4th PNP bipolar junction transistor, the 5th PNP bipolar junction transistor, the 6th PNP bipolar junction transistor, the 7th ambipolar crystalline substance of PNP The breadth length ratio of body pipe is equal.
10. a kind of offbeat form voltage-reference with overheat protector according to claim 4, which is characterized in that institute The 11st NPN bipolar transistor stated generates negative temperature coefficient, the 9th NPN bipolar transistor and the 11st NPN Bipolar junction transistor collective effect generates positive temperature coefficient.
CN201811462883.2A 2018-12-03 2018-12-03 A kind of offbeat form voltage-reference with overheat protector Withdrawn CN109343642A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210124386A1 (en) * 2019-10-24 2021-04-29 Nxp Usa, Inc. Voltage reference generation with compensation for temperature variation
CN114578890A (en) * 2022-03-10 2022-06-03 中国电子科技集团公司第五十八研究所 Reference voltage source circuit with piecewise linear compensation

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210124386A1 (en) * 2019-10-24 2021-04-29 Nxp Usa, Inc. Voltage reference generation with compensation for temperature variation
US11774999B2 (en) * 2019-10-24 2023-10-03 Nxp Usa, Inc. Voltage reference generation with compensation for temperature variation
CN114578890A (en) * 2022-03-10 2022-06-03 中国电子科技集团公司第五十八研究所 Reference voltage source circuit with piecewise linear compensation
CN114578890B (en) * 2022-03-10 2023-06-20 中国电子科技集团公司第五十八研究所 Reference voltage source circuit with piecewise linear compensation

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