CN109327222A - The time-interleaved system adaptively eliminated based on time error - Google Patents
The time-interleaved system adaptively eliminated based on time error Download PDFInfo
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- CN109327222A CN109327222A CN201811107063.1A CN201811107063A CN109327222A CN 109327222 A CN109327222 A CN 109327222A CN 201811107063 A CN201811107063 A CN 201811107063A CN 109327222 A CN109327222 A CN 109327222A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0624—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by synchronisation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
- H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
- H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing
Abstract
The invention discloses a kind of time-interleaved systems adaptively eliminated based on time error, the M sampled signal sampled for M ADC module, digital time delayer is respectively adopted to be delayed, using the delay sampled signal of the sampled signal of the 1st ADC module and delay sampled signal and other each ADC module as reference signal, reference signal is sent into corresponding time error estimation module to the time error estimation for carrying out corresponding sampled signal according to the reference signal dispensing scheme predefined, simultaneously phase correction values are calculated in phase control module receiving time error estimation result, correct the sampling clock phase of corresponding A DC module, data die section carries out data recombination to M sampled signal, obtain final sampled signal.The present invention dynamically eliminates time error using time error adaptively correcting, facilitates the accurate reproduction of signal for the time mismatch error between multi-channel sampling signal.
Description
Technical field
The invention belongs to time-interleaved technical fields, more specifically, are related to a kind of adaptive based on time error
The time-interleaved system that should be eliminated.
Background technique
As the high speed of the associated electricals message areas such as modern communications, intelligent automobile, aerospace detection, artificial intelligence is sent out
The application of exhibition, ultra-high frequency signal increases rapidly, in order to accurately identify and measure these high speed signals, to data collection system
Sample rate more stringent requirements are proposed.Since (Analog-to-digital converter, modulus turn existing monolithic ADC
Parallel operation) scheme limited by material, technique etc. are many-sided, it is difficult to meet the needs of high speed acquisition.Therefore parallel acquisition technique is made
Real-time acquisition technique for a kind of pair of arbitrary signal has obtained extensive research, and time-interleaved technology among these is exactly one
Kind effectively improves the means of sampling rate.
Time-interleaved (Time-interleaved analog-to-digital conversion, TIADC) system
It is made of M channel, M piece ADC alternating sampling in a parallel fashion, under the driving of multiphase sampling clock, every ADC is to signal x
(t) it samples, and by the sampled data x in each channeli[n] is sent to data die section and carries out data recombination, i=0,1 ..., M-
1, obtain the reconstruct y [n] of original signal.The sample rate of signal breaches the sample rate of monolithic ADC after reconstructing, and realizes M times
Promotion.Either from wireless communication system to time domain measurement instrument, or from high-speed ADC chip to high performance receiver, when
Between alternating sampling technology suffer from extremely wide application value.
However, time-interleaved parallel scheme although realize sample rate promotion, but due to ADC device parameters, set
The non-uniform characteristic such as the placement-and-routing during meter can generate channel mismatching error between each channel, and most direct performance is weight
There are gain error, biased error and time errors for digital signal after structure.To ensure the accurate recreation to original signal, channel
Mismatch error needs are eliminated.In existing mismatch error bearing calibration, gain error and biased error are relatively easy to,
But time error is a stubborn problem, this is a main bottleneck of time-interleaved technology.
Summary of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide it is a kind of based on time error adaptively eliminate when
Between alternating sampling system, for the time mismatch error between multi-channel sampling signal, using time error adaptively correcting come
Dynamic eliminates time error, facilitates the accurate reproduction of signal.
For achieving the above object, the present invention is based on the time-interleaved systems that time error is adaptively eliminated includes
M ADC module and 1 data die section, M digital time delayer, reference signal dispensing module, correction course control module,
M-1 time error estimation module and M-1 phase control module, wherein 1 digital time delayer is configured for the 1st ADC module,
2nd configures 1 digital time delayer, 1 time error estimation module and 1 phase control module to m-th ADC module；
M ADC module is used to carry out input signal x (t) time-interleaved, and t indicates the signal moment, obtains M and leads to
The sampled signal x in roadi[n], i indicate sampled signal serial number, i=0,1 ..., M-1, M=2D, D is positive integer, when n indicates sampling
It carves；The sampled signal x in M channeli[n] is sent to data die section, and is sent respectively to corresponding digital time delayer, and the 1st
The sampled signal x of a ADC module0[n] will also be sent to reference signal dispensing module as reference signal；
M digital time delayer is used for respectively to the sampled signal x receivediThe delay that [n] carries out 1 clock cycle obtains
Be delayed sampled signal xi[n-1], the delay sampled signal of sampled signal serial number even number is as reference signal input reference signal
Module is sent, the 2nd to m-th digital time delayer be delayed sampled signal, that is, be delayed sampled signal x1[n-1] is to xM-1[n-1]
It is sent respectively to corresponding time error estimation module；
Then reference signal dispensing module will correct batch information for determining reference signal dispensing scheme and correction batch
It is sent to correction course control module, scheme is sent according to reference signal, M+1 reference signal is distributed to each time error
Estimation module；Reference signal sends scheme and correction batch is determined using following methods:
1) initialization of reference signal set B={ x0[n-1],x0[n] }, correct batch serial number λ=1；
2) remember that the reference signal quantity in current reference signal set B is Q, reference signal x is set0[n] corresponding sampling
Signal serial number M is arranged reference signal each in sets of reference signals B with corresponding sampled signal serial number from small to large
Sequence, the corresponding sampled signal serial number I of q-th of reference signal of noteq, q=0,1 ..., Q-1；
3) serial number for the Q-1 sampled signal that λ batches carry out time error adaptively correcting is calculated according to the following formula
Wherein, j=0,1 ..., Q-2；
Sampled signalCorresponding two reference signals are respectivelyWithWork as Ij+1=M
When,
The set of the Q-1 sampled signal serial number of this batch is denoted as Fλ；
4) the Q-1 sampled signal determined in step 3) is added in sets of reference signals B；
5) judge whether the reference signal quantity in current reference signal set B is equal to M+1, if so, enter step 7),
Otherwise it enters step 6)；
6) correction batch serial number λ=λ+1, return step 2 are enabled)；
7) reference signal dispensing scheme is obtained in the reference signal of timing according to each sampled signal, according to each batch
Corrected sampled signal serial number set FλGenerate correction batch information；
Correction course control module receives the correction batch information that reference signal dispensing module is sent, according to correction batch letter
It ceases the corresponding time error estimation module of the sampled signal for successively including into each batch and sends correction enabled instruction, and monitor
The correction of time error estimation module feedback finishes signal, when the school for receiving the corresponding all time error estimation modules of this batch
Signal is just finished, then sends correction enabled instruction to next batch, until all correction finishes all batches；
M-1 time error estimation module is after receiving correction enabled instruction, when carrying out to its corresponding sampled signal
Between estimation error, time error estimated result is sent to corresponding phase control module, the specific method of time error estimation
It is as follows:
1) remember sampled signal xi′[n-1] corresponding two-way reference signal is respectively xi′,ref1[n-1] and xi′,ref2[n-1],
Wherein n=1,2 ..., N, N indicate signal length, i '=1,2 ..., M-1；
2) the number of iterations k=1, time error estimated result r are initializedi′(0)=0；
3) error sequence e is calculated separately out according to the following formulai′,1[n-1] and ei′,2[n-1]:
ei′,1[n-1]=xi′[n-1]-xi′,ref1[n-1]
ei′,2[n-1]=xi′[n-1]-xi′,ref2[n-1]
4) cost function of current iteration is calculated according to the following formula
5) time error estimation is carried out using following formula:
Wherein, ri′(k)、ri′(k-1) the time error estimated result of kth time, kth -1 time is respectively indicated, μ indicates default
Adjusting stepping, the value range of μ is (0,1)；The time error estimated result r that will be obtainedi′(k) it is sent to phase controlling mould
Block；
6) judge whether to reach iteration termination condition, if it is, correction terminates, enter step 8), otherwise enter step
7)；
7) k=k+1, return step 3 are enabled)；
8) time error estimation module sends correction to correction course control module and finishes signal；
Phase control module is from corresponding time error estimation module receiving time error estimation result ri′(k), according to
Phase correction values R is calculated in lower formulai′(k):
Ri′(k)=Ri′(0)-[ri′(k)/S]
Wherein, Ri′(0) indicate that the sampling clock phase initial value of corresponding A DC module, S indicate that preset adjusting stepping is prolonged
When, [] indicates to be rounded；
Phase control module is according to phase correction values Ri′(k) it generates phase control signal and is sent to corresponding ADC module, it is right
The sampling clock phase of ADC module is modified；
Data die section is used for the sampled signal x to M channeli[n] carries out data recombination, obtains final sampling letter
Number, it is denoted as X [n].
The present invention is based on the time-interleaved systems that time error is adaptively eliminated, and M ADC module is sampled to obtain
M sampled signal, digital time delayer is respectively adopted and is delayed, by the sampled signal of the 1st ADC module and delay sampling letter
Number and other each ADC module delay sampled signal as reference signal, sent according to the reference signal predefined
Reference signal is sent into corresponding time error estimation module the time error estimation for carrying out corresponding sampled signal, phase control by scheme
Simultaneously phase correction values are calculated in molding block receiving time error estimation result, correct the sampling clock phase of corresponding A DC module,
Data die section carries out data recombination to M sampled signal, obtains final sampled signal.The present invention believes for multi-channel sampling
Time mismatch error between number, dynamically eliminates time error using time error adaptively correcting, facilitates the standard of signal
Really reduction.
Detailed description of the invention
Fig. 1 is the sample waveform exemplary diagram of binary channels TIADC；
Fig. 2 is the specific embodiment structure for the time-interleaved system adaptively eliminated the present invention is based on time error
Figure；
Fig. 3 is the flow chart that reference signal dispensing scheme is determined in the present invention；
Fig. 4 is the flow chart that time error is estimated in the present invention；
Fig. 5 is the structure chart of time-interleaved system in the present embodiment；
Fig. 6 is that reference signal sends scheme schematic diagram in the present embodiment.
Specific embodiment
A specific embodiment of the invention is described with reference to the accompanying drawing, preferably so as to those skilled in the art
Understand the present invention.Requiring particular attention is that in the following description, when known function and the detailed description of design perhaps
When can desalinate main contents of the invention, these descriptions will be ignored herein.
Technical solution in order to better illustrate the present invention, first to of the invention by taking binary channels time-interleaved as an example
Technical principle is briefly described.
Fig. 1 is the sample waveform exemplary diagram of binary channels TIADC.As shown in Figure 1, x (t) is continuous analog signal, two panels
Sample rate is fsADC the signal is sampled according to time-interleaved mode, the sampling interval T of single continuous sampling point of ADCs
=1/fs.Using the sampled result of first ADC as reference signal, enabling the initial phase of the ADC is Φ0Generate signal x0[n], the
The initial phase of two ADC is Φ1Generate sampled signal x1[n].To mark reference signal x convenient for understanding algorithmref1[n]=
x0[n] and xref2[n]=x0[n+1].Ideally x1Sampling instant be reference signal xref1And xref2Sampling instant in
Point, the time interval of two panels ADC is Δ t=T in figures/ 2, i.e. phase difference Φ1-Φ0=180 °.
Define two new sequence e1[n]=x1[n]-xref1[n] and e2[n]=x1[n]-xref2[n], new sequence are x1
With the difference of two reference signals.In the ideal case i.e. there is no when time error, following equilibrium relationships are set up
E(|e1|)=E (| e2|)
Wherein, E () indicates averaged.
And when sampled point be the non-ideal moment when, have E (| e1|)≠E(|e2|)。
The present invention is based on discussed above, a kind of time-interleaved system adaptively eliminated based on time error is proposed
System.Fig. 2 is the specific embodiment structure chart for the time-interleaved system adaptively eliminated the present invention is based on time error.Such as
Shown in Fig. 2, the present invention is based on the time-interleaved systems that time error is adaptively eliminated, in addition to including the M in conventional system
A ADC module 1 and 1 data die section 7 further includes M digital time delayer 2, reference signal dispensing module 3, correction course
Control module 4, M-1 time error estimation module 5 and M-1 phase control module, wherein configuring 1 for the 1st ADC module
Digital time delayer, the 2nd to m-th ADC module configures 1 digital time delayer, 1 time error estimation module and 1 phase control
Molding block, is separately below described in detail modules.
M ADC module 1 is used to carry out input signal x (t) time-interleaved, and t indicates the signal moment, obtains M and leads to
The sampled signal x in roadi[n], i indicate sampled signal serial number, i=0,1 ..., M-1, and n indicates sampling instant.The sampling in M channel
Signal xi[n] is sent to data die section 7, and is sent respectively to corresponding digital time delayer 2, the sampling of the 1st ADC module
Signal x0[n] will also be sent to reference signal dispensing module as reference signal.
M digital time delayer 2 is used for respectively to the sampled signal x receivedi[n] carries out 1 delay and obtains delay sampling
Signal xiThe delay sampled signal of [n-1], sampled signal serial number even number send module as reference signal input reference signal
3, the 2nd is delayed sampled signal to m-th digital time delayer, i.e. delay sampled signal x1[n-1] is to xM-1[n-1] is sent out respectively
Give corresponding time error estimation module 5.
Reference signal dispensing module 3, then will correction batch letter for determining reference signal dispensing scheme and correction batch
Breath is sent to correction course control module 4, sends scheme according to reference signal and M+1 reference signal is distributed to each time mistake
Poor estimation module 5.Fig. 3 is the flow chart for determining reference signal dispensing scheme in the present invention and correcting batch.As shown in figure 3, this
Determine that reference signal dispensing scheme includes: with the specific steps for correcting batch in invention
S301: initialization of reference signal set and correction batch:
The present invention is selected with sampled signal x0[n] carries out time error elimination, and technology according to the present invention as benchmark
Principle needs two reference signals it is found that when a sampled signal carries out time error elimination, is based on this, initialized reference letter
Number set B={ x0[n-1],x0[n] }, correct batch serial number λ=1.
S302: sets of reference signals parameter is obtained:
Remember that the reference signal quantity in current reference signal set B is Q, reference signal x is set0[n] corresponding sampling letter
Number serial number M, reference signal each in sets of reference signals B is sorted from small to large with corresponding sampled signal serial number,
Remember the corresponding sampled signal serial number I of q-th of reference signalq, q=0,1 ..., Q-1.Obvious the Q-1 reference signal is x0
[n]。
S303: reference signal is determined:
The serial number for the Q-1 sampled signal that λ batches carry out time error adaptively correcting is calculated according to the following formula
Wherein, j=0,1 ..., Q-2；
Sampled signalCorresponding two reference signals are respectivelyWithWork as Ij+1=M
When,
The set of the Q-1 sampled signal serial number of this batch is denoted as Fλ, i.e.,FλAs
The λ batches of sampled signal set for carrying out time error adaptively correcting.
S304: sets of reference signals is updated:
When Q-1 sampled signal of this batch is after time error adaptively correcting, reference signal use can be used as, because
Q-1 sampled signal determined in step S303 is added in sets of reference signals B for this.
S305: judging whether the reference signal quantity in current reference signal set B is equal to M+1, if so, entering step
Otherwise S307 enters step S306.
S306: correction batch serial number λ=λ+1, return step S302 are enabled.
S307: reference signal dispensing scheme and correction batch are obtained:
According to each sampled signal the reference signal of timing obtain reference signal dispensing scheme, according to each batch into
The sampled signal serial number set F of row correctionλGenerate correction batch information.
According to the above process it is found that the present invention is carrying out time error adaptively correcting constantly to each sampled signal, ginseng
Sampled signal or delay sampled signal of the signal only with sampled signal serial number even number are examined, and sampled signal sequence is not used
Number for odd number sampled signal or delay sampled signal, in this namely M obtained delay sampled signal of digital time delayer 2
The reason of delay sampled signal of sampled signal serial number even number can be only sent to reference signal dispensing module 3.
Correction course control module 4 receives the correction batch information that reference signal dispensing module 3 is sent, according to correction batch
The corresponding time error estimation module 5 of the sampled signal that information successively includes into each batch sends correction enabled instruction, and
The correction that monitoring time estimation error module 5 is fed back finishes signal, estimates moulds when receiving the corresponding all time errors of this batch
The correction of block 5 finishes signal, then sends correction enabled instruction to next batch, until all correction finishes all batches.
M-1 time error estimation module 5 is after receiving correction enabled instruction, when carrying out to its corresponding sampled signal
Between estimation error, time error estimated result is sent to corresponding phase control module 6.Fig. 4 is time error in the present invention
The flow chart of estimation.As shown in figure 4, the specific steps that time error is estimated in the present invention include:
S401: signal configuration:
Remember sampled signal xi′[n-1] corresponding two-way reference signal is respectively xi′,ref1[n-1] and xi′,ref2[n-1],
Middle n=1,2 ..., N, N indicate signal length, i '=1,2 ..., M-1.In general, sampled signal and reference signal all use
The sequence that is constituted of newest N number of sampled value that sampling instant requirement is met to induction signal.
S402: initialization the number of iterations k=1, time error estimated result ri′(0)=0；
S403: error sequence is calculated:
Error sequence e is calculated separately out according to the following formulai′,1[n-1] and ei′,2[n-1]:
ei′,1[n-1]=xi′[n-1]-xi′,ref1[n-1]
ei′,2[n-1]=xi′[n-1]-xi′,ref2[n-1]
S404: cost function is calculated:
The cost function of current iteration is calculated according to the following formula
S405: time error estimation:
Time error estimation is carried out using following formula:
Wherein, ri′(k)、ri′(k-1) the time error estimated result of kth time, kth -1 time is respectively indicated, μ indicates default
Adjusting stepping, the value range of μ is (0,1), the fast convergence rate when μ is larger, but can lose certain precision, when μ is smaller
Estimated accuracy is high but convergence rate is slow, is can according to need in practical applications the specific value of high section stepping μ is arranged.
The time error estimated result r that time error estimation module 5 will obtaini′(k) it is sent to phase control module 6.
S406: judging whether to reach iteration termination condition, if it is, correction terminates, enters step S408, otherwise enters
Step S407.
Whether iteration termination condition is generally divided into two kinds, one is judging whether time error estimated result restrains, i.e., full
Footε indicates preset threshold, if convergence, correction terminates；One is whether judge the number of iterations
Reach preset maximum number of iterations, if reached, correction terminates.
S407: k=k+1, return step S403 are enabled；
S408: correction finishes:
Time error estimation module 5 sends correction to correction course control module 4 and finishes signal.
Phase control module 6 is from corresponding 5 receiving time error estimation result r of time error estimation modulei′(k), according to
Phase correction values R is calculated in following formulai′(k):
Ri′(k)=Ri′(0)-[ri′(k)/S]
Wherein, Ri′(0) indicate that the sampling clock phase initial value of corresponding A DC module, S indicate that preset adjusting stepping is prolonged
When, [] indicates to be rounded.
Phase control module 6 is according to phase correction values Ri′(k) it generates phase control signal and is sent to corresponding ADC module,
The sampling clock phase of ADC module is modified.The modified detailed process of sampling clock phase needs the tool according to ADC module
Body configures to determine, when ADC module is configured with internal phase regulator, directly its phase register is arranged, if
There is no phase regulator, then needs to carry out phase adjusted by adjusting the clock source of ADC module sampling clock.
From the above description, it can be seen that time error adaptively correcting is by time error estimation module 5 and phase in the present invention
The cooperation of control module 6 is realized: time error estimation module 5 persistently carries out time error according to sampled signal and two reference signals
Estimation then carries out a sampling clock phase amendment by phase control module 6 after each time error estimation, ties until meeting
Beam condition.It is adaptive that every group of time error estimation module 5 and phase control module 6 according to correction batch successively carry out time error
After correction, the time error that entire time-interleaved system can be realized adaptively is eliminated.
Data die section is used for the sampled signal x to M channeli[n] carries out data recombination, obtains final sampling letter
Number, i.e. X [n].Data die section is the conventional configuration of time-interleaved system, is not emphasis of the invention, specific
Details are not described herein for data recombination process.
Adaptively disappear in practical application, time-interleaved system generally can carry out a time error when powering on
Remove, in the process of running, can according to need periodically or single start time error and adaptively eliminate, in corresponding module
In be configured.
Embodiment
Technical solution in order to better illustrate the present invention, using a specific example, the present invention is described in detail.
Fig. 5 is the structure chart of time-interleaved system in the present embodiment.As shown in figure 5, time-interleaved in the present embodiment
Sampling system is configured with 4 ADC module, that is, there is the sampled signal x in 4 channels0[n]、x1[n]、x2[n]、x3[n], at one
The clock phase of 4 sampled signals is respectively 0 °, 90 °, 180 °, 270 ° in sampling period.4 ADC module are adopted in the present embodiment
With same sampling clock source, configuration phase adjuster is used for phase adjusted inside ADC module.
As it can be seen that in the present embodiment, there are 5 reference signal x0[n-1], x0[n], x1[n-1], x2[n-1], x3[n-
1].Determine that reference signal sends scheme firstly the need of by reference signal dispensing module 3, detailed process is as follows:
Initialization of reference signal set B={ x0[n-1],x0[n] }, it is seen that the reference signal in sets of reference signals B at this time
Quantity is that the corresponding sampled signal serial number of 2,2 reference signals is respectively I1=0, I2=4.So the 1st batch carries out time error
Adaptively correcting sampled signal only has 1, sampled signal serial number f1=(0+4)/2=2, that is, the sampled signal for needing to correct are
x2[n-1], reference signal x0[n-1] and x0[n]。
Then by x2Sets of reference signals B is added in [n-1], after being ranked up to reference signal according to sampled signal serial number,
Know B={ x at this time0[n-1],x2[n-1],x0[n] }, reference signal quantity is the corresponding sampled signal sequence of 3,3 reference signals
Number be respectively I1=0, I2=2, I3=4.Therefore the 2nd batch, which carries out time error adaptively correcting sampled signal, 2, adopts
Sample signal serial number is respectively f1=(0+2)/2=1, f2=(2+4)/2=3, that is, the sampled signal for needing to correct are x1[n-1]、x3
[n-1], sampled signal x1The reference signal of [n-1] is x0[n-1] and x2[n-1], sampled signal x3The reference signal of [n-1] is x2
[n-1] and x0[n]。
Fig. 6 is that reference signal sends scheme schematic diagram in the present embodiment.As shown in fig. 6, x0[n-1] believes as initial reference
Number, it does not need to be corrected.1st batch carries out sampled signal x2The time error adaptively correcting of [n-1], sampled signal x2[n-
1] reference signal is x0[n-1] and x0[n], the 2nd batch carry out sampled signal x1[n-1]、x3The time error of [n-1] is adaptive
It should correct, sampled signal x1The reference signal of [n-1] is x0[n-1] and x2[n-1], sampled signal x3The reference signal of [n] is x2
[n-1] and x0[n].Reference signal sends module 3 and is sent to reference signal accordingly according to above with reference to signal dispensing scheme
Time error estimation module 5, it is less by ADC module in this present embodiment, therefore end is directlyed adopt in reference signal dispensing module 3
Physical connection between mouthful carries out the dispensing of reference signal.When ADC module is more, reference signal point can be realized using chip
It send.Reference signal dispensing module 3 also needs to correct batch information and is sent to correction course control module 4.
Correction batch is controlled by correction course control module 4, and correction course control module 4 is adopted to the 1st batch first
Sample signal x2[n-1] corresponding time error estimation module 5 sends correction enabled instruction, i.e. the 2nd time error estimation module
5, sampled signal x is carried out by the time error estimation module 5 and corresponding phase control module 62The time error of [n-1] is adaptive
It should correct.Time error estimation module 5 sends correction to correction course control module 4 and finishes signal after correction, corrects
Process control module 4 is again to the sampled signal x of the 2nd batch1[n-1]、x3[n-1] corresponding time error estimation module 5 sends correction
Enabled instruction carries out sampled signal x1[n-1]、x3The correction of [n-1].Each time error estimation module 5 completes correction in batches after,
The time error of entire time-interleaved system is eliminated, thus the accuracy for the signal for obtaining data die section 7
It is higher.
Although the illustrative specific embodiment of the present invention is described above, in order to the technology of the art
Personnel understand the present invention, it should be apparent that the present invention is not limited to the range of specific embodiment, to the common skill of the art
For art personnel, if various change the attached claims limit and determine the spirit and scope of the present invention in, these
Variation is it will be apparent that all utilize the innovation and creation of present inventive concept in the column of protection.
Claims (1)
1. a kind of time-interleaved system adaptively eliminated based on time error, M ADC module and 1 data composite die
Block, which is characterized in that further include M digital time delayer, reference signal dispensing module, correction course control module, M-1 time
Estimation error module and M-1 phase control module, wherein for the 1st ADC module 1 digital time delayer of configuration, the 2nd to M
A ADC module configures 1 digital time delayer, 1 time error estimation module and 1 phase control module；
M ADC module is used to carry out input signal x (t) time-interleaved, and t indicates the signal moment, obtains M channel
Sampled signal xi[n], i indicate sampled signal serial number, i=0,1 ..., M-1, M=2D, D is positive integer, and n indicates sampling instant；M
The sampled signal x in a channeli[n] is sent to data die section, and is sent respectively to corresponding digital time delayer, the 1st ADC
The sampled signal x of module0[n] will also be sent to reference signal dispensing module as reference signal；
M digital time delayer is used for respectively to the sampled signal x receivedi[n] carries out 1 delay and obtains delay sampled signal xi
[n-1], the delay sampled signal of sampled signal serial number even number send module as reference signal input reference signal, the 2nd to
M-th digital time delayer is delayed sampled signal, i.e. delay sampled signal x1[n-1] is to xM-1[n-1] is sent respectively to correspond to
Time error estimation module；
Then reference signal dispensing module sends correction batch information for determining reference signal dispensing scheme and correction batch
Correction course control module is given, scheme is sent according to reference signal, M+1 reference signal is distributed to each time error estimation
Module；Reference signal sends scheme and correction batch is determined using following methods:
1) initialization of reference signal set B={ x0[n-1],x0[n] }, correct batch serial number λ=1；
2) remember that the reference signal quantity in current reference signal set B is Q, reference signal x is set0[n] corresponding sampled signal sequence
Number be M, reference signal each in sets of reference signals B is sorted from small to large with corresponding sampled signal serial number, note q
The corresponding sampled signal serial number I of a reference signalq, q=0,1 ..., Q-1；
3) serial number for the Q-1 sampled signal that λ batches carry out time error adaptively correcting is calculated according to the following formula
Wherein, j=0,1 ..., Q-2；
Sampled signalCorresponding two reference signals are respectivelyWithWork as Ij+1When=M,
The set of the Q-1 sampled signal serial number of this batch is denoted as Fλ；
4) the Q-1 sampled signal determined in step 3) is added in sets of reference signals B；
5) judge whether the reference signal quantity in current reference signal set B is equal to M+1, if so, entering step 7), otherwise
It enters step 6)；
6) correction batch serial number λ=λ+1, return step 1 are enabled)；
7) reference signal dispensing scheme is obtained in the reference signal of timing according to each sampled signal, is carried out according to each batch
The sampled signal serial number set F of correctionλGenerate correction batch information；
Correction course control module receive reference signal dispensing module send correction batch information, according to correction batch successively to
The corresponding time error estimation module of the sampled signal for including in each batch sends correction enabled instruction, and monitoring time error
The correction of estimation module feedback finishes signal, when the correction for receiving the corresponding all time error estimation modules of this batch finishes letter
Number, then correction enabled instruction is sent to next batch, until all correction finishes all batches；
M-1 time error estimation module carries out time mistake after receiving correction enabled instruction, to its corresponding sampled signal
Time error estimated result is sent to corresponding phase control module by difference estimation, and the specific method is as follows for time error estimation:
1) remember sampled signal xi′[n-1] corresponding two-way reference signal is respectively xi′,ref1[n-1] and xi′,ref2[n-1], wherein n
=1,2 ..., N, N indicate signal length, i '=1,2 ..., M-1；
2) the number of iterations k=1, time error estimated result r are initializedi′(0)=0；
3) error sequence e is calculated separately out according to the following formulai′,1[n-1] and ei′,1[n-1]:
ei′,1[n-1]=xi′[n-1]-xi′,ref1[n-1]
ei′,2[n-1]=xi′[n-1]-xi′,ref2[n-1]
4) cost function of current iteration is calculated according to the following formula
5) time error estimation is carried out using following formula:
Wherein, ri′(k)、ri′(k-1) the time error estimated result of kth time, kth -1 time is respectively indicated, μ indicates preset adjusting
Stepping, the value range of μ are (0,1)；The time error estimated result r that will be obtainedi′(k) it is sent to phase control module；
6) judge whether to reach iteration termination condition, if it is, correction terminates, enter step 8), otherwise enter step 7)；
7) k=k+1, return step 3 are enabled)；
8) time error estimation module sends correction to correction course control module and finishes signal；
Phase control module is from corresponding time error estimation module receiving time error estimation result ri′(k), according to following public affairs
Phase correction values R is calculated in formulai′(k):
Ri′(k)=Ri′(0)-[ri′(k)/S]
Wherein, Ri′(0) indicate that the sampling clock phase initial value of corresponding A DC module, S indicate preset adjusting stepping delay, []
It indicates to be rounded；
Phase control module is according to phase correction values Ri′(k) it generates phase control signal and is sent to corresponding ADC module, to ADC
The sampling clock phase of module is modified；
Data die section is used for the sampled signal x to M channeli[n] carries out data recombination, obtains final sampled signal.
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| CN114665876B (en) * | 2022-03-15 | 2022-12-27 | 深圳大学 | Data-driven multiple-collection sampling clock mismatch self-adaptive calibration method |
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