CN109326599A - A kind of forming method and three-dimensional storage part of three-dimensional storage part - Google Patents
A kind of forming method and three-dimensional storage part of three-dimensional storage part Download PDFInfo
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- CN109326599A CN109326599A CN201811169251.7A CN201811169251A CN109326599A CN 109326599 A CN109326599 A CN 109326599A CN 201811169251 A CN201811169251 A CN 201811169251A CN 109326599 A CN109326599 A CN 109326599A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Abstract
The embodiment of the invention discloses a kind of forming method of three-dimensional storage part and three-dimensional storage parts, wherein the described method includes: the lower lamination of etching three-dimensional storage part, to form N number of lower channel hole, wherein N is more than or equal to 2；Deposition forms superimposed layer on the lower lamination；The corresponding lower channel hole etches the superimposed layer, to form M upper channel hole, wherein M is less than N, and M lower channel hole in M upper channel hole and N number of lower channel hole corresponds.
Description
Technical field
The present embodiments relate to semiconductor devices and its manufacturing field, a kind of three-dimensional storage part is related to, but are not limited to
Forming method and three-dimensional storage part.
Background technique
In order to overcome the limitation of two-dimensional storage device, industry has been developed that the memory device with three-dimensional structure, passes through
Memory cell is three-dimensionally disposed in substrate to improve integration density.
Existing bilayer three-dimensional storage part, such as double-deck three-dimensional computer flash memory device (3D NAND) memory device,
Superimposed layer and lower lamination are all made of the mode of vertical stacking multilayered memory unit, realize the 3D nand memory part of stack.Such as
Shown in Fig. 1, it is existing bilayer 3D nand memory part, divides in the lower lamination 10 and superimposed layer 11 of the memory device of stack
It Ju You one-to-one multiple access openings (Channel Hole, CH), wherein each lower channel hole 101 in lower lamination 10
There is a corresponding upper channel hole 111 positioned at superimposed layer 11.
But for the existing double-deck three-dimensional storage part, if lower channel hole bottom is carrying out selective epitaxial growth
Preferable epitaxial structure 13 is not formed when (Selective Epitaxial Growth, SEG), for example, obtaining thinner thickness
Epitaxial structure 13, then, if carrying out the processing in the upper channel hole of superimposed layer corresponding position again, be easy to bring device reliable
Property and electric leakage the problems such as.
Summary of the invention
In view of this, the embodiment of the present invention provides the forming method and three-dimensional storage part of a kind of three-dimensional storage part, energy
Not the problems such as enough solutions do not form preferable epitaxial structure and bring device reliability and electric leakage due to lower channel hole.
The technical solution of the embodiment of the present invention is achieved in that
In a first aspect, the embodiment of the present invention provides a kind of forming method of three-dimensional storage part, which comprises
The lower lamination of three-dimensional storage part is etched, to form N number of lower channel hole, wherein N is more than or equal to 2；
Deposition forms superimposed layer on the lower lamination；
The corresponding lower channel hole etches the superimposed layer, to form M upper channel hole, wherein M is less than N, and the M is a
M lower channel hole in upper channel hole and N number of lower channel hole corresponds.
In other embodiments, the correspondence lower channel hole etches the superimposed layer, to form M upper channel hole,
Include:
M lower channel hole is selected in N number of lower channel hole according to preset condition；
Corresponding M lower channel hole, performs etching the superimposed layer, to form the M on the superimposed layer
Upper channel hole, wherein M lower channel hole is located at any position of the lower lamination.
In other embodiments, the method also includes: the bottom in N number of lower channel hole is raw using selective epitaxial
Long SEG forms N number of epitaxial structure.
In other embodiments, after forming N number of lower channel hole, the method also includes:
Side wall along N number of lower channel hole sequentially forms N number of first oxide-nitride-oxide ONO from the inside to the outside
Structure；
After forming M upper channel hole, the side wall along M upper channel hole forms M the 2nd ONO knots from the inside to the outside
Structure.
In other embodiments, the superimposed layer and the lower lamination are stacked by first material layer and second material layer circulation
It is formed.
Second aspect, the embodiment of the present invention provide a kind of three-dimensional storage part, and the three-dimensional storage part includes:
Lower lamination；
N number of lower channel hole within the lower lamination, wherein N is more than or equal to 2；
The superimposed layer being formed on the lower lamination；
The M upper channel hole within the superimposed layer, wherein M be less than N, M upper channel hole with it is described N number of
M lower channel hole in lower channel hole corresponds.
In other embodiments, M lower channel hole is located at any position of the lower lamination.
In other embodiments, the three-dimensional storage part further include:
N number of epitaxial structure, N number of epitaxial structure is formed by selective epitaxial growth SEG, and N number of extension
Structure is located at the bottom in N number of lower channel hole.
In other embodiments, the three-dimensional storage part further include:
N number of first oxide-nitride-oxide that side wall along N number of lower channel hole sequentially forms from the inside to the outside
ONO structure；And the side wall along M upper channel hole is formed by M the second ONO structures from the inside to the outside.
In other embodiments, the superimposed layer and the lower lamination are stacked by first material layer and second material layer circulation
It is formed.
The forming method and three-dimensional storage part of three-dimensional storage part provided in an embodiment of the present invention, wherein the method
It include: the lower lamination for etching three-dimensional storage part, to form N number of lower channel hole；Deposition, which is formed, on the lower lamination folds
Layer；The corresponding lower channel hole etches the superimposed layer, to form M upper channel hole, wherein M is less than N, the M upper channel
M lower channel hole in hole and N number of lower channel hole corresponds.In this way, due to the upper channel hole that is formed in superimposed layer
Quantity M is less than the quantity N in the lower channel hole that lower lamination is formed, it is possible to a part of lower channel hole without upper channel
The processing in hole, for example, the processing to no lower channel hole for forming preferable epitaxial structure without corresponding upper channel hole；Such as
This, the problems such as being able to solve device reliability and leak electricity.
Detailed description of the invention
In attached drawing (it is not necessarily drawn to scale), similar appended drawing reference can describe phase in different views
As component.Similar reference numerals with different letter suffix can indicate the different examples of similar component.Attached drawing with example and
Unrestricted mode generally shows each embodiment discussed herein.
Fig. 1 is existing bilayer 3D nand memory part；
Fig. 2 is the implementation process schematic diagram of the forming method for the three-dimensional storage part that the embodiment of the present invention one provides；
Fig. 3 A is the process schematic that separation layer is formed on the substrate in one three-dimensional storage part of the embodiment of the present invention；
Fig. 3 B is the process schematic that one three-dimensional storage part of the embodiment of the present invention forms lower lamination；
Fig. 3 C is the process schematic that one three-dimensional storage part of the embodiment of the present invention forms lower channel hole；
Fig. 3 D is the process schematic that one three-dimensional storage part of the embodiment of the present invention forms superimposed layer；
Fig. 3 E is the process schematic that one three-dimensional storage part of the embodiment of the present invention forms upper channel hole；
Fig. 4 is the implementation process schematic diagram of the forming method of three-dimensional storage part provided by Embodiment 2 of the present invention；
Fig. 5 A is the process schematic that separation layer is formed on the substrate in two three-dimensional storage part of the embodiment of the present invention；
Fig. 5 B is the process schematic that two three-dimensional storage part of the embodiment of the present invention forms lower lamination；
Fig. 5 C is the process schematic that two three-dimensional storage part of the embodiment of the present invention forms lower channel hole；
Fig. 5 D is the process schematic that two three-dimensional storage part of the embodiment of the present invention forms the first ONO structure；
Fig. 5 E is the process schematic that two three-dimensional storage part of the embodiment of the present invention forms epitaxial structure；
Fig. 5 F is the process schematic that two three-dimensional storage part of the embodiment of the present invention forms superimposed layer；
Fig. 5 G is the process schematic that two three-dimensional storage part of the embodiment of the present invention forms upper channel hole；
Fig. 5 H is the process schematic that two three-dimensional storage part of the embodiment of the present invention forms the second ONO structure；
Fig. 6 is the structural schematic diagram for the three-dimensional storage part that the embodiment of the present invention three provides；
Fig. 7 is the structural schematic diagram for the three-dimensional storage part that the embodiment of the present invention four provides.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, the specific technical solution of invention is described in further detail.The following examples are intended to illustrate the invention, but does not have to
To limit the scope of the invention.
As shown in the application and claims, unless context clearly prompts exceptional situation, " one ", "one", " one
The words such as kind " and/or "the" not refer in particular to odd number, may also comprise plural number.In general, term " includes " only prompts to wrap with "comprising"
Include clearly identify the step of and element, and these steps and element do not constitute one it is exclusive enumerate, method or device
The step of may also including other or element.
When describing the embodiments of the present invention, for purposes of illustration only, indicating that the sectional view of device architecture can disobey general proportion work
Partial enlargement, and the schematic diagram is example, should not limit the scope of protection of the invention herein.In addition, in practical system
It should include the three-dimensional space of length, width and depth in work.
In the context of this application, structure of the described fisrt feature in the "upper" of second feature may include first
Feature and second feature are formed as the embodiment directly contacted, also may include that other feature is formed in fisrt feature and second
Embodiment between feature, such fisrt feature and second feature may not be direct contact.
Embodiment one
The embodiment of the present invention provides a kind of forming method of three-dimensional storage part, and Fig. 2 is what the embodiment of the present invention one provided
The implementation process schematic diagram of the forming method of three-dimensional storage part, as shown in Fig. 2, the described method comprises the following steps:
Step S201 etches the lower lamination of three-dimensional storage part, to form N number of lower channel hole.
Here, the lower lamination of the three-dimensional storage part is insulating layer and the alternately stacked stack layer of semiconductor layer.This reality
It applies in example, lower channel hole is the through-hole in lower lamination, can use lithographic technique, such as reactive ion etching (Reactive
Ion Etching, RIE) the lower lamination of technology etching, until exposing substrate surface, to form lower channel hole.Alternatively, lower channel
Hole can also be realized using photoetching technique, for example, being exposed after covering photoresist layer, then be performed etching.
In the present embodiment, N is more than or equal to 2, and after etching lower lamination, the lower lamination of the three-dimensional storage part has N number of
Lower channel hole.
It should be noted that step S201 etching three-dimensional storage part lower lamination before, the method also includes with
Lower step:
Step S2011 provides substrate, forms separation layer over the substrate.
As shown in Figure 3A, separation layer 32 is formed on substrate 31.Wherein, the material of substrate 31 can choose silicon Si, SiGe
Alloy SiGe, silicon carbide SiC, aluminium oxide Al 2O3, aluminium nitride AlN, zinc oxide ZnO, gallium oxide Ga2O3 or lithium aluminate LiAlO2
One of Deng.Since Si substrate is cheap, and it is easy to adulterate, while is prone to reaction and generating heterogeneous separation layer, because
Si be can choose in this present embodiment as substrate 31.
The separation layer 32 can be silica material, and the effect of separation layer 32 is to realize substrate 31 and the separation layer 32
The electric isolation of superstructure.
Step S2012, lamination under being formed on the separation layer.
As shown in Figure 3B, the lower lamination 33 can be formed by the way of vertical stacking multilayered memory unit.Under for example,
Lamination 33 can be stacked and be formed by first material layer 331 and the circulation of second material layer 332.Wherein, first material layer 331 and second
The number of plies of material layer 332 can be any amount.Using chemical vapor deposition (Chemical Vapor Deposition, CVD)
Perhaps atomic layer deposition (Atomic Layer Deposition ALD) or other depositional modes, successively in separation layer 32
On be alternately stacked multilayer first material layer 331 and second material layer 332.
In the present embodiment, first material layer 331 is semiconductor layer, and first material layer 331 can be silicon nitride；Second material
Layer 332 is insulating layer, and second material layer 332 can be silica.
Under being formed on the separation layer after lamination, as shown in Figure 3 C, the lower lamination of three-dimensional storage part is etched,
To form N number of lower channel hole 333.
Step S202, deposition forms superimposed layer on the lower lamination.
After the etching for completing lower channel hole, as shown in Figure 3D, deposition forms superimposed layer 34 on the lower lamination,
The superimposed layer 34 is identical as the lower lamination 33, can be formed by the way of vertical stacking multilayered memory unit.On for example,
Lamination 34 can be stacked and be formed by third material layer 343 and the 4th material layer 344 circulation.Wherein, third material layer 343 and the 4th
The number of plies of material layer 344 can be any amount.Using CVD or ALD or other depositional modes, successively in lower lamination 33
On be alternately stacked multilayer third material layer 343 and the 4th material layer 344.
In the present embodiment, third material layer 343 is semiconductor layer, and third material layer 343 can be silicon nitride；4th material
Layer 344 is insulating layer, and the 4th material layer 344 can be silica.
Step S203, the corresponding lower channel hole etches the superimposed layer, to form M upper channel hole.
Here, M is less than N, and M lower channel hole in M upper channel hole and N number of lower channel hole corresponds.
In the present embodiment, after forming superimposed layer on the lower lamination, as shown in FIGURE 3 E, corresponding N number of lower channel
M lower channel hole in hole etches the superimposed layer 34 of three-dimensional storage part, to form M upper channel hole 341.Wherein, on M
Each of access opening 341 upper channel hole is corresponding with a lower channel hole.Here, the correspondence refers to, the upper channel
Hole 341 is located at the surface in the lower channel hole 333, and the upper channel hole 341 is connected to the lower channel hole 333.
The forming method of three-dimensional storage part provided in an embodiment of the present invention, firstly, etching three-dimensional storage part is lower folded
Layer, to form N number of lower channel hole, wherein N is more than or equal to 2；Then, deposition forms superimposed layer on the lower lamination；Most
Afterwards, the corresponding lower channel hole etches the superimposed layer, to form M upper channel hole, wherein M is less than N, the M upper channel
M lower channel hole in hole and N number of lower channel hole corresponds.In this way, corresponding a part of lower channel hole is without upper logical
The etching in road hole, wherein the part lower channel hole can be the lower channel hole for not forming preferable epitaxial structure, in this way, energy
Enough avoid not formed preferable epitaxial structure due to lower channel hole and the problems such as bring device reliability and electric leakage.
Embodiment two
The embodiment of the present invention provides a kind of forming method of three-dimensional storage part, and Fig. 4 is provided by Embodiment 2 of the present invention
The implementation process schematic diagram of the forming method of three-dimensional storage part, as shown in figure 4, the described method comprises the following steps:
Step S401 etches the lower lamination of three-dimensional storage part, to form N number of lower channel hole.
Here, the lower lamination of the three-dimensional storage part is insulating layer and the alternately stacked stack layer of semiconductor layer.This reality
It applies in example, lower channel hole is the through-hole in lower lamination, and lithographic technique, such as RIE technology can be used to etch lower lamination, Zhi Daobao
Expose substrate surface, to form lower channel hole.Alternatively, lower channel hole can also be realized using photoetching technique, for example, in covering light
It is exposed after resistance layer, then performs etching.
In the present embodiment, N is more than or equal to 2, and after etching lower lamination, the lower lamination of the three-dimensional storage part has N number of
Lower channel hole.
It should be noted that step S401 etching three-dimensional storage part lower lamination before, the method also includes with
Lower step:
Step S4011 provides substrate, forms separation layer over the substrate.
As shown in Figure 5A, separation layer 52 is formed on substrate 51.Wherein, the material of substrate 51 can choose Si, SiGe,
One of SiC, Al2O3, AlN, ZnO, Ga2O3, LiAlO2 or LiAlO3 etc..Since Si substrate is cheap, and it is easy to mix
It is miscellaneous, while being prone to reaction and generating heterogeneous separation layer, therefore can choose Si in the present embodiment as substrate 51.
The separation layer 52 can be silica material, and the effect of separation layer 52 is to realize substrate 51 and the separation layer 52
The electric isolation of superstructure.
Step S4012, lamination under being formed on the separation layer.
As shown in Figure 5 B, the lower lamination 53 can be formed by the way of vertical stacking multilayered memory unit.Under for example,
Lamination 53 can be stacked and be formed by first material layer 531 and the circulation of second material layer 532.Wherein, first material layer 531 and second
The number of plies of material layer 532 can be any amount.Using CVD or ALD or other depositional modes, successively in separation layer 52
On be alternately stacked multilayer first material layer 531 and second material layer 532.
In the present embodiment, first material layer 531 is semiconductor layer, and first material layer 531 can be silicon nitride；Second material
Layer 532 is insulating layer, and second material layer 532 can be silica.
Under being formed on the separation layer after lamination, as shown in Figure 5 C, the lower lamination of three-dimensional storage part is etched,
To form N number of lower channel hole 533.
Step S402, the side wall along N number of lower channel hole sequentially form N number of first silicon oxide-silicon nitride-from the inside to the outside
Silica ONO structure.
In the forming process of three-dimensional storage part, when the lower lamination for etching the three-dimensional storage part formed it is N number of lower logical
After road hole 533, also the first ONO structure forming step can be executed for N number of lower channel hole 533.As shown in Figure 5 D, N number of
Barrier insulating layer is sequentially formed from the inside to the outside along the side wall in lower channel hole 533 in each lower channel hole in lower channel hole
5341, electric charge capture layer 5342 and tunneling insulation layer 5343.Barrier insulating layer 5341, electric charge capture layer 5342 and tunneling insulation layer
5343 constitute the accumulation layer of the three-dimensional storage part.Wherein, the material of barrier insulating layer 5341 can be silica, charge prisoner
The material for obtaining layer 5342 can be silicon nitride, and the material of tunneling insulation layer 5343 can be silica, in this way, by silica-nitrogen
The accumulation layer that SiClx-silica is formed is first ONO structure 534.Certainly, each layer in the first ONO structure can also
To select other materials, the present embodiment is not limited this.
Step S403 uses selective epitaxial growth SEG in the bottom in N number of lower channel hole, forms N number of epitaxy junction
Structure.
As shown in fig. 5e, it is respectively formed epitaxial structure 535 in the bottom in each lower channel hole, the material of epitaxial structure 535 can
Think silicon, the mode for forming epitaxial structure can be SEG.
It should be noted that the state that the bottom in each lower channel hole is formed by epitaxial structure 535 is different, it is generally proximal to
The epitaxial structure 535 of device periphery or marginal position is grown bad, such as the thinner thickness of epitaxial structure 535.
Step S404, deposition forms superimposed layer on the lower lamination.
After the growth for completing epitaxial structure 535, as illustrated in figure 5f, deposition forms superimposed layer on the lower lamination
54, the superimposed layer 54 is identical as the lower lamination 53, can be formed by the way of vertical stacking multilayered memory unit.Example
Such as, superimposed layer 54 can be stacked and be formed by third material layer 543 and the 4th material layer 544 circulation.Wherein, third material layer 543
The number of plies with the 4th material layer 544 can be any amount.Using CVD or ALD or other depositional modes, successively under
Multilayer third material layer 543 and the 4th material layer 544 are alternately stacked on lamination 53.
In the present embodiment, third material layer 543 is semiconductor layer, and third material layer 543 can be silicon nitride；4th material
Layer 544 is insulating layer, and the 4th material layer 544 can be silica.
Step S405 selects M lower channel hole according to preset condition in N number of lower channel hole.
Here, described to select M lower channel hole in N number of lower channel hole according to preset condition, it can be selection institute
State the M bad lower channel hole of the growth of N number of lower channel hole epitaxial structures 535, or the position according to N number of lower channel hole
The M lower channel hole that selection is located at edge is set, or edge is located at according to the position selected section in N number of lower channel hole
The total M lower channel hole centrally located with part.
It is of course also possible to according to actual needs using other modes or according to other preset conditions described N number of lower logical
It selects M lower channel hole, to preset item based on when the present embodiment is to the mode and selection for selecting M lower channel hole in road hole
Part is simultaneously not specifically limited.
It should be noted that step S404 and step S405 can not have fixed sequencing, i.e., in the present invention one
In embodiment, step S404 can be first carried out and execute step S405 again, or in an alternative embodiment of the invention, can first carried out
Step S405 executes step S404 again.
Step S406, corresponding M lower channel hole, performs etching the superimposed layer, with the shape on the superimposed layer
At M upper channel hole.
Here, M lower channel hole is located at any position of the lower lamination.M lower channel hole is step
It is selected in N number of lower channel hole in S405.
In the present embodiment, only upper channel hole corresponding with M lower channel hole of selection is performed etching, it is lower for M logical
Other lower channel holes except road hole, the embodiment of the present invention do not perform etching corresponding upper channel hole.
As depicted in fig. 5g, corresponding M lower channel hole 533, performs etching the superimposed layer 54, described folded
M upper channel hole 541 is formed on layer 54.Wherein, lower channel hole 533a is not selected M lower channel hole, be in addition to
Access opening except selected M lower channel hole, corresponding position does not perform etching in corresponding superimposed layer 54.
Step S407, the side wall along M upper channel hole form M the second ONO structures from the inside to the outside.
In the forming process of three-dimensional storage part, above lead to when the superimposed layer for etching the three-dimensional storage part forms M
After road hole 541, also the second ONO structure forming step can be executed for the M upper channel hole 541.As illustrated in fig. 5h, at M
Barrier insulating layer is sequentially formed from the inside to the outside along the side wall in upper channel hole 541 in each upper channel hole in upper channel hole
5421, electric charge capture layer 5422 and tunneling insulation layer 5423.Barrier insulating layer 5421, electric charge capture layer 5422 and tunneling insulation layer
5423 constitute the accumulation layer of the three-dimensional storage part.Wherein, the material of barrier insulating layer 5421 can be silica, charge prisoner
The material for obtaining layer 5422 can be silicon nitride, and the material of tunneling insulation layer 5423 can be silica, in this way, by silica-nitrogen
The accumulation layer that SiClx-silica is formed is second ONO structure 542.Certainly, each layer in the second ONO structure can also
To select other materials, the present embodiment is not limited this.
The forming method of three-dimensional storage part provided in an embodiment of the present invention, firstly, etching three-dimensional storage part is lower folded
Layer, to form N number of lower channel hole；Side wall along N number of lower channel hole sequentially forms N number of first silica-nitrogen from the inside to the outside
SiClx-silica ONO structure；Selective epitaxial growth SEG is used in the bottom in N number of lower channel hole, forms N number of epitaxy junction
Structure；Then, deposition forms superimposed layer on the lower lamination；M are selected in N number of lower channel hole according to preset condition
Lower channel hole；Finally, corresponding M lower channel hole, performs etching the superimposed layer, to form institute on the superimposed layer
State M upper channel hole；Side wall along M upper channel hole forms M the second ONO structures from the inside to the outside.In this way, one corresponding
Divide etching of the lower channel hole without upper channel hole, wherein the part lower channel hole can be not form preferable epitaxy junction
The lower channel hole of structure, or for positioned at the lower channel hole of peripheral region；So, it is possible to avoid not formed due to lower channel hole compared with
Good epitaxial structure, or the lower channel hole relatively thin epitaxial structure easy to form due to being located at peripheral region, and bring device
The problems such as part reliability and electric leakage.
Embodiment three
The embodiment of the present invention provides a kind of three-dimensional storage part, and in the present embodiment, the three-dimensional storage part can be 3D
Flash memory, such as 3D nand flash memory.
Fig. 6 is the structural schematic diagram for the three-dimensional storage part that the embodiment of the present invention three provides, as shown in fig. 6, the three-dimensional
Memory device includes:
Lower lamination 61；
N number of lower channel hole 611 within the lower lamination 61；
The superimposed layer 62 being formed on the lower lamination 61；
The M upper channel hole 621 within the superimposed layer 62.
Here, lower lamination 61 is insulating layer and the alternately stacked stack layer of semiconductor layer.Lower lamination 61 can be using vertical
The mode of stacked multilayer storage unit is formed.For example, lower lamination 61 can be followed by first material layer 612 and second material layer 613
Ring stacks to be formed.Wherein, the number of plies of first material layer 612 and second material layer 613 can be any amount.Using CVD or
ALD or other depositional mode, successively alternating deposit stacked multilayer first material layer 612 and second material layer 613.Wherein,
First material layer 612 is semiconductor layer, and first material layer 612 can be silicon nitride；Second material layer 613 be insulating layer, second
Material layer 613 can be silica.
Lower channel hole 611 can etch lower lamination, until exposing for the through-hole in lower lamination 61 using lithographic technique
Substrate surface, to form lower channel hole 611.Alternatively, lower channel hole 611 can also be realized using photoetching technique, for example, covering
It is exposed after photoresist layer, then performs etching.In the present embodiment, the quantity N in the lower channel hole 611 in lower lamination 61 is greater than
Equal to 2.
Superimposed layer 62, it is identical as the lower lamination 61, it can be formed by the way of vertical stacking multilayered memory unit.Example
Such as, superimposed layer 62 can also be stacked and be formed by third material layer 622 and the 4th material layer 623 circulation.Wherein, third material layer
622 and the 4th the number of plies of material layer 623 can be any amount.Using CVD or ALD or other depositional modes, successively
Multilayer third material layer 622 and the 4th material layer 623 are alternately stacked on lower lamination 61.Wherein, third material layer 622 is half
Conductor layer, third material layer 622 can be silicon nitride；4th material layer 623 is insulating layer, and the 4th material layer 623 can be oxygen
SiClx.
Upper channel hole 621 is the through-hole in superimposed layer 62, as lower channel hole 611, can also be carved using lithographic technique
Lower lamination is lost, until exposing substrate surface, to form upper channel hole 621.Alternatively, upper channel hole 621 can also use photoetching
Technology is realized, for example, being exposed after covering photoresist layer, is then performed etching.It is upper in superimposed layer 62 in the present embodiment
The quantity M of access opening 621 is less than N.Correspond to a part of lower channel hole 611, the etching without upper channel hole 621.The M
M lower channel hole 611 in upper channel hole 621 and N number of lower channel hole corresponds
Three-dimensional storage part provided in an embodiment of the present invention, lower lamination have N number of lower channel hole, and superimposed layer has on M
Access opening, the quantity M in upper channel hole are less than the quantity N in lower channel hole, corresponding a part of lower channel hole, without upper channel hole
Etching, in this way, the three-dimensional storage part of the present embodiment can be avoided since part lower channel hole does not form preferable epitaxy junction
The problems such as structure and bring device reliability and electric leakage.
Example IV
The embodiment of the present invention provides a kind of three-dimensional storage part, and in the present embodiment, the three-dimensional storage part can be 3D
Flash memory, such as 3D nand flash memory.
Fig. 7 is the structural schematic diagram for the three-dimensional storage part that the embodiment of the present invention four provides, as shown in fig. 7, the three-dimensional
Memory device includes:
Substrate 71；
The separation layer 72 formed on the substrate 71；
Lamination 73 under being formed on the separation layer 72；
N number of lower channel hole 731 within the lower lamination 73；
Side wall along N number of lower channel hole 731 sequentially forms N number of first oxide-nitride-oxide from the inside to the outside
ONO structure 732；
Selective epitaxial growth SEG, N number of epitaxial structure 733 of formation are used in the bottom in N number of lower channel hole；
The superimposed layer 74 being formed on the lower lamination；
The M upper channel hole 741 within the superimposed layer；
Side wall along M upper channel hole forms M the second ONO structures 742 from the inside to the outside.
Here, the material of substrate 71 can choose Si, SiGe, SiC, Al2O3, AlN, ZnO, Ga2O3, LiAlO2 or
One of LiAlO3 etc..Since Si substrate is cheap, and it is easy to adulterate, while is prone to reaction and generating heterogeneous isolation
Layer, therefore can choose Si in the present embodiment as substrate 71.
Separation layer 72, can be silica material, and the effect of separation layer 72 is realized on substrate 71 and the separation layer 72
The electric isolation of portion's structure.
Lower lamination 73 is insulating layer and the alternately stacked stack layer of semiconductor layer.Lower lamination 73 can use vertical stacking
The mode of multilayered memory unit is formed.For example, lower lamination 73 can be recycled by first material layer 7301 and second material layer 7302
It stacks and is formed.
Lower channel hole 731 can etch lower lamination, until exposing for the through-hole in lower lamination 73 using lithographic technique
Substrate surface, to form lower channel hole 731.Alternatively, lower channel hole 731 can also be realized using photoetching technique, for example, covering
It is exposed after photoresist layer, then performs etching.In the present embodiment, the quantity N in the lower channel hole 731 in lower lamination 73 is greater than
Equal to 2.
First ONO structure 732, to sequentially form resistance from the inside to the outside along the side wall in lower channel hole 731 in lower channel hole
Keep off insulating layer 7311, electric charge capture layer 7312 and tunneling insulation layer 7313.Barrier insulating layer 7311, electric charge capture layer 7312 and tunnel
Wear the accumulation layer that insulating layer 7313 constitutes the three-dimensional storage part.Wherein, the material of barrier insulating layer 7311 can be oxidation
Silicon, the material of electric charge capture layer 7312 can be silicon nitride, and the material of tunneling insulation layer 7313 can be silica, in this way, by
The accumulation layer that oxide-nitride-oxide is formed is first ONO structure 732.Certainly, in the first ONO structure 732
Each layer also can choose other materials, the present embodiment does not limit this.In the present embodiment, each lower channel hole 731 is
With the first ONO structure 732.
The material of epitaxial structure 733, the bottom position positioned at lower channel hole 731, epitaxial structure 733 can be silicon, be formed
The mode of epitaxial structure can be SEG.
Superimposed layer 74, it is identical as the lower lamination 73, it can be formed by the way of vertical stacking multilayered memory unit.Example
Such as, superimposed layer 74 can also be stacked and be formed by third material layer 7401 and the 4th material layer 7402 circulation.Wherein, third material layer
7401 be semiconductor layer, and third material layer 7401 can be silicon nitride；4th material layer 7402 is insulating layer, the 4th material layer
7402 can be silica.
Upper channel hole 741 is the through-hole in superimposed layer 74, as lower channel hole 731, can also be carved using lithographic technique
Lower lamination is lost, until exposing substrate surface, to form upper channel hole 741.Alternatively, upper channel hole 741 can also use photoetching
Technology is realized.In the present embodiment, the quantity M in the upper channel hole 741 in superimposed layer 74 is less than N.
Second ONO structure 742, to sequentially form resistance from the inside to the outside along the side wall in upper channel hole 741 in upper channel hole
Keep off insulating layer 7411, electric charge capture layer 7412 and tunneling insulation layer 7413.Barrier insulating layer 7411, electric charge capture layer 7412 and tunnel
Wear the accumulation layer that insulating layer 7413 constitutes the three-dimensional storage part.Wherein, the material of barrier insulating layer 7411 can be oxidation
Silicon, the material of electric charge capture layer 7412 can be silicon nitride, and the material of tunneling insulation layer 7413 can be silica, in this way, by
The accumulation layer that oxide-nitride-oxide is formed is second ONO structure 742.Certainly, in the second ONO structure 742
Each layer also can choose other materials, the present embodiment does not limit this.In the present embodiment, each upper channel hole 741 is
With the second ONO structure 742.
Three-dimensional storage part provided in an embodiment of the present invention, lower lamination have N number of lower channel hole, and superimposed layer has on M
Access opening, the quantity M in upper channel hole are less than the quantity N in lower channel hole, corresponding a part of lower channel hole, without upper channel hole
Etching, wherein the part lower channel hole can be not form the lower channel hole of preferable epitaxial structure, or for positioned at periphery
The lower channel hole in region.In this way, the three-dimensional storage part of the present embodiment can be avoided since lower channel hole is not formed preferably
Epitaxial structure, or the lower channel hole relatively thin epitaxial structure easy to form due to being located at peripheral region, and bring device can
The problems such as by property and electric leakage.
It should be understood by those skilled in the art that, other of three-dimensional storage part of the embodiment of the present invention and forming method thereof
Constitute and effect, be all for a person skilled in the art it is known, in order to reduce redundancy, the embodiment of the present invention is not done
It repeats.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example " " specific example "
Or the description of " some examples " etc. means particular features, structures, materials, or characteristics packet described in conjunction with this embodiment or example
Contained at least one embodiment of the present invention or example.In the present specification, schematic expression of the above terms are not necessarily
Refer to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be any one
It can be combined in any suitable manner in a or multiple embodiment or examples.
Although an embodiment of the present invention has been shown and described, it will be understood by those skilled in the art that: not
A variety of change, modification, replacement and modification can be carried out to these embodiments in the case where being detached from the principle of the present invention and objective, this
The range of invention is by claim and its equivalent limits.
Claims (10)
1. a kind of forming method of three-dimensional storage part, which is characterized in that the described method includes:
The lower lamination of three-dimensional storage part is etched, to form N number of lower channel hole, wherein N is more than or equal to 2；
Deposition forms superimposed layer on the lower lamination；
The corresponding lower channel hole etches the superimposed layer, to form M upper channel hole, wherein M is less than N, and the M upper logical
M lower channel hole in road hole and N number of lower channel hole corresponds.
2. the method according to claim 1, wherein the correspondence lower channel hole etches the superimposed layer,
To form M upper channel hole, comprising:
M lower channel hole is selected in N number of lower channel hole according to preset condition；
Corresponding M lower channel hole, performs etching the superimposed layer, upper logical to form the M on the superimposed layer
Road hole, wherein M lower channel hole is located at any position of the lower lamination.
3. the method according to claim 1, wherein the method also includes:
Selective epitaxial growth SEG is used in the bottom in N number of lower channel hole, forms N number of epitaxial structure.
4. the method according to claim 1, wherein the method is also wrapped after forming N number of lower channel hole
It includes:
Side wall along N number of lower channel hole sequentially forms N number of first oxide-nitride-oxide ONO knot from the inside to the outside
Structure；
After forming M upper channel hole, the side wall along M upper channel hole forms M the second ONO structures from the inside to the outside.
5. the method according to claim 1, wherein the superimposed layer and the lower lamination by first material layer with
Second material layer circulation, which stacks, to be formed.
6. a kind of three-dimensional storage part, which is characterized in that the three-dimensional storage part includes:
Lower lamination；
N number of lower channel hole within the lower lamination, wherein N is more than or equal to 2；
The superimposed layer being formed on the lower lamination；
The M upper channel hole within the superimposed layer, wherein M be less than N, M upper channel hole and it is described it is N number of it is lower lead to
M lower channel hole in road hole corresponds.
7. three-dimensional storage part according to claim 6, which is characterized in that M lower channel hole is located at described lower folded
Any position of layer.
8. three-dimensional storage part according to claim 6, which is characterized in that the three-dimensional storage part further include:
N number of epitaxial structure, N number of epitaxial structure is formed by selective epitaxial growth SEG, and N number of epitaxial structure
Positioned at the bottom in N number of lower channel hole.
9. three-dimensional storage part according to claim 6, which is characterized in that the three-dimensional storage part further include:
N number of first oxide-nitride-oxide ONO knot that side wall along N number of lower channel hole sequentially forms from the inside to the outside
Structure；And the side wall along M upper channel hole is formed by M the second ONO structures from the inside to the outside.
10. three-dimensional storage part according to claim 6, which is characterized in that the superimposed layer and the lower lamination are by the
One material layer and second material layer circulation are stacked and are formed.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120061744A1 (en) * | 2010-09-10 | 2012-03-15 | Sung-Min Hwang | Three dimensional semiconductor memory devices |
| US20170345843A1 (en) * | 2016-05-27 | 2017-11-30 | Eun-young Lee | Vertical memory devices |
| CN108417576A (en) * | 2018-03-16 | 2018-08-17 | 长江存储科技有限责任公司 | Three-dimensional storage part and the method that epitaxial structure is formed in its raceway groove hole |
| CN109075170A (en) * | 2018-06-29 | 2018-12-21 | 长江存储科技有限责任公司 | Three-dimensional storage part with the stacking device chip for using interpolater |
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2018
- 2018-10-08 CN CN201811169251.7A patent/CN109326599B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120061744A1 (en) * | 2010-09-10 | 2012-03-15 | Sung-Min Hwang | Three dimensional semiconductor memory devices |
| US20170345843A1 (en) * | 2016-05-27 | 2017-11-30 | Eun-young Lee | Vertical memory devices |
| CN108417576A (en) * | 2018-03-16 | 2018-08-17 | 长江存储科技有限责任公司 | Three-dimensional storage part and the method that epitaxial structure is formed in its raceway groove hole |
| CN109075170A (en) * | 2018-06-29 | 2018-12-21 | 长江存储科技有限责任公司 | Three-dimensional storage part with the stacking device chip for using interpolater |
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