CN109326575A - A kind of low cost reroutes the manufacturing method of bump packaging structure - Google Patents
A kind of low cost reroutes the manufacturing method of bump packaging structure Download PDFInfo
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- CN109326575A CN109326575A CN201811124910.5A CN201811124910A CN109326575A CN 109326575 A CN109326575 A CN 109326575A CN 201811124910 A CN201811124910 A CN 201811124910A CN 109326575 A CN109326575 A CN 109326575A
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- bump
- rdl
- photoresist
- layer
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
The invention discloses the manufacturing methods that a kind of low cost reroutes bump packaging structure, comprising: PVD seed layer is formed on wafer；RDL layer photoresist is formed in PVD seed layer surface；Exposure is patterned to the RDL layer photoresist of formation, forms the exposure area RDL；Bump layer photoresist is formed on RDL layer photoresist after exposure；The image conversion exposure for carrying out Bump layer photoresist, forms the exposure area Bump；Development forms Bump and RDL plating window；Plating forms RDL and Bump structure；And remove the PVD seed layer of photoresist and leakage.This method combines Twi-lithography technique, can complete rewiring and two processing procedure of salient point by an electroplating technology, reduce processing step, shorten the process time, can save equipment, material cost, improve production capacity.
Description
Technical field
The present invention relates to semiconductor or (MEMS) the encapsulation technology field MEMS more particularly to a kind of low cost weight cloth
The manufacturing method of line bump packaging structure.
Background technique
With the development of semiconductor technology, especially semiconductor packaging, it is based on the BGA package technology of salient point (Bump)
Than traditional attachment based on pin and inserting with smaller volume, better heat dissipation performance and electrical property.This unofficial biography
The encapsulation of sensor, radio-frequency devices has better technique suitability and heat, electrical property using bump process.
Existing bump process generally includes placement-and-routing's technique again and Bumping technique, and this technique can be related to two
Cover lithographic process, it may be assumed that first by PVD seed layer deposition, gluing, exposure, development, be electroplated, remove photoresist, remove PVD seed layer with
And it applies insulating layer coating (such as PI) and forms placement-and-routing (RDL) layer again；Then again by PVD seed layer deposition, gluing, exposure
Light development, is electroplated, removes photoresist, removing PVD seed layer and Reflow Soldering formation salient point.
That there are process flows is long for above-mentioned existing bump process, needs to complete two sets of photoetching processes, and process costs height etc. lacks
Point.It is higher to cost requirement especially when for MEMS device encapsulation and other sensing device packages, while its opposite large scale
(RDL) layer of placement-and-routing again it is not high to the required precision of electroplating technology when, it would be desirable to simplify above-mentioned bump process processing procedure.
Overcome that process flow existing for above-mentioned bump process in the prior art is long, at high cost etc. asks in order at least part of
Topic, the invention proposes the manufacturing methods that a kind of low cost reroutes bump packaging structure, and Twi-lithography technique is combined, is passed through
Electroplating technology can complete rewiring and two processing procedure of salient point, reduce processing step, shorten process time, Ke Yijie
About equipment, material cost improve production capacity.
Summary of the invention
The problems such as long, at high cost for process flow existing for bump process in the prior art, one according to the present invention
Embodiment provides a kind of manufacturing method of low cost rewiring bump packaging structure, comprising: PVD kind is formed on wafer
Sublayer；RDL layer photoresist is formed in PVD seed layer surface；Exposure is patterned to the RDL layer photoresist of formation, forms RDL
Exposure area；Bump layer photoresist is formed on RDL layer photoresist after exposure；The image conversion for carrying out Bump layer photoresist exposes
Light forms the exposure area Bump；Development forms Bump and RDL plating window；Plating forms RDL and Bump structure；And removal
Photoresist and the PVD seed layer of leakage.
In one embodiment of the invention, the thickness of the Bump layer photoresist is greater than the thickness of the RDL layer photoresist
Degree, Bump layer photoresist and RDL layer photoresist are all positive photoresist.
In one embodiment of the invention, it is conduction copper column that the plating, which forms the Bump of RDL and Bump structure,.
In one embodiment of the invention, it is tin silver welded spheroid or tin that the plating, which forms the Bump of RDL and Bump structure,
Silver-bearing copper soldered ball.
In one embodiment of the invention, this method further includes carrying out Reflow Soldering to Bump structure.
According to another embodiment of the invention, a kind of manufacturing method of low cost rewiring bump packaging structure is provided,
Include:
PVD seed layer is formed on wafer；
RDL layer photoresist is formed in PVD seed layer surface；
Exposure is patterned to the RDL layer photoresist of formation, forms the exposure area RDL；
Develop to RDL layer photoresist, forms RDL and window is electroplated；
Bump layer photoresist is formed on RDL layer photoresist after development；
The image conversion exposure for carrying out Bump layer photoresist, forms the exposure area Bump；
Development forms Bump plating window；
Plating forms RDL and Bump structure；And
Remove the PVD seed layer of photoresist and leakage.
In another embodiment of the present invention, the Bump layer photoresist is the photoresist dry film that note covers, and thickness is big
In the thickness of the RDL layer photoresist.
In another embodiment of the present invention, it is conduction copper column that the plating, which forms the Bump of RDL and Bump structure,.
In another embodiment of the present invention, it is described be electroplated formed RDL and Bump structure Bump be tin silver welded spheroid or
Tin silver copper column.
In another embodiment of the present invention, this method further includes carrying out Reflow Soldering to Bump structure.
The invention proposes the manufacturing methods that a kind of low cost reroutes bump packaging structure, by after exposure again
Bump layer photoresist gluing, exposure technology are directly carried out on placement-and-routing's photoresist layer, then carry out a subsynchronous development, electricity
It plates, remove photoresist, removing the techniques such as PVD seed layer formation RDL and salient point.The step of reducing prior art, shortens the process time,
Equipment, material cost can be saved, production capacity is improved.
Detailed description of the invention
For the above and other advantages and features for each embodiment that the present invention is furture elucidated, will be presented with reference to attached drawing
The more specific description of various embodiments of the present invention.It is appreciated that these attached drawings only describe exemplary embodiments of the invention, therefore
It is not to be regarded as being restriction on its scope.In the accompanying drawings, in order to cheer and bright, identical or corresponding component will use identical or class
As mark indicate.
Fig. 1 shows a kind of diagrammatic cross-section of low cost rewiring bump packaging structure 100.
Fig. 2A to Fig. 2 I is shown forms a kind of low cost rewiring bump packaging structure according to one embodiment of present invention
100 process diagrammatic cross-section.
Fig. 3 is shown forms a kind of low cost rewiring bump packaging structure 100 according to one embodiment of present invention
Flow chart 300.
Fig. 4 A to Fig. 4 J is shown forms a kind of low cost rewiring bump packaging structure according to still another embodiment of the invention
100 process diagrammatic cross-section.
Fig. 5 is shown forms a kind of low cost rewiring bump packaging structure 100 according to still another embodiment of the invention
Flow chart 500.
Specific embodiment
In the following description, with reference to each embodiment, present invention is described.However, those skilled in the art will recognize
Know can in the case where none or multiple specific details or with other replacements and/or addition method, material or component
Implement each embodiment together.In other situations, well known structure, material or operation are not shown or are not described in detail in order to avoid making this
The aspects of each embodiment of invention is obscure.Similarly, for purposes of explanation, specific quantity, material and configuration are elaborated, with
Comprehensive understanding to the embodiment of the present invention is just provided.However, the present invention can be implemented in the case where no specific detail.This
Outside, it should be understood that each embodiment shown in the accompanying drawings is illustrative expression and is not drawn necessarily to scale.
In the present specification, the reference of " one embodiment " or " embodiment " is meaned to combine embodiment description
A particular feature, structure, or characteristic is included at least one embodiment of the invention.Occur in everywhere in this specification short
Language " in one embodiment " is not necessarily all referring to the same embodiment.
It should be noted that the embodiment of the present invention is described processing step with particular order, however this is only
Facilitate and distinguish each step, and is not the sequencing for limiting each step, it in different embodiments of the invention, can be according to work
Skill is adjusted to adjust the sequencing of each step.
The invention proposes the manufacturing methods that a kind of low cost reroutes bump packaging structure, by after exposure again
Bump layer photoresist gluing, exposure technology are directly carried out on placement-and-routing's photoresist layer, then carry out a subsynchronous development, electricity
It plates, remove photoresist, removing the techniques such as PVD seed layer formation RDL and salient point.The step of reducing prior art, shortens the process time,
Equipment, material cost can be saved, production capacity is improved.
A kind of low cost according to an embodiment of the invention is discussed in detail below with reference to Fig. 1 and reroutes salient point encapsulation
Structure.Fig. 1 shows a kind of diagrammatic cross-section of low cost rewiring bump packaging structure 100.As shown in Figure 1, low cost weight
Being routed bump packaging structure 100 further comprises wafer 101, chip bonding pad 102, again placement-and-routing (RDL) 103 and salient point
(Bump)104。
Wafer 101 is the wafer for having completed the element manufacturings such as chip or sensor.In one embodiment of the invention,
Wafer 101 can be the MEMS device for having completed three-dimensional micro fabrication.Wafer 101 can be silicon wafer wafer and be also possible to it
The wafer of his substrate, such as glass substrate, silicon carbide substrates.
Chip bonding pad 102 is the external interface of the electricity of function element and/or signal on wafer 101.In common technique,
Subsequent encapsulation needs again placement-and-routing that chip bonding pad 102 is reset to other positions, to obtain the better electricity of chip, calorifics
And mechanical performance.
Again placement-and-routing (RDL) 103 is used to chip bonding pad 102 being reset to other positions, and the chip after making encapsulation obtains
Obtain better electricity, calorifics and mechanical performance.Again 103 one end of placement-and-routing (RDL) and chip bonding pad 102 are electrically interconnected, separately
One end and salient point (Bump) are electrically interconnected.Again placement-and-routing (RDL) 103 is usually copper product.
Salient point (Bump) 104 is as the external electricity of chip and/or the interface of signal.Salient point (Bump) 104 can be conduction
Copper post (Copper pillar) or soldered ball.
It is described in detail to form this kind low cost rewiring bump packaging structure below with reference to Fig. 2A to Fig. 2 I and Fig. 3
100 process.Fig. 2A to Fig. 2 I is shown forms a kind of low cost rewiring salient point encapsulation knot according to one embodiment of present invention
The process diagrammatic cross-section of structure 100；Fig. 3 show formed according to one embodiment of present invention it is a kind of low cost reroute it is convex
The flow chart 300 of point encapsulating structure 100.
Firstly, as shown in Figure 2 A, forming PVD seed layer 202 on wafer 201 in step 301.At of the invention one
In embodiment, PVD seed layer 202 is formed by PVD deposition, and material is chromium-copper, and wherein layers of chrome thickness is about 500 angstroms, and layers of copper is thick
About 1000 angstroms to 3000 angstroms of degree.
Next, as shown in Figure 2 B, forming RDL layer photoetching on 202 surface of PVD seed layer of wafer 201 in step 302
Glue 203.The specific steps for forming RDL layer photoresist 203 further comprise drop glue, brush coating, drying glue.It is specific at of the invention one
In embodiment, RDL layer photoresist 203 is positive photoresist, and thickness is about 3 microns to 10 microns.
Then, in step 303, as shown in Figure 2 C, exposure is patterned to the RDL layer photoresist 203 of formation, is formed
The exposure area RDL 204.
Next, as shown in Figure 2 D, forming Bump layers of photoetching on RDL layer photoresist 203 after exposure in step 304
Glue 205.According to the needs of bump design, Bump layer photoresist 205 is usually thicker than RDL layer photoresist 203.In order to realize Bump layers
Photoresist 205 is synchronous with RDL layer photoresist 203 to develop and removes photoresist, and Bump layer photoresist 205 is also positive photoresist.
Then, in step 305, as shown in Figure 2 E, the image conversion exposure of Bump layer photoresist 205 is carried out, Bump is formed and exposes
Light region 206.
Next, as shown in Figure 2 F, development forms Bump and RDL plating window 207 in step 306.After development Bump and
RDL plating window 207 exposes PVD seed layer 202.
Then, in step 307, as shown in Figure 2 G, plating forms RDL and Bump structure 208.It is specific at of the invention one
In embodiment, RDL layer is layers of copper, and Bump is copper post (Copper Pillar), and specific electroplating technology can be by disposably synchronizing
Electro-coppering is formed.In still another embodiment of the invention, RDL layer is layers of copper, and Bump is Xi Yin or tin silver copper soldered ball, is being had
The copper pad for forming RDL and Bump bottom is electroplated by elder generation when being electroplated in copper plating tank for body, then again in another tin silver
Or subsequent Bump is electroplated in tin silver copper electroplating bath.
Finally, as illustrated in figure 2h, removing the PVD seed layer 202 of photoresist 203,205 and leakage in step 308.At this
In one specific embodiment of invention, photoresist lift off liquid removal photoresist 203,205 is first passed through, after cleaning, is passing through wet process
Etching technics removes PVD seed layer 202.In order to protect the binding force of RDL layer, needs to control etching technics in etching, prevent
Excessive lateral erosion.
It simultaneously optionally include that step 309 as shown in figure 2i, flows back to Bump in step 309.
Another this kind of formation low cost is described in detail below with reference to Fig. 4 A to Fig. 4 J and Fig. 5 and reroutes salient point encapsulation knot
The process of structure 100.Fig. 4 A to Fig. 4 J is shown forms a kind of low cost rewiring salient point encapsulation according to still another embodiment of the invention
The process diagrammatic cross-section of structure 100；Fig. 5 is shown forms a kind of low cost rewiring according to still another embodiment of the invention
The flow chart 500 of bump packaging structure 100.
Firstly, in step 501, it is similar with step 301 as shown in Figure 4 A, PVD seed layer 402 is formed on wafer 401.
In one embodiment of the invention, PVD seed layer 402 is formed by PVD deposition, and material is titanium copper, and wherein titanium layer thickness is about
It is 500 angstroms, copper layer thickness is about 1000 angstroms to 3000 angstroms.
Next, as shown in Figure 4 B, forming RDL layer photoetching on 402 surface of PVD seed layer of wafer 401 in step 502
Glue 403.The specific steps for forming RDL layer photoresist 403 further comprise drop glue, brush coating, drying glue.It is specific at of the invention one
In embodiment, RDL layer photoresist 403 is positive photoresist, and thickness is about 3 microns to 10 microns.
Then, in step 503, as shown in Figure 4 C, exposure is patterned to the RDL layer photoresist 403 of formation, is formed
The exposure area RDL 404.
Next, as shown in Figure 4 D, carrying out development in step 504 to RDL layer photoresist 403 and forming RDL plating window
405。
Then, in step 505, as shown in Figure 4 E, Bump layer photoresist is formed on RDL layer photoresist 403 after development
406.In one particular embodiment of the present invention, Bump layer photoresist 406 is formed by pasting photoresist dry film.
Next, as illustrated in figure 4f, carrying out the image conversion exposure of Bump layer photoresist 406 in step 506, forming Bump
Exposure area 407.
Then, in step 507, as shown in Figure 4 G, development forms Bump plating window 408.Window is electroplated in Bump after development
408 and RDL is electroplated window 405 and is connected, and exposes PVD seed layer 402.
It connects down, in step 508, as shown at figure 4h, plating forms RDL and Bump structure 409.It is specific at of the invention one
In embodiment, RDL layer is layers of copper, and Bump is copper post (Copper Pillar).In still another embodiment of the invention, RDL
Layer is layers of copper, and Bump is Xi Yin or tin silver copper column.
Finally, as shown in fig. 41, removing the PVD seed layer 402 of photoresist 403,406 and leakage in step 509.At this
In one specific embodiment of invention, photoresist lift off liquid removal photoresist 403,406 is first passed through, after cleaning, is passing through wet process
Etching technics removes PVD seed layer 402.In order to protect the binding force of RDL layer, needs to control etching technics in etching, prevent
Excessive lateral erosion.
It simultaneously optionally include that step 510 as shown in fig. 4j, flows back to Bump in step 510.
Manufacturing method that bump packaging structure is rerouted based on this kind provided by the invention low cost, by after exposure
Again Bump layer photoresist gluing, exposure technology are directly carried out on placement-and-routing's photoresist layer, then carry out one it is subsynchronous development,
It is electroplated, removes photoresist, removing the techniques such as PVD seed layer formation RDL and salient point.The step of reducing prior art, when shortening technique
Between, equipment, material cost can be saved, production capacity is improved.
Although described above is various embodiments of the present invention, however, it is to be understood that they are intended only as example to present
, and without limitation.For those skilled in the relevant art it is readily apparent that various combinations, modification can be made to it
Without departing from the spirit and scope of the invention with change.Therefore, the width of the invention disclosed herein and range should not be upper
It states disclosed exemplary embodiment to be limited, and should be defined according only to the appended claims and its equivalent replacement.
Claims (10)
1. the manufacturing method that a kind of low cost reroutes bump packaging structure, comprising:
PVD seed layer is formed on wafer；
RDL layer photoresist is formed in PVD seed layer surface；
Exposure is patterned to the RDL layer photoresist of formation, forms the exposure area RDL；
Bump layer photoresist is formed on RDL layer photoresist after exposure；
The image conversion exposure for carrying out Bump layer photoresist, forms the exposure area Bump；
Development forms Bump and RDL plating window；
Plating forms RDL and Bump structure；And
Remove the PVD seed layer of photoresist and leakage.
2. the method as described in claim 1, which is characterized in that the thickness of the Bump layer photoresist is greater than the RDL layer light
The thickness of photoresist, Bump layer photoresist and RDL layer photoresist are all positive photoresist.
3. the method as described in claim 1, which is characterized in that the plating forms the Bump of RDL and Bump structure as conduction
Copper post.
4. the method as described in claim 1, which is characterized in that the Bump that the plating forms RDL and Bump structure is tin silver
Soldered ball or tin silver copper soldered ball.
5. method as claimed in claim 4, which is characterized in that further include carrying out Reflow Soldering to Bump structure.
6. the manufacturing method that a kind of low cost reroutes bump packaging structure, comprising:
PVD seed layer is formed on wafer；
RDL layer photoresist is formed in PVD seed layer surface；
Exposure is patterned to the RDL layer photoresist of formation, forms the exposure area RDL；
Develop to RDL layer photoresist, forms RDL and window is electroplated；
Bump layer photoresist is formed on RDL layer photoresist after development；
The image conversion exposure for carrying out Bump layer photoresist, forms the exposure area Bump；
Development forms Bump plating window；
Plating forms RDL and Bump structure；And
Remove the PVD seed layer of photoresist and leakage.
7. method as claimed in claim 6, which is characterized in that the Bump layer photoresist is the photoresist dry film that note covers,
Thickness is greater than the thickness of the RDL layer photoresist.
8. method as claimed in claim 6, which is characterized in that the plating forms the Bump of RDL and Bump structure as conduction
Copper post.
9. method as claimed in claim 6, which is characterized in that the Bump that the plating forms RDL and Bump structure is tin silver
Soldered ball or tin silver copper column.
10. method as claimed in claim 9, which is characterized in that further include carrying out Reflow Soldering to Bump structure.
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| CN201811124910.5A CN109326575B (en) | 2018-09-26 | 2018-09-26 | Manufacturing method of low-cost rewiring bump packaging structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811124910.5A CN109326575B (en) | 2018-09-26 | 2018-09-26 | Manufacturing method of low-cost rewiring bump packaging structure |
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| CN109326575B CN109326575B (en) | 2020-03-31 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110320760A (en) * | 2019-05-29 | 2019-10-11 | 宁波芯健半导体有限公司 | It is a kind of that the identifiable exposure method of Wafer ID is guaranteed by multiple exposure |
| CN110544679A (en) * | 2019-08-30 | 2019-12-06 | 颀中科技（苏州）有限公司 | Chip rewiring structure and preparation method thereof |
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| JP2006294862A (en) * | 2005-04-11 | 2006-10-26 | Fujikura Ltd | Wiring circuit board and manufacturing method thereof |
| JP2007258629A (en) * | 2006-03-27 | 2007-10-04 | Yamaha Corp | Manufacturing method of chip size package |
| US20110074025A1 (en) * | 2007-01-31 | 2011-03-31 | Sanyo Electric Co., Ltd. | Semiconductor module, method of manufacturing semiconductor module, and mobile device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006294862A (en) * | 2005-04-11 | 2006-10-26 | Fujikura Ltd | Wiring circuit board and manufacturing method thereof |
| JP2007258629A (en) * | 2006-03-27 | 2007-10-04 | Yamaha Corp | Manufacturing method of chip size package |
| US20110074025A1 (en) * | 2007-01-31 | 2011-03-31 | Sanyo Electric Co., Ltd. | Semiconductor module, method of manufacturing semiconductor module, and mobile device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110320760A (en) * | 2019-05-29 | 2019-10-11 | 宁波芯健半导体有限公司 | It is a kind of that the identifiable exposure method of Wafer ID is guaranteed by multiple exposure |
| CN110544679A (en) * | 2019-08-30 | 2019-12-06 | 颀中科技（苏州）有限公司 | Chip rewiring structure and preparation method thereof |
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| CN109326575B (en) | 2020-03-31 |
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