CN109309495A - The D-latch of nuclear hardening - Google Patents
The D-latch of nuclear hardening Download PDFInfo
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- CN109309495A CN109309495A CN201811417813.5A CN201811417813A CN109309495A CN 109309495 A CN109309495 A CN 109309495A CN 201811417813 A CN201811417813 A CN 201811417813A CN 109309495 A CN109309495 A CN 109309495A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
Abstract
The D-latch of nuclear hardening belongs to the nuclear hardening field in IC reliability.Although hardware needed for solving traditional D-latch is more, power consumption is high, delay time is long and can realize anti-binode upset, there are anti-binode upset ability is poor, or even the problem of cannot achieve the appearance to binode upset.The present invention includes NMOS transistor N1 to N20, PMOS transistor P1 to P16 and phase inverter I1, and device used is few, and structure is simple, to reduce the power consumption of entire latch and possess lower hardware spending.The signal of latch inputs only passes through a transmission gate can be for transmission to output port, and data transmission period is short, additionally it is possible to realize to the fault-tolerant of any single node and binode upset, to realize the fault-tolerant protection of anti-single node and binode upset.The present invention can provide protection for the application of IC chip in high radiation environment (such as space flight and aviation and ground nuclear power station).
Description
Technical field
The invention belongs to the field of radioresistance reinforcement in IC reliability.
Background technique
D-latch is logic element of the product kind in digital circuit with memory function.It latches, is exactly that signal is temporary
Deposit to maintain certain level state, then can recorde binary digital signal " 0 " and " 1 " in digital circuit, therefore, be easy by
To the influence of extraneous radiating particle, so that the information saved changes.Traditional D-latch is the disadvantage is that required hardware is more, function
Consumption is high, delay time is long, although and can realize anti-binode upset, there are the ability of anti-binode upset is poor or even nothing
Method is realized to the fault-tolerant of binode upset.Therefore, the problem urgent need to resolve present on.
Summary of the invention
Although the present invention is in order to which hardware needed for solving traditional D-latch is more, power consumption is high, delay time is long and can be real
Now anti-binode upset, but there are the ability of anti-binode upset is poor, or even cannot achieve and the fault-tolerant of binode upset is asked
Topic, the present invention provides a kind of D-latch of nuclear hardening.
The D-latch of nuclear hardening, including NMOS transistor N1 to N20, PMOS transistor P1 to P16 and phase inverter I1；
After the drain electrode of transistor N16 to N18, the source electrode of transistor P16 are connected with the input terminal of phase inverter I1, as latch
The input terminal D of device；
After the grid of transistor N16 to N20 and the grid of transistor P15 connect simultaneously, the clock signal as latch
The input terminal of CLK；
After the grid of transistor P16 is connected with the grid of transistor N15, the input of the clock signal clk N as latch
End；
The source electrode of transistor N16, the drain electrode of transistor P16, the drain electrode of transistor P15 are connected with the drain electrode of transistor N15
Afterwards, as the output end Q of latch；The drain electrode of the output end and transistor N19 to N20 of phase inverter I1 connects simultaneously；
The source electrode of transistor N17, the source electrode of transistor N4, the drain electrode of transistor N2, the grid of transistor P3, transistor N1
Grid connected with the grid of transistor N12 after, as node a；
The source electrode of transistor N19, the source electrode of transistor N3, the drain electrode of transistor N1, the grid of transistor P4, transistor N2
Grid, after the grid of transistor N11, the grid of transistor P13 connect with the grid of transistor N14, as node b；
The grid of transistor P5, the grid of transistor P1, the drain electrode of transistor P6, the drain electrode of transistor N5 and transistor N4
Grid connection after, as node c；
The grid of transistor P6, the grid of transistor P2, the drain electrode of transistor P5, the drain electrode of transistor N6 and transistor N3
Grid connection after, as node d；
The source electrode of transistor N18, the grid of transistor N6, the source electrode of transistor N10, the drain electrode of transistor N8, transistor
After the grid of P9 is connected with the grid of transistor N7, as node e；
The source electrode of transistor N20, the grid of transistor N5, the source electrode of transistor N9, the drain electrode of transistor N7, transistor
The grid of P10, the grid of transistor N8, transistor P14 grid connected with the grid of transistor N13 after, as node f；
The grid of transistor P11, the grid of transistor P7, the drain electrode of transistor P12, the drain electrode of transistor N11 and crystal
After the grid connection of pipe N10, as node g；
The grid of transistor P12, the grid of transistor P8, the drain electrode of transistor P11, the drain electrode of transistor N12 and crystal
After the grid connection of pipe N9, as node h；The source electrode of transistor P1 to P2, the source electrode of transistor P5 to P6, transistor P7 to P8
Source electrode and the source electrode of transistor P11 to P13 connect with power supply；
The source electrode of transistor N1 to N 2, the source electrode of transistor N 5 to N 6, transistor N 7 to N 8 source electrode and transistor
The source electrode of N 11 to N 13 is connect with power ground；
The drain electrode of transistor P1 is connect with the source electrode of transistor P3, and the drain electrode of transistor P3 and the drain electrode of transistor N3 connect
It connects, the drain electrode of transistor P2 is connect with the source electrode of transistor P4, and the drain electrode of transistor P4 is connect with the drain electrode of transistor N4, crystal
The drain electrode of pipe P7 is connect with the source electrode of transistor P9, and the drain electrode of transistor P9 is connect with the drain electrode of transistor N9, transistor P8's
Drain electrode is connect with the source electrode of transistor P10, and the drain electrode of transistor P10 is connect with the drain electrode of transistor N10, the leakage of transistor P13
Pole is connect with the source electrode of transistor P14, and the drain electrode of transistor P14 is connect with the source electrode of transistor P15, the source electrode of transistor N15
It is connect with the drain electrode of transistor N14, the source electrode of transistor N14 is connect with the drain electrode of transistor N13.
Preferably, when clock signal clk is low level " 0 ", latches；Clock signal clk is high level " 1 "
When, latch conducting.
Preferably,
When latches low level " 0 ", latch sensitive nodes are b, c, d, f, g and h；
When latches high level " 1 ", latch sensitive nodes are a, c, d, e, g and h.
Preferably, the D-latch of the nuclear hardening, including normal operating conditions and fault-tolerant operation state.
Normal operating conditions includes following situation:
Situation one: assuming that the data input pin D=1 of latch；
(1) as CLK=1, CLKN=0, NMOS transistor N1, N4, N6, N7, N10, N12, N16 are opened to 20,
NMOS transistor N2, N3, N5, N8, N9, N11, N13 are turned off to N15, PMOS transistor P2, P4, P6, P8, P10, P12,
P13, P14, P16 are opened, and PMOS transistor P1, P3, P5, P7, P9, P11, P15 are turned off, at this point, a=c=e=g=Q=
1, b=d=f=h=0；
(2) as CLK=0, CLKN=1, NMOS transistor N16 to N20 and PMOS transistor P16 are closed, PMOS crystal
Pipe P15 is opened, and therefore, output end Q will connect power supply voltage by the PMOS transistor P13 to P15 of conducting, due to latching
The reason of device inner interlocked, output end Q will save always 1 state, and latch enters latch mode；
Situation two: assuming that the data input pin D=0 of latch；
(1) as CLK=1, CLKN=0, at this point, NMOS transistor N2, N3, N5, N8, N9, N11, N13, N14, N16 are extremely
N20 is opened, and NMOS transistor N1, N4, N6, N7, N10, N12, N15 are turned off, PMOS transistor P1, P3, P5, P7, P9,
P11, P16 are opened, and PMOS transistor P2, P4, P6, P8, P10, P12 to P15 are turned off, at this point, a=c=e=g=Q=0,
B=d=f=h=1；
(2) as CLK=0, CLKN=1, NMOS transistor N16 to N20 and PMOS transistor P16 are closed, NMOS crystal
Pipe N15 is opened, and therefore, output end Q will power on ground by the NMOS transistor N13 to N15 be connected, inside latch
The reason of interlocking, output end Q will save always 0 state, and latch enters latch mode；
Fault-tolerant operation state occurs during latches, and fault-tolerant operation state includes following situation:
Situation one:
When latches low level " 0 ", sensitive nodes b, c, d, f, g and h；It is any one in above-mentioned sensitive nodes
When a or two sensitive nodes are flipped, due to being constantly present two in the sensitive nodes and node a, e that are not flipped
Or more than two node states remain unchanged, and therefore, can restore above-mentioned one or two node being flipped to respective original
The state come；
Situation two:
When latches high level " 1 ", sensitive nodes a, c, d, e, g and h are any one in above-mentioned sensitive nodes
When a or two sensitive nodes are flipped, due to being constantly present two in the sensitive nodes and node b, f that are not flipped
Or more than two node states remain unchanged, and therefore, can restore above-mentioned one or two node being flipped to respective original
The state come.
Principle analysis:
Fault-tolerant operation state is unrelated with the received data-signal of data input pin D of latch, and fault-tolerant operation state occurs
It is related with the data that node each inside latch latches in latches state, low redundancy Flouride-resistani acid phesphatase D-latch fault-tolerant operation
State analysis is as follows: as clock signal CLK=0, CLKN=1,8 internal nodes a=c=e=g=1, b=d=f=h=0,
Output end Q=1, the inside sensitive nodes of the latch have 6, respectively a, c, d, e, g and h, above-mentioned 6 sensitivities at this time
Specific situation when one or two of node is flipped is as follows:
1, when node a is turned to 0, NMOS transistor N1, N12 will be closed.Remaining node will keep respective
State it is constant, therefore, PMOS transistor P2, P4 and NMOS transistor N4 will be opened always, and a node will be pulled back to originally
1, then, NMOS transistor N1, N12 will be opened.
2, when node c is turned to 0, PMOS transistor P5 and P1 will be turned on.Since the state of node e is not sent out
Changing, or 1 original state, this will be so that NMOS transistor N6 be constantly in open state, therefore node d will be 0
State, PMOS transistor P6 will be constantly on, and node c will be restored to 1 original state.
3, when node d is turned to 1, PMOS transistor P2 and P6 will be closed, and NMOS transistor N3 will be beaten
It opens.Remaining node will keep respective state constant, and therefore, NMOS transistor N6 will always be in open state, this will drop-down
Recovery nodes d is to original correct 0 state.
4, when node e is turned to 0, NMOS transistor N7, N6 will be closed.Remaining node will keep respective
State is constant, and therefore, PMOS transistor P8, P10 and NMOS transistor N10 will be opened always, and e node will be pulled back to originally
1, then, NMOS transistor N7, N6 will be opened.
5, when node g is turned to 0, PMOS transistor P11 and P7 will be turned on.Due to node a state not
It changes, or 1 original state, this will be so that NMOS transistor N12 be constantly in open state, therefore node h will
It is 0 state, PMOS transistor P12 will be constantly on, and node g will be restored to 1 original state.
6, when node h is turned to 1, PMOS transistor P8 and P12 will be closed, and NMOS transistor N9 will be beaten
It opens.Remaining node will keep respective state constant, and therefore, NMOS transistor N12 will always be in open state, this will drop-down
Recovery nodes h is to original correct 0 state.
7, when node a and c are flipped, PMOS transistor P5 and P1 will be turned on, NMOS transistor N1, N12,
N4 will be closed.But since the state of node e does not change, NMOS transistor N6 will always be in opening state
State, node d will always be in 0 state, and as a result PMOS transistor P6, P2 will be constantly on, and node c will be restored to original
1 state, PMOS transistor P5 and P1 will be closed, and NMOS transistor N4 will be turned on, and therefore, node a will pass through conducting
PMOS transistor P2, P4 and NMOS tube N4 are restored to 1 original state.
8, when node a and d are flipped, NMOS transistor N12, N1 and PMOS transistor P2 and P6 will be closed
It closes, NMOS transistor N3 and PMOS transistor P3 will be opened.But since the state of e node does not change,
NMOS transistor N6 will always be in open state, and node d will retract 0 original state under NMOS transistor N6 switched on,
Then, PMOS transistor P2 and P6 will be opened, and NMOS transistor N3 will be closed, and node a will pass through the PMOS crystal of conducting
Pipe P2, P4 and NMOS tube N4 are restored to 1 original state.
9, when node c and d are flipped, PMOS transistor P2 and P6 will be closed, and NMOS transistor N3 will be temporary
When be opened, PMOS transistor P5 and P1 will be opened temporarily, and NMOS transistor N4 will be temporarily closed.But due to node e
State do not change, therefore, NMOS transistor N6 will always be in open state, and node d will be restored to 0 state, because
This, PMOS transistor P2 and P6 will be turned on, and node c will also be restored to original correct status.
10, when node a and node e is flipped simultaneously, NMOS transistor N12, N1, N7, N6 will be closed.This
It will not influence the state of other nodes, therefore, node a will be restored by PMOS transistor P2, P4 of conducting and NMOS tube N4, section
Point e will be restored by PMOS transistor P8, P10 of conducting and NMOS tube N10.
11, when node a and node g is flipped simultaneously, NMOS transistor N12, N1, N10 will be temporarily closed,
PMOS transistor P11, P7 will be opened briefly near bottom dead center on.Since no change has taken place for the state of e node, NMOS transistor N6 will
Always on, node d will keep 0 original state, and PMOS transistor P2 will be always on.A node will be by leading always
Logical PMOS transistor P2, P4 and NMOS tube N4 is restored to original state.Then, NMOS transistor N12, N1 also will be extensive
Open state is arrived again, and therefore, node h will be always maintained at 0 state, and PMOS transistor P12 is always on opening, so node g
1 original state will be pulled up back.
12, when node a and node h is flipped simultaneously, NMOS transistor N12, N1 and PMOS transistor P8,
P12 will be temporarily closed, and NMOS transistor N9 will be opened briefly near bottom dead center on.Since no change has taken place for the state of e node,
NMOS transistor N6 will be always on, and node d will keep 0 original state, and PMOS transistor P2 will be always on.A section
Point will be restored to original state by constantly on PMOS transistor P2, P4 and NMOS tube N4.Then, NMOS transistor
N12, N1 will also be restored to open state, and therefore, node h will be restored to 0 original state.
13, when node c and node e is flipped simultaneously, PMOS transistor P5, P1 will be opened temporarily,
NMOS transistor N4, N7 and N6 will be temporarily closed.Since the state of node a is constantly in 1 original state, NMOS
Transistor N12 will always be in open state, and also all no change has taken place for the state of node g and node h, then PMOS transistor P8
It is in open state with NMOS transistor N10, therefore node e can be restored to 1.Then, NMOS transistor N6 will again
It is opened, node d will be in 0 original state, therefore PMOS transistor P6 will be in the open state, and node c will be extensive by meeting
Again to 1 state.
14, when node c and node g is flipped simultaneously, PMOS transistor P5, P1, P11, P7 will be opened temporarily
It opens, NMOS transistor N4 and N10 will be temporarily closed.Since all no change has taken place for the state of node a and node e,
NMOS transistor N6 and N12 will be constantly on, this will make node d and node h is 0 original state, PMOS transistor
P6 and P12 will be constantly on state, therefore node c and node g can be resumed.
15, when node c and node h is flipped simultaneously, PMOS transistor P5, P1 and NMOS transistor N9 will
It is temporarily opened, NMOS transistor N4 and PMOS tube P8, P12 will be temporarily closed.Since the state of node a and node e all do not have
It changes, therefore, NMOS transistor N6 and N12 will be constantly on, this will make node d be 0 original state, node
H can be restored to 0 original state.By the PMOS transistor P6 of conducting, node c will also be restored to 1 state.
16, when node d and node e is flipped simultaneously, PMOS transistor P2, P6 and NMOS transistor N7, N6
It will be temporarily closed, NMOS transistor N3 will be by temporary unlatching.Since the state of node a is unchanged, NMOS transistor N12 will
In the open state, also no change has taken place for the state of node g, h.Therefore, node e passes through the PMOS transistor by conducting
P8, P10 and NMOS transistor N10 restore to 1 original state.Then, NMOS transistor N7, N6 will be switched on again, node d
It will be restored by the NMOS transistor N6 be connected to original state 0.
17, when node d and node g is flipped simultaneously, PMOS transistor P2, P6 and NMOS transistor N10 will
It is temporarily closed, NMOS transistor N3 and PMOS transistor P11, P7 will be by temporary unlatchings.Since node a and node e are not sent out
Changing, therefore NMOS transistor N6 and N12 will be always on, node d will be restored to original state.Node h will
0 original state is kept, so that PMOS transistor P12 will be in the open state, node g will be pulled up go back to original 1.
18, when node d and node h is flipped simultaneously, PMOS transistor P2, P6, P8, P12 will be closed temporarily
It closes, NMOS transistor N3, N9 will be by temporary unlatchings.But since all no change has taken place for the state of a and e node,
NMOS transistor N6 and N12 will be constantly on, this restores node d and node h all to original state 0.
19, when node e and node g is flipped simultaneously, PMOS transistor P11 and P7 will be turned on, and NMOS is brilliant
Body pipe N7, N6, N10 will be closed.But since the state of node a does not change, NMOS transistor N12 will always
In the open state, node h will always be in 0 state, and as a result PMOS transistor P12, P8 will be constantly on, and node g will be by
It is restored to 1 original state, PMOS transistor P11 and P7 will be closed, and NMOS transistor N10 will be turned on, therefore, node e
1 original state will be restored to by PMOS transistor P8, P10 and NMOS tube N10 of conducting.
20, when node e and h are flipped, NMOS transistor N7, N6 and PMOS transistor P8 and P12 will be closed
It closes, NMOS transistor N9 and PMOS transistor P9 will be opened.But since the state of a node does not change,
NMOS transistor N12 will always be in open state, and node h will retract 0 original shape under NMOS transistor N12 switched on
State, then, PMOS transistor P8 and P12 will be opened, and NMOS transistor N9 will be closed, and node e will pass through the PMOS of conducting
Transistor P8, P10 and NMOS tube N10 are restored to 1 original state.
21, when node g and h are flipped, PMOS transistor P82 and P12 will be closed, and NMOS transistor N9 will
It is temporarily opened, PMOS transistor P11 and P7 will be opened temporarily, and NMOS transistor N10 will be temporarily closed.But due to section
The state of point a does not change, and therefore, NMOS transistor N12 will always be in open state, and node h will be restored to 0 shape
State, therefore, PMOS transistor P8 and P12 will be turned on, and node g will also be restored to original correct status.
To sum up, when one or two of 6 sensitive nodes are flipped, pass through above-mentioned analysis, it is found that total
There are two or more than two nodes no change has taken place, by its save value, these overturning states can restore.
Inventive concept of the invention is to be reinforced according to the physical characteristic that radiating particle bombarding semiconductor device generates
Design, therefore, node of the invention shares 8, respectively a, b, c, d, e, f, g and h, still, according to the value of latch, will latch
Sensitive nodes are reduced to 6 inside device, and sensitive area reduces, and the probability bombarded by radiating particle is caused also to reduce, compared to existing
Some D-latch, area, power consumption, delay will can be greatly reduced.
The invention has the beneficial effects that
(1) present invention shares 36 transistors and a phase inverter, and device used is few, and small in size, structure is simple, by institute
It is few with device, to reduce the power consumption of entire latch and possess lower hardware spending.
(2) in the present invention, data input pin D only passes through a transmission gate and (that is: can latch for transmission to output port
Device on state, data input pin D only can be transmitted directly by the transmission gate being made of transistor N16 and transistor P16
To the output end Q of latch), therefore, delay will also be reduced.
(3) existing D-latch is typically necessary the ability for the anti-overturning that can be only achieved in conjunction with laying out pattern, and this hair
It is bright not need cooperation diagram optimizing, because can restore after its internal any single node or binode are flipped, because
This, the ability of anti-single node and binode upset is improved, the D lock of the low anti-binode upset of redundancy of the present invention
Storage can be realized to the fault-tolerant of any single node and binode upset, to realize the appearance of anti-single node and binode upset
Error protection.
The D-latch for the nuclear hardening that the present invention constructs, high reliablity, can for high radiation environment (such as space flight and aviation with
And ground nuclear power station etc.) in IC chip application provide protection.
Detailed description of the invention
Fig. 1 is the schematic illustration of the D-latch of nuclear hardening of the present invention；
Fig. 2 is the analogous diagram of the D-latch of nuclear hardening of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art without making creative work it is obtained it is all its
Its embodiment, shall fall within the protection scope of the present invention.
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The present invention will be further explained below with reference to the attached drawings and specific examples, but not as the limitation of the invention.
Illustrate present embodiment, the D-latch of nuclear hardening described in present embodiment, including NMOS crystal referring to Fig. 1
Pipe N1 to N20, PMOS transistor P1 to P16 and phase inverter I1；
After the drain electrode of transistor N16 to N18, the source electrode of transistor P16 are connected with the input terminal of phase inverter I1, as latch
The input terminal D of device；
After the grid of transistor N16 to N20 and the grid of transistor P15 connect simultaneously, the clock signal as latch
The input terminal of CLK；
After the grid of transistor P16 is connected with the grid of transistor N15, the input of the clock signal clk N as latch
End；
The source electrode of transistor N16, the drain electrode of transistor P16, the drain electrode of transistor P15 are connected with the drain electrode of transistor N15
Afterwards, as the output end Q of latch；The drain electrode of the output end and transistor N19 to N20 of phase inverter I1 connects simultaneously；
The source electrode of transistor N17, the source electrode of transistor N4, the drain electrode of transistor N2, the grid of transistor P3, transistor N1
Grid connected with the grid of transistor N12 after, as node a；
The source electrode of transistor N19, the source electrode of transistor N3, the drain electrode of transistor N1, the grid of transistor P4, transistor N2
Grid, after the grid of transistor N11, the grid of transistor P13 connect with the grid of transistor N14, as node b；
The grid of transistor P5, the grid of transistor P1, the drain electrode of transistor P6, the drain electrode of transistor N5 and transistor N4
Grid connection after, as node c；
The grid of transistor P6, the grid of transistor P2, the drain electrode of transistor P5, the drain electrode of transistor N6 and transistor N3
Grid connection after, as node d；
The source electrode of transistor N18, the grid of transistor N6, the source electrode of transistor N10, the drain electrode of transistor N8, transistor
After the grid of P9 is connected with the grid of transistor N7, as node e；
The source electrode of transistor N20, the grid of transistor N5, the source electrode of transistor N9, the drain electrode of transistor N7, transistor
The grid of P10, the grid of transistor N8, transistor P14 grid connected with the grid of transistor N13 after, as node f；
The grid of transistor P11, the grid of transistor P7, the drain electrode of transistor P12, the drain electrode of transistor N11 and crystal
After the grid connection of pipe N10, as node g；
The grid of transistor P12, the grid of transistor P8, the drain electrode of transistor P11, the drain electrode of transistor N12 and crystal
After the grid connection of pipe N9, as node h；The source electrode of transistor P1 to P2, the source electrode of transistor P5 to P6, transistor P7 to P8
Source electrode and the source electrode of transistor P11 to P13 connect with power supply；
The source electrode of transistor N1 to N 2, the source electrode of transistor N 5 to N 6, transistor N 7 to N 8 source electrode and transistor
The source electrode of N 11 to N 13 is connect with power ground；
The drain electrode of transistor P1 is connect with the source electrode of transistor P3, and the drain electrode of transistor P3 and the drain electrode of transistor N3 connect
It connects, the drain electrode of transistor P2 is connect with the source electrode of transistor P4, and the drain electrode of transistor P4 is connect with the drain electrode of transistor N4, crystal
The drain electrode of pipe P7 is connect with the source electrode of transistor P9, and the drain electrode of transistor P9 is connect with the drain electrode of transistor N9, transistor P8's
Drain electrode is connect with the source electrode of transistor P10, and the drain electrode of transistor P10 is connect with the drain electrode of transistor N10, the leakage of transistor P13
Pole is connect with the source electrode of transistor P14, and the drain electrode of transistor P14 is connect with the source electrode of transistor P15, the source electrode of transistor N15
It is connect with the drain electrode of transistor N14, the source electrode of transistor N14 is connect with the drain electrode of transistor N13.
The D-latch of nuclear hardening described in present embodiment has a data input pin, two clock signal inputs
End and an output end, node shares 8, respectively a, b, c, d, e, f, g and h, still, according to the value of latch, by latch
Internal sensitive nodes are reduced to 6, and sensitive area reduces, and cause the probability bombarded by radiating particle also to reduce, compared to existing
D-latch, area, power consumption, delay will can be greatly reduced.
(1) present invention shares 36 transistors and a phase inverter, and device used is few, and small in size, structure is simple, by institute
It is few with device, to reduce the power consumption of entire latch and possess lower hardware spending.
(2) in the present invention, data input pin D only passes through a transmission gate and (that is: can latch for transmission to output port
Device on state, data input pin D only can be transmitted directly by the transmission gate being made of transistor N16 and transistor P16
To the output end Q of latch), therefore, delay will also be reduced.
(3) existing D-latch is typically necessary the ability for the anti-overturning that can be only achieved in conjunction with laying out pattern, and this hair
It is bright not need cooperation diagram optimizing, because can restore after its internal any single node or binode are flipped, because
This, the ability of anti-single node and binode upset is improved, the D lock of the low anti-binode upset of redundancy of the present invention
Storage can be realized to the fault-tolerant of any single node and binode upset, to realize the appearance of anti-single node and binode upset
Error protection.
Illustrate that this preferred embodiment, preferred embodiment are referring to Fig. 1, when clock signal clk is low level " 0 ", lock
Storage latches；When clock signal clk is high level " 1 ", latch conducting, it may be assumed that data input pin D is only by by transistor P16
Latch outputs Q can be transmitted directly to the transistor N16 transmission gate constituted.
Although latch node of the present invention shares 8, respectively a, b, c, d, e, f, g and h, according to latch
Value, sensitive nodes are reduced to 6:
When latches low level " 0 ", latch sensitive nodes are b, c, d, f, g and h；
When latches high level " 1 ", latch sensitive nodes are a, c, d, e, g and h.
Illustrate that this preferred embodiment, preferred embodiment are referring to Fig. 1, the D-latch of nuclear hardening includes normal work
Make state and fault-tolerant operation state.
(1) normal operating conditions includes following situation:
Situation one: assuming that the data input pin D=1 of latch；
(1) as CLK=1, CLKN=0, NMOS transistor N1, N4, N6, N7, N10, N12, N16 are opened to 20,
NMOS transistor N2, N3, N5, N8, N9, N11, N13 are turned off to N15, PMOS transistor P2, P4, P6, P8, P10, P12,
P13, P14, P16 are opened, and PMOS transistor P1, P3, P5, P7, P9, P11, P15 are turned off, at this point, a=c=e=g=Q=
1, b=d=f=h=0；
(2) as CLK=0, CLKN=1, NMOS transistor N16 to N20 and PMOS transistor P16 are closed, PMOS crystal
Pipe P15 is opened, and therefore, output end Q will connect power supply voltage by the PMOS transistor P13 to P15 of conducting, due to latching
The reason of device inner interlocked, output end Q will save always 1 state, and latch enters latch mode, at this point, data input pin D
Any variation will not affect that output end Q；
Situation two: assuming that the data input pin D=0 of latch；
(1) as CLK=1, CLKN=0, at this point, NMOS transistor N2, N3, N5, N8, N9, N11, N13, N14, N16 are extremely
N20 is opened, and NMOS transistor N1, N4, N6, N7, N10, N12, N15 are turned off, PMOS transistor P1, P3, P5, P7, P9,
P11, P16 are opened, and PMOS transistor P2, P4, P6, P8, P10, P12 to P15 are turned off, at this point, a=c=e=g=Q=0,
B=d=f=h=1；
(2) as CLK=0, CLKN=1, NMOS transistor N16 to N20 and PMOS transistor P16 are closed, NMOS crystal
Pipe N15 is opened, and therefore, output end Q will power on ground by the NMOS transistor N13 to N15 be connected, inside latch
The reason of interlocking, output end Q will save always 0 state, and latch enters latch mode, at this point, any change of data input pin D
Change will not affect that output end Q；
(2) fault-tolerant operation state occurs during latches, and fault-tolerant operation state includes following situation:
Situation one:
When latches low level " 0 ", sensitive nodes b, c, d, f, g and h；It is any one in above-mentioned sensitive nodes
When a or two sensitive nodes are flipped, due to being constantly present two in the sensitive nodes and node a, e that are not flipped
Or more than two node states remain unchanged, and therefore, can restore above-mentioned one or two node being flipped to respective original
The state come；
Situation two:
When latches high level " 1 ", sensitive nodes a, c, d, e, g and h are any one in above-mentioned sensitive nodes
When a or two sensitive nodes are flipped, due to being constantly present two in the sensitive nodes and node b, f that are not flipped
Or more than two node states remain unchanged, and therefore, can restore above-mentioned one or two node being flipped to respective original
The state come.
Verification test: referring specifically to Fig. 2, showing the analogous diagram of the D-latch of nuclear hardening of the present invention in Fig. 2,
Pass through the analogous diagram, it can be seen that the timing function and fault tolerance of the D-latch for the novel nuclear hardening that the present invention constructs be
Correctly.Such as: between CLK time 30ns~60ns, once inside out is respectively had occurred in node a, c, d, e, g and h, but final
Original state can be restored to；Between CLK time 150ns~165ns, node a-d, a-e, a-g, a-h have occurred respectively
The overturning of binode, but can also be restored to respective correct state.
Although describing the present invention herein with reference to specific embodiment, it should be understood that, these realities
Apply the example that example is only principles and applications.It should therefore be understood that can be carried out to exemplary embodiment
Many modifications, and can be designed that other arrangements, without departing from spirit of the invention as defined in the appended claims
And range.It should be understood that different appurtenances can be combined by being different from mode described in original claim
Benefit requires and feature described herein.It will also be appreciated that the feature in conjunction with described in separate embodiments can be used
Other embodiments.
Claims (6)
1. the D-latch of nuclear hardening, which is characterized in that including NMOS transistor N1 to N20, PMOS transistor P1 to P16 and
Phase inverter I1；
After the drain electrode of transistor N16 to N18, the source electrode of transistor P16 are connected with the input terminal of phase inverter I1, as latch
Input terminal D；
After the grid of the grid of transistor N16 to N20 and transistor P15 connect simultaneously, clock signal clk as latch
Input terminal；
After the grid of transistor P16 is connected with the grid of transistor N15, the input terminal of the clock signal clk N as latch；
After the source electrode of transistor N16, the drain electrode of transistor P16, the drain electrode of transistor P15 are connected with the drain electrode of transistor N15, make
For the output end Q of latch；The drain electrode of the output end and transistor N19 to N20 of phase inverter I1 connects simultaneously；
The source electrode of transistor N17, the source electrode of transistor N4, the drain electrode of transistor N2, the grid of transistor P3, transistor N1 grid
After pole is connected with the grid of transistor N12, as node a；
The source electrode of transistor N19, the source electrode of transistor N3, the drain electrode of transistor N1, the grid of transistor P4, transistor N2 grid
Pole, the grid of transistor N11, transistor P13 grid connected with the grid of transistor N14 after, as node b；
The grid of transistor P5, the grid of transistor P1, the drain electrode of transistor P6, the drain electrode of transistor N5 and transistor N4 grid
After the connection of pole, as node c；
The grid of transistor P6, the grid of transistor P2, the drain electrode of transistor P5, the drain electrode of transistor N6 and transistor N3 grid
After the connection of pole, as node d；
The source electrode of transistor N18, the grid of transistor N6, the source electrode of transistor N10, the drain electrode of transistor N8, transistor P9
After grid is connected with the grid of transistor N7, as node e；
The source electrode of transistor N20, the grid of transistor N5, the source electrode of transistor N9, the drain electrode of transistor N7, transistor P10
Grid, the grid of transistor N8, transistor P14 grid connected with the grid of transistor N13 after, as node f；
The grid of transistor P11, the grid of transistor P7, the drain electrode of transistor P12, the drain electrode of transistor N11 and transistor N10
Grid connection after, as node g；
The grid of transistor P12, the grid of transistor P8, the drain electrode of transistor P11, the drain electrode of transistor N12 and transistor N9
Grid connection after, as node h；The source of the source electrode of transistor P1 to P2, the source electrode of transistor P5 to P6, transistor P7 to P8
The source electrode of pole and transistor P11 to P13 are connect with power supply；
The source electrode of transistor N1 to N2, the source electrode of transistor N5 to N6, transistor N7 to N8 source electrode and transistor N11 to N13
Source electrode connect with power ground；
The drain electrode of transistor P1 is connect with the source electrode of transistor P3, and the drain electrode of transistor P3 is connect with the drain electrode of transistor N3, brilliant
The drain electrode of body pipe P2 is connect with the source electrode of transistor P4, and the drain electrode of transistor P4 is connect with the drain electrode of transistor N4, transistor P7
Drain electrode connect with the source electrode of transistor P9, the drain electrode of transistor P9 is connect with the drain electrode of transistor N9, the drain electrode of transistor P8
Connect with the source electrode of transistor P10, the drain electrode of transistor P10 is connect with the drain electrode of transistor N10, the drain electrode of transistor P13 with
The source electrode of transistor P14 connects, and the drain electrode of transistor P14 is connect with the source electrode of transistor P15, the source electrode and crystalline substance of transistor N15
The drain electrode of body pipe N14 connects, and the source electrode of transistor N14 is connect with the drain electrode of transistor N13.
2. the D-latch of nuclear hardening according to claim 1, which is characterized in that clock signal clk is low level " 0 "
When, latches；When clock signal clk is high level " 1 ", latch conducting.
3. the D-latch of nuclear hardening according to claim 1 or 2, which is characterized in that
When latches low level " 0 ", latch sensitive nodes are b, c, d, f, g and h；
When latches high level " 1 ", latch sensitive nodes are a, c, d, e, g and h.
4. the D-latch of nuclear hardening according to claim 1, which is characterized in that including normal operating conditions and fault-tolerant
Working condition.
5. the D-latch of nuclear hardening according to claim 4, which is characterized in that normal operating conditions includes following feelings
Condition:
Situation one: assuming that the data input pin D=1 of latch；
(1) as CLK=1, CLKN=0, NMOS transistor N1, N4, N6, N7, N10, N12, N16 are opened to 20, and NMOS is brilliant
Body pipe N2, N3, N5, N8, N9, N11, N13 to N15 is turned off, PMOS transistor P2, P4, P6, P8, P10, P12, P13, P14,
P16 is opened, and PMOS transistor P1, P3, P5, P7, P9, P11, P15 are turned off, at this point, a=c=e=g=Q=1, b=d=
F=h=0；
(2) as CLK=0, CLKN=1, NMOS transistor N16 to N20 and PMOS transistor P16 are closed, PMOS transistor P15
It opens, therefore, output end Q will connect power supply voltage by the PMOS transistor P13 to P15 of conducting, due in latch
The reason of portion interlocks, output end Q will save always 1 state, and latch enters latch mode；
Situation two: assuming that the data input pin D=0 of latch；
(1) as CLK=1, CLKN=0, at this point, NMOS transistor N2, N3, N5, N8, N9, N11, N13, N14, N16 are to N20
Open, NMOS transistor N1, N4, N6, N7, N10, N12, N15 are turned off, PMOS transistor P1, P3, P5, P7, P9, P11,
P16 is opened, and PMOS transistor P2, P4, P6, P8, P10, P12 to P15 are turned off, at this point, a=c=e=g=Q=0, b=d
=f=h=1；
(2) as CLK=0, CLKN=1, NMOS transistor N16 to N20 and PMOS transistor P16 are closed, NMOS transistor N15
It opens, therefore, output end Q will power on ground by the NMOS transistor N13 to N15 be connected, due to latch inner interlocked
The reason of, output end Q will save always 0 state, and latch enters latch mode.
6. the D-latch of nuclear hardening according to claim 4, which is characterized in that the generation of fault-tolerant operation state is being latched
In device latching process, fault-tolerant operation state includes following situation:
Situation one:
When latches low level " 0 ", sensitive nodes b, c, d, f, g and h；Any one in above-mentioned sensitive nodes or
When two sensitive nodes are flipped, due to being constantly present two or two in the sensitive nodes and node a, e that are not flipped
A above node state remains unchanged, and therefore, can restore above-mentioned one or two node being flipped to respectively original
State；
Situation two:
When latches high level " 1 ", sensitive nodes a, c, d, e, g and h, any one in above-mentioned sensitive nodes or
When two sensitive nodes are flipped, due to being constantly present two or two in the sensitive nodes and node b, f that are not flipped
A above node state remains unchanged, and therefore, can restore above-mentioned one or two node being flipped to respectively original
State.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811417813.5A CN109309495A (en) | 2018-11-26 | 2018-11-26 | The D-latch of nuclear hardening |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811417813.5A CN109309495A (en) | 2018-11-26 | 2018-11-26 | The D-latch of nuclear hardening |
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ID=65222405
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110995236A (en) * | 2019-12-26 | 2020-04-10 | 中北大学 | High-frequency circuit application-oriented charge sharing resistant D latch |
| CN111030668A (en) * | 2019-12-26 | 2020-04-17 | 中北大学 | Charge sharing resistant D latch for use in medium and low frequency circuitry |
-
2018
- 2018-11-26 CN CN201811417813.5A patent/CN109309495A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110995236A (en) * | 2019-12-26 | 2020-04-10 | 中北大学 | High-frequency circuit application-oriented charge sharing resistant D latch |
| CN111030668A (en) * | 2019-12-26 | 2020-04-17 | 中北大学 | Charge sharing resistant D latch for use in medium and low frequency circuitry |
| CN111030668B (en) * | 2019-12-26 | 2022-04-26 | 中北大学 | Charge sharing resistant D latch for use in medium and low frequency circuitry |
| CN110995236B (en) * | 2019-12-26 | 2022-04-26 | 中北大学 | High-frequency circuit application-oriented charge sharing resistant D latch |
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Application publication date: 20190205 |