CN109308993B - Reworking method for integrated circuit manufacturing process - Google Patents
Reworking method for integrated circuit manufacturing process Download PDFInfo
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- CN109308993B CN109308993B CN201810991770.5A CN201810991770A CN109308993B CN 109308993 B CN109308993 B CN 109308993B CN 201810991770 A CN201810991770 A CN 201810991770A CN 109308993 B CN109308993 B CN 109308993B
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- photoresist
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
Abstract
The invention discloses a reworking method of an integrated circuit manufacturing process, which comprises the following steps: step one, forming photoresist on a semiconductor substrate, and carrying out a first photoetching process; step two, detecting after development, and performing the following reworking steps when the detection after development exceeds the range: step 21, carrying out comprehensive second exposure on the photoresist by adopting a blank photomask; step 22, carrying out second development to remove the photoresist for the first time; and step 23, dissolving by adopting a photoresist decrement process to remove the photoresist for the second time. The invention can increase the removal rate of the photoresist, prevent the photoresist residue and eliminate the pollution of the photoresist residue on the subsequent wet etching machine.
Description
Technical Field
The present invention relates to semiconductor integrated circuit manufacturing, and more particularly to a rework method of an integrated circuit manufacturing process.
Background
The integrated manufacturing method of NMOS and PMOS with high dielectric constant metal grid (HKMG) comprises the steps of forming a grid dielectric layer with high dielectric constant (HK) and forming a metal grid simultaneously in the HKMG process, wherein a post metal grid process is usually adopted in the conventional HKMG process, and a virtual polysilicon grid, namely a pseudo polysilicon grid, is usually adopted in the post metal grid process, the pseudo polysilicon grid is used for forming the grid dielectric layer, a channel region and a source drain region of a device, then replacement of the metal grid is carried out, namely the pseudo polysilicon grid is removed, and the metal grid is formed by filling a region where the pseudo polysilicon grid is removed with metal.
In the existing metal gate-last process, after the dummy polysilicon gate is usually removed, a layer of TiN is deposited as a work function metal layer of the PMOS, and then the TiN layer in the NMOS region is removed by one-time photolithography and etching processes. The deposition of the work function metal layer TiAl of the NMOS is followed by the filling of the metal gate, the material of which is usually Al, and then the Chemical Mechanical Polishing (CMP) is carried out.
In performing the photolithography of the TiN layer, a bottom anti-reflective coating (BARC) consisting of a sacrificial siloxane polymer (DUO) is generally used, and after the DUO layer is formed on the TiN layer, a photoresist is coated, generally, a process layer consisting of the DUO as BARC and a top-coated photoresist is called NRG, and the photoresist material is generally used as SEPR 612; carrying out a photoetching process, wherein the whole photoetching process comprises exposure and development, carrying out post-development detection (ADI) after the development, carrying out a reworking step when the detection result after the development exceeds the range, wherein the reworking process is to remove NRG, re-form the NRG and then carry out photoetching; removing NRG is one of the critical steps in the rework process, and is required to ensure that NRG does not affect other structures and processing equipment to be formed. As shown in fig. 1A to 1C, the device structure diagram in each step of the rework method of the conventional integrated circuit manufacturing process; the following is an example of the photolithography of a TiN layer:
as shown in fig. 1A, a DUO layer 102 and a photoresist 103 are sequentially formed on a TiN layer 101.
Then, photolithography is performed, the photoresist 103 is sequentially exposed and developed in the photolithography process, and a pattern structure of the photoresist 103 is formed after development.
Thereafter, a pattern structure formed in the photoresist 103 after the ADI inspection development is performed, and if the ADI inspection fails, rework is required. The rework process first requires removal of the photoresist 103 followed by removal of the DUO layer 102.
As shown in fig. 1B, the photoresist 103 is directly removed by a Resist Reduction (RRC) process in the conventional method. In practice, however, after the RRC process is completed, a portion of the photoresist 103 remains on the DUO layer 102, and the remaining photoresist is separately denoted by reference numeral 103B in fig. 1B.
After that, the DUO layer 102 is removed. In the prior art, the DUO layer 102 is usually removed by a wet etching process, such as cleaning the DUO layer 102 by using a solvent CLK888 in an Etching (ETCH) region, and the cleaning process usually employs a repeat mode (recycle mode). Since the photoresist residue 103a is present in the photoresist removing process, the photoresist residue 103a is carried into the cleaning process of the DUO layer 102. As shown in fig. 1C, in the cleaning process of the DUO layer 102, the photoresist residue 103a may be cleaned into the wet etching tool, which may cause contamination of the wet etching tool.
Disclosure of Invention
The invention aims to provide a reworking method of an integrated circuit manufacturing process, which can prevent photoresist residues from being formed after photoresist reworking.
In order to solve the above technical problems, the rework method of the integrated circuit manufacturing process provided by the present invention comprises the following steps:
step one, forming photoresist on a semiconductor substrate, and carrying out a first photoetching process, wherein the first photoetching process comprises first exposure and first development.
Step two, detecting after development, and performing the following reworking steps when the detection after development exceeds the range:
and step 21, carrying out comprehensive second exposure on the photoresist by adopting a blank photomask.
And step 22, carrying out second development on the photoresist, and carrying out first removal on the photoresist by combining the second exposure and the second development.
And 23, removing the photoresist for the second time by adopting a photoresist reduction process, and increasing the removal rate of the photoresist by combining the first removal and the second removal to prevent the photoresist from remaining.
In a further improvement, the first step further comprises the step of forming a bottom anti-reflective coating before forming the photoresist, wherein the photoresist is coated on the bottom anti-reflective coating.
In a further improvement, an integrated circuit fabrication process is used to form a CMOS device with HKMG.
In a further improvement, the HKMG is formed using a post-metal gate process comprising the steps of:
and sequentially forming a gate dielectric layer and a polysilicon gate on the surface of the semiconductor substrate, wherein the gate dielectric layer comprises a high-dielectric-constant material layer.
And forming a side wall on the side surface of the polysilicon gate.
And forming a source region and a drain region on the surface of the semiconductor substrate on two sides of the polysilicon gate.
A contact etching stopper layer and an interlayer film are sequentially formed.
And flattening, wherein the top surface of the polysilicon gate is exposed after flattening.
And removing the polysilicon gate and forming a gate groove in the polysilicon gate removing region, wherein the gate groove is used for forming a metal gate.
A metal work function layer is formed.
Forming a bottom anti-reflection coating.
And step one, forming the photoresist.
In a further improvement, if the post-development detection in step two passes, the following process is performed:
and etching the bottom anti-reflection coating.
And etching the metal work function layer.
And forming the metal gate.
In a further improvement, after the rework step of step two is completed, the method further comprises the steps of:
and removing the bottom anti-reflection coating.
In a further improvement, the bottom anti-reflective coating is DUO.
In a further improvement, the bottom anti-reflection coating is removed by a wet etching process.
In a further refinement, the CMOS devices comprise NMOS devices and PMOS devices.
The further improvement is that the metal work function layer of the PMOS device is made of TiN; the metal work function layer of the PMOS device is made of TiAl.
In a further improvement, an interface layer is also formed between the high-dielectric-constant material layer of the gate dielectric layer and the semiconductor substrate; and a first anti-diffusion layer is arranged between the high-dielectric-constant material layer of the gate dielectric layer and the metal work function layer, and a second anti-diffusion layer is arranged between the metal work function layer and the metal gate.
In a further improvement, the semiconductor substrate is a silicon substrate, and the interface layer is silicon oxide.
In a further improvement, the material of the first anti-diffusion layer is TaN.
In a further improvement, the second anti-diffusion layer is formed by sequentially stacking TiN and Ti.
In a further improvement, the metal grid is made of aluminum or tungsten.
In the reworking process, a process step of carrying out overall exposure on the photoresist by adopting a blank photomask, namely, a second exposure, is added before the photoresist is removed, and the photoresist can be basically removed through a developing process after exposure, so that a first development, namely, a second development, is added after the second exposure, and the photoresist is removed for the first time by combining the second exposure and the second development.
And then, the photoresist is removed for the second time by adopting a photoresist reduction process, and the photoresist after the second development is basically removed and can be basically and completely removed after the photoresist reduction process, so that the removal rate of the photoresist can be increased by combining the first removal and the second removal, and the photoresist residue is prevented.
After the photoresist is not left, the photoresist can be prevented from polluting a wet etching machine when the semiconductor substrate is subjected to subsequent wet etching cleaning.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIGS. 1A-1C are device structure diagrams at various steps of a rework method of a prior integrated circuit fabrication process;
FIG. 2 is a flow chart of a rework method of an integrated circuit manufacturing process, in accordance with an embodiment of the present invention;
fig. 3A-3D are device structure diagrams in steps of a method according to an embodiment of the invention.
Detailed Description
FIG. 2 is a flow chart of a rework method of the integrated circuit manufacturing process according to an embodiment of the invention; as shown in fig. 3A to fig. 3D, which are device structure diagrams in the steps of the method according to the embodiment of the present invention, the rework method of the integrated circuit manufacturing process according to the embodiment of the present invention includes the following steps:
step one, as shown in fig. 3A, a photoresist 3 is formed on a semiconductor substrate, and a first photolithography process is performed, where the first photolithography process includes first exposure and first development.
The method also comprises a step of forming a bottom anti-reflection coating 2 before forming the photoresist 3, and the photoresist is coated on the bottom anti-reflection coating 2.
In an embodiment of the invention, an integrated circuit fabrication process is used to form a CMOS device with an HKMG.
The HKMG is formed by adopting a post-metal gate process and comprises the following steps before the photoresist 3 is formed:
and sequentially forming a gate dielectric layer and a polysilicon gate on the surface of the semiconductor substrate, wherein the gate dielectric layer comprises a high-dielectric-constant material layer.
And forming a side wall on the side surface of the polysilicon gate.
And forming a source region and a drain region on the surface of the semiconductor substrate on two sides of the polysilicon gate.
A contact etching stopper layer and an interlayer film are sequentially formed.
And flattening, wherein the top surface of the polysilicon gate is exposed after flattening.
And removing the polysilicon gate and forming a gate groove in the polysilicon gate removing region, wherein the gate groove is used for forming a metal gate.
A metallic work function layer 1 is formed.
The bottom anti-reflection coating 2 is formed. The material of the bottom anti-reflection coating 2 is DUO.
Step two, detecting after development, and performing the following reworking steps when the detection after development exceeds the range:
step 21, as shown in fig. 3A, the photoresist uses the blank mask 4 to perform a second exposure on the photoresist 3.
Step 22, as shown in fig. 3A, performing a second development on the photoresist 3, and performing a first removal on the photoresist 3 by combining the second exposure and the second development. The corresponding schematic diagram after the first removal process is completed is shown in fig. 3B, where the photoresist 3 is substantially removed and the remaining photoresist is denoted by reference numeral 3 a.
Step 23, as shown in fig. 3C, a photoresist 3 reduction process is adopted to remove the photoresist 3, i.e. the photoresist residue 3a, for the second time. The schematic after the second removal process is shown in fig. 3D. Therefore, the embodiment of the present invention combines the first removal and the second removal to increase the removal rate of the photoresist 3, thereby preventing the photoresist 3 from remaining. Because no photoresist residue is left after the second removal process, adverse effects of the photoresist residue on subsequent processes can not occur, for example, the photoresist can not pollute a wet etching machine when the wet etching process is adopted in the subsequent processes.
In the embodiment of the present invention, after the rework step of removing the photoresist is completed, the method further includes the steps of:
the bottom anti-reflection coating 2 is removed. And the bottom anti-reflection coating 2 is removed by adopting a wet etching process.
In an embodiment of the invention, the CMOS device comprises an NMOS device and a PMOS device.
The metal work function layer 1 of the PMOS device is made of TiN; the metal work function layer 1 of the PMOS device is made of TiAl. The metal work function layer 1 shown in fig. 3A is illustrated by taking TiN as an example.
Forming an interface layer between the high-dielectric-constant material layer of the gate dielectric layer and the semiconductor substrate; and a first anti-diffusion layer is arranged between the high-dielectric-constant material layer of the gate dielectric layer and the metal work function layer 1, and a second anti-diffusion layer is arranged between the metal work function layer 1 and the metal gate.
The semiconductor substrate is a silicon substrate, and the interface layer is silicon oxide.
The material of the first anti-diffusion layer is TaN.
The second anti-diffusion layer is formed by sequentially overlapping TiN and Ti.
The metal grid is made of aluminum or tungsten.
In the embodiment of the invention, if the post-development detection in the second step passes, the following process is performed:
and etching the bottom anti-reflection coating 2.
And etching the metal work function layer 1.
And then forming the metal gate.
In the rework process of the embodiment of the invention, a process step of performing overall exposure on the photoresist 3 by using the blank photomask 4, namely, a second exposure, is added before the photoresist 3 is removed, and since the photoresist 3 can be basically removed by a developing process after exposure, a first development, namely, a second development, is added after the second exposure, and the photoresist 3 is removed for the first time by combining the second exposure and the second development.
And then, the photoresist 3 is removed for the second time by adopting the photoresist 3 reduction process, and the photoresist 3 after the second development is basically removed, so that the photoresist 3 can be basically and completely removed after the photoresist 3 reduction process, and the removal rate of the photoresist 3 can be increased by combining the first removal and the second removal, and the photoresist 3 is prevented from remaining.
After the photoresist 3 is not left, the photoresist 3 can be prevented from polluting a wet etching machine when the semiconductor substrate is subjected to subsequent wet etching cleaning.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (11)
1. A rework method of an integrated circuit manufacturing process, comprising the steps of:
forming photoresist on a semiconductor substrate, and carrying out a first photoetching process, wherein the first photoetching process comprises first exposure and first development;
before forming the photoresist, forming a bottom anti-reflection coating on which the photoresist is coated;
the material of the bottom anti-reflection coating is DUO;
step two, detecting after development, and performing the following reworking steps when the detection after development exceeds the range:
step 21, carrying out comprehensive second exposure on the photoresist by adopting a blank photomask;
step 22, carrying out second development on the photoresist, and carrying out first removal on the photoresist by combining the second exposure and the second development;
step 23, removing the photoresist for the second time by adopting a photoresist reduction process, and increasing the removal rate of the photoresist by combining the first removal and the second removal to prevent the photoresist from remaining;
further comprising the steps of:
removing the bottom anti-reflection coating; and the bottom anti-reflection coating is removed by adopting a wet etching process.
2. A method of rework of the integrated circuit manufacturing process as recited in claim 1, wherein: an integrated circuit fabrication process is used to form CMOS devices with HKMG.
3. A method of rework of the integrated circuit manufacturing process as recited in claim 1, wherein: the HKMG is formed by adopting a post-metal gate process and comprises the following steps:
sequentially forming a gate dielectric layer and a polysilicon gate on the surface of the semiconductor substrate, wherein the gate dielectric layer comprises a high-dielectric-constant material layer;
forming a side wall on the side face of the polysilicon gate;
forming a source region and a drain region on the surface of the semiconductor substrate on two sides of the polysilicon gate;
sequentially forming a contact etching stop layer and an interlayer film;
flattening, wherein the top surface of the polysilicon gate is exposed after flattening;
removing the polysilicon gate and forming a gate groove in the polysilicon gate removing region, wherein the gate groove is used for forming a metal gate;
forming a metal work function layer;
forming the bottom anti-reflection coating;
and step one, forming the photoresist.
4. A method of rework of the integrated circuit manufacturing process as recited in claim 3, wherein: and if the detection after the development in the step two passes, performing the following process:
etching the bottom anti-reflection coating;
etching the metal work function layer;
and forming the metal gate.
5. A method of rework of the integrated circuit manufacturing process as recited in claim 3, wherein: the CMOS devices include NMOS devices and PMOS devices.
6. The method of rework of integrated circuit manufacturing processes as recited in claim 5, wherein: the metal work function layer of the PMOS device is made of TiN; the metal work function layer of the NMOS device is made of TiAl.
7. A method of rework of the integrated circuit manufacturing process as recited in claim 6, wherein: forming an interface layer between the high-dielectric-constant material layer of the gate dielectric layer and the semiconductor substrate; and a first anti-diffusion layer is arranged between the high-dielectric-constant material layer of the gate dielectric layer and the metal work function layer, and a second anti-diffusion layer is arranged between the metal work function layer and the metal gate.
8. A method of rework of the integrated circuit manufacturing process as recited in claim 7, wherein: the semiconductor substrate is a silicon substrate, and the interface layer is silicon oxide.
9. A method of rework of the integrated circuit manufacturing process as recited in claim 7, wherein: the material of the first anti-diffusion layer is TaN.
10. A method of rework of the integrated circuit manufacturing process as recited in claim 7, wherein: the second anti-diffusion layer is formed by sequentially overlapping TiN and Ti.
11. A method of rework of the integrated circuit manufacturing process as recited in claim 7, wherein: the metal grid is made of aluminum or tungsten.
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| US7276316B2 (en) * | 2004-02-02 | 2007-10-02 | International Business Machines Corporation | Common second level frame exposure methods for making embedded attenuated phase shift masks |
| KR20070002632A (en) * | 2005-06-30 | 2007-01-05 | 주식회사 하이닉스반도체 | Method for forming a semiconductor device |
| CN101281379A (en) * | 2007-04-03 | 2008-10-08 | 中芯国际集成电路制造(上海)有限公司 | Method for removing photoresist as well as method for reworking of photoetching technology |
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| CN101154047A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Reworking processing method |
| JP2012256726A (en) * | 2011-06-09 | 2012-12-27 | Panasonic Corp | Rework method for resist film, manufacturing method for semiconductor device, and substrate processing system |
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