CN109285824A - Dual chip TO-252 lead frame and semiconductor packing device - Google Patents
Dual chip TO-252 lead frame and semiconductor packing device Download PDFInfo
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- CN109285824A CN109285824A CN201811338171.XA CN201811338171A CN109285824A CN 109285824 A CN109285824 A CN 109285824A CN 201811338171 A CN201811338171 A CN 201811338171A CN 109285824 A CN109285824 A CN 109285824A
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- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000012856 packing Methods 0.000 title claims description 9
- 230000009977 dual effect Effects 0.000 title abstract description 15
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical group [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims abstract description 25
- 238000009434 installation Methods 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 abstract description 24
- 230000017525 heat dissipation Effects 0.000 abstract description 20
- 238000005538 encapsulation Methods 0.000 description 28
- 238000005286 illumination Methods 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000007789 sealing Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 210000001699 lower leg Anatomy 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 241001465382 Physalis alkekengi Species 0.000 description 1
- 239000012080 ambient air Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005485 electric heating Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Led Device Packages (AREA)
Abstract
The present invention discloses a kind of dual chip TO-252 lead frame, and lead wire unit includes the first Ji Dao, second Ji Dao and four terminal pin, wherein the first lead foot positioned at the lead wire unit leftmost side or the rightmost side is connected with the first Ji Dao；Second Ji Dao is located at the end of second terminal pin adjacent with first lead foot；Second, third, the spacing between the 4th terminal pin be TO-252-5L standard pin pitch, the spacing between first and second terminal pin is twice of standard pin pitch.The present invention significantly improves the heat dissipation performance of packaging body while with low-cost advantage.
Description
Technical field
The present invention relates to the encapsulation of semiconductor devices, in particular to a kind of dual chip TO-252 lead frame, and
Using the semiconductor packing device of the lead frame.
Background technique
As the lighting source of a new generation, light emitting diode (LED) has been used widely.In global illumination market,
LED illumination is estimated to account for seventy percent or more.Occupation rate of market from 1% to 70%, LED illumination have only used the time less than 10 years.
So fast growth rate is based on two aspect reasons, first is that the really more energy efficient environmental protection of LED illumination；Second is that LED illumination lamp cost
Decline rapidly, or even already below the cost of traditional lighting lamps and lanterns.
Before 5 years, 1 watt of LED luminescence chip average price is at 1 yuan, and the price of current same chip is no more than
0.1 yuan, price declines 10 times or more.It is similar therewith, between past 5 years, the price of other all accessories of LED lamp
It also reduced 10 times or more.This includes the constant current drive integrated circult for being used as LED drive power core devices certainly, is commonly called as constant current
Driving chip.Before 5 years, constant-current driven chip market price is at 2 yuans or so, and current generally the least expensive driving chip price is
Lower than 0.15 yuan.The main reason for inexpensive is that chip dosage all too is big.Currently, the dosage of chip every month is 500,000,000
Only between 1,000,000,000, than 5 years before increase by 50 times or more.It can be said that 5 years in the past are exactly that LED constant current driving chip is rapidly sent out
5 years of exhibition.
The invention mainly relates to the encapsulation of LED constant current driving chip.Chip package is exactly briefly by chip die
The integrated circuit die (Die) of factory's production is put on the lead frame that one piece is played carrying, then pin is drawn, and is then fixed
Packaging becomes an entirety.Encapsulation can be played the role of protecting chip, be equivalent to the shell of chip, be not only capable of fixing, seal
Chip, moreover it is possible to enhance its electric heating property.Therefore, it for integrated circuit, encapsulates extremely important.Semiconductor industry history is not
It is long, since invention bipolar semiconductor triode in 1949, it has been less than 70 years.So semiconductor packages most begins around three
Pole pipe expansion gradually forms serial mature encapsulation after decades of development, for example, TO-89 series, TO-220 series and
TO-252 series, is three feet；Prefix TO is the abbreviation of English Transistor Outline (triode shape).Wherein,
TO-89 series is plug-in unit encapsulation, is suitble to low current, low-power applications；TO-220 series is also plug-in unit encapsulation, can install outside
Radiator is suitble to high current, high-power applications；TO-252 series is surface mount packages, relies primarily on PCB (printed circuit board) help
Heat dissipation is suitble to medium current, medium power applications, is suitable for automated production.
Integrated circuit is invented in nineteen fifty-nine, than transistor late ten years, away from the present less than 60 years.Earliest mature
Integrated antenna package be dual-in-line package DIP (Dual In-line Package), such as DIP-28, DIP-14, DIP-8.
For 1970s to the beginning of the eighties, computer CPU just uses DIP to encapsulate.Phase at the end of the seventies in last century, the exploitation of PHILIP company
Small external form surface mount packages SOP (Small Outline Package), such as SOP-8, SOP-16, SOP-28 are gone out, have still existed so far
It is a large amount of to use.Thus the encapsulation of SSOP, TSSOP series is gradually derived, it is extremely successful.
In early stage mainstream LED illumination driving power, two parts --- current constant control core that constant-current driven chip is included
Piece and pliotron are to separate encapsulation；For example current constant control chip uses the single-chip of SOP-8 encapsulation, and power tube is adopted
The MOS triode encapsulated with TO-220 or TO-252.Before 5 years, comes into vogue and control chip and pliotron conjunction envelope
SOP-8 and DIP-8 encapsulation, all there are two the Ji Dao of mutual insulating for both packaging frames.Close the constant-current driven chip of envelope significantly
The cost of LED drive power is reduced, while being greatly simplified the production of LED drive power, so that LED lamp illumination market
Fast Growth.Just start that there is better heat-sinking capability due to closing envelope DIP-8, it occupies most of market.But because of Surface Mount
SOP-8 encapsulates automated production lower than DIP-8 packaging cost and being more suitable for LED drive power, closes envelope SOP-8 and occupied later
On surpass in reverse rapidly, become the absolute encapsulation overlord in LED illumination market.Until currently, it is still LED that SOP-8 and DIP-8, which closes envelope encapsulation,
The absolute mainstream packing forms of constant-current driven chip, 95% or more market accounting, wherein DIP-8 encapsulates accounting no more than 5%.And
The form that control chip and power tube separately encapsulate accounts for the remaining market less than 5%, and 90% or more power tube uses among these
TO-252 surface mount packages；This is because TO-252 packaging cost is lower, and Surface Mount is more advantageous to compared with the TO-220 of plug-in unit encapsulation
The automated production of LED illumination power supply.
The encapsulation history of evolution of LED constant current driving chip is summarized as follows: most being started current constant control chip and power tube and is separated
Encapsulation；It is transitioned into the conjunction envelope stage of the two again, plug-in unit closes envelope DIP-8 before this, is then transitioned into more inexpensive Surface Mount rapidly and closes
Seal SOP-8.It is obvious that low cost is the first leading factor that LED constant current driving chip encapsulation is developed.Second leading factor is then
Pursue high production efficiency.It is equally to close envelope, conjunction envelope DIP-8, which is not only higher than on packaging cost, closes envelope SOP-8, but also is producing
It is much lower in efficiency.
Close envelope SOP-8 advantage be it is at low cost, be no more than 5 points of RMB, optimization space is little on packaging cost.But close envelope
SOP-8 also has disadvantage, is exactly that packaging body heat dissipation performance is bad.The switching regulator function that sealing chip is tape controller is closed in LED constant current driving
Rate device requires the heat dissipation performance of packaging body.But SOP-8 early stage is normal integrated circuit and develops, and is not appropriate for function
Rate device.SOP-8 packaging body will radiate mainly by eight thin metal pipe feet in thermal conductivity to PCB, direct secondly by plastic-sealed body
It radiates to ambient air, this is also the bad reason for it of SOP-8 heat dissipation.
The heat of switching power devices all is from power loss.Loss is divided into two parts, and a part is posting for power device
Switching loss caused by raw capacitor, this partition losses and switching frequency are substantially linear；Another part is that power tube exists
The conduction loss that conducting phase is generated due to conducting resistance.Because switching frequency is not high, generally in 50KHz or so, so LED
The switching loss of constant-current driven chip only accounts for secondary part.Dominant loss is conduction loss, accounts for eighty per cant or more, and and power tube
Conducting resistance it is linear.Therefore, power device total losses can be approximately equal to conduction loss, as shown in formula 1, wherein K
For proportionality coefficient.In the case where input voltage, output electric current, output power are constant, K is exactly a constant.
PLOSS≈K*Rdson (1)
Above formula explanation, in the case where external condition is certain, the thermal losses P of power deviceLOSSWith power tube conducting resistance
RdsonIt is substantially proportional to.Conducting resistance is bigger, and thermal losses is bigger, and the heat dissipation pressure of pairing sealing chip packaging body is also bigger.
In the identical situation of thermal losses, the heat-sinking capability for closing sealing chip packaging body is poorer, and chip operating temperature will be higher；And chip
Operating temperature has a upper limit, for example highest (is only illustrated, actual conditions may not here no more than 120 degrees Celsius
Together).Close the heat dissipation performance of envelope SOP-8 than close seal poor one times of DIP-8 or more (thick one times of DIP-8 metal pin or more, plastic-sealed body body
Product also wants two to three times big), which means that SOP-8 encapsulates chip ratio DIP-8 and encapsulates chip under same working environment
Operating temperature doubles above.It can be concluded that, same chip operation is obtained under same operating condition in conjunction with formula 1
Temperature, the conducting resistance R of SOP-8 internal power pipedsonThan the conducting resistance R of DIP-8 internal power pipedsonAs soon as small times,
It is that the area of power tube will be twice, corresponding power tube cost will double.
Following table lists mesh first two prevalence and closes the relativity encapsulated between each index.For convenience, all fingers
Conjunction envelope SOP-8 is marked with to be normalized for standard.Wherein, " efficiency cost " comparison, which is referred to, is processed into LED using chip finished product
The comparison of the material and processing charges of illumination driving power source.It on the one hand, is plug-in unit due to closing envelope DIP-8, it is general to be inserted using manual
Part, it is low efficiency, costly；On the other hand, big due to closing envelope DIP-8 volume, PCB surface product is also big, and Material Cost also will increase, institute
SOP-8 high is sealed more than conjunction with its efficiency cost." total application cost " includes three parts: " packaging cost ", " power tube cost " with
" efficiency cost ".As shown in the following chart, the total application cost for closing envelope DIP-8 is twice or more for closing the envelope total application cost of SOP-8, it
It is defeated by the latter on the market and also belongs to reasonable.
| Close envelope SOP-8 | Close envelope DIP-8 | |
| Heat dissipation performance | 1 | 2 |
| Packaging cost | 1 | 2.5 |
| Power tube cost | 1 | 0.5 |
| Efficiency cost | 1 | 4 |
| Total application cost | 1 | 2~3 times |
LED illumination enters market only 10 years, in 30 years futures, also can't see alternative lighting engineering.With regard to LED perseverance
For flowing driving chip, the SOP-8 of mainstream closes encapsulation technique it is not possible that unalterable at present；Especially, as it was noted above, closing envelope
There is poor heat radiation in the packaging body of SOP-8, it is also faced with innovation and asks change.
Summary of the invention
It is an object of the present invention in view of the above problems in the prior art, provided for LED constant current driving chip a kind of new
Encapsulation technology significantly improves the heat dissipation performance of packaging body while with low-cost advantage.
According to the first aspect of the invention, a kind of TO-252 lead frame is provided, including it is multiple by dowel be connected
Lead wire unit, the lead wire unit include the first Ji Dao, second Ji Dao and four terminal pin, wherein first Ji Dao is used
In carrying the first chip, relative to the second Ji Dao one predetermined altitude of sinking；Positioned at the lead wire unit leftmost side or the rightmost side
First lead foot is connected with the first Ji Dao；Second Ji Dao is located at and the first lead foot phase for carrying the second chip
The end of the second adjacent terminal pin；Second, third, the spacing between the 4th terminal pin be TO-252-5L standard pin pitch, first with
Spacing between second terminal pin is twice of the standard pin pitch.
In the first aspect, it is preferred that the minimum widith of second Ji Dao is TO-252-5L standard pin pitch and mark
The sum of quasi- pin width.
Preferably, the shape of first Ji Dao and area use TO-252-5L standard.
Preferably, first chip is power chip, and the second chip is that LED constant current controls chip, and described first draws
Stitch is power tube high input voltage foot.
According to second aspect, a kind of semiconductor packing device is provided, including plastic-sealed body, is encapsulated within the plastic-sealed body
Lead wire unit and the first, second chip, which is characterized in that the lead wire unit includes the first Ji Dao, the second Ji Dao and four
Terminal pin, wherein first Ji Dao sinks a predetermined altitude relative to the second Ji Dao, installs described first on the first Ji Dao
Chip；First lead foot positioned at the lead wire unit leftmost side or the rightmost side is connected with the first Ji Dao；Second base island position
In the end of second terminal pin adjacent with the first lead foot, second chip is installed on the second Ji Dao, described first
Chip and the second chip by bonding wire with second, third, the 4th terminal pin connect；Second, third, between the 4th terminal pin between
Away from for TO-252-5L standard pin pitch, the spacing between first and second terminal pin is twice of the standard pin pitch.
In second aspect, it is preferred that the minimum widith of second Ji Dao is TO-252-5L standard pin pitch and mark
The sum of quasi- pin width.
Preferably, the shape of first Ji Dao and area use TO-252-5L standard.
Preferably, first chip is power chip, and the second chip is that LED constant current controls chip, and described first draws
Stitch is power tube high input voltage foot.
According to the present invention, LED constant current driving chip is encapsulated using the dual chip TO-252 lead frame of innovation, due to adopting
It is installed with patch, high degree of automation, cost per efficiency unit is with regard to low.Under equal conditions, the present invention closes envelope TO-252-4L packaging body
Heat dissipation performance can reach and close envelope four times or more of SOP-8 heat dissipation performance, correspondingly, power tube cost only has four points of the latter
One of, the present invention closes total application cost of envelope TO-252-4L encapsulation lower than conjunction envelope SOP-8 encapsulation.
Detailed description of the invention
For a better understanding of the invention, hereafter with embodiment combination attached drawing, the invention will be further described.In attached drawing:
Fig. 1 is the sample application circuit of typical LED constant current driving chip；
Fig. 2 is the lead frame structure figure of general TO-252-5L；
Fig. 3 is the dual chip TO-252 lead frame structure figure of one embodiment of the invention；
Fig. 4 shows lead wire unit 101 in the dual chip TO-252 lead frame of two rows of arrangements；
Fig. 5 is the dual chip TO-252 lead frame structure figure of another embodiment of the present invention；
Fig. 6 shows lead wire unit 201 in the dual chip TO-252 lead frame of two rows of arrangements；
Fig. 7 is the TO-252 lead frame structure figure that one embodiment of the invention is equipped with chip；
Fig. 8 is the cross-sectional view of TO-252 lead frame shown in Fig. 7.
Specific embodiment
Currently, it is substantially minimum in view of total application cost of the conjunction envelope SOP-8 of occupation rate of market first, it to be LED constant current
Driving chip finds a kind of lower new encapsulation scheme of total application cost, need to meet first the following: first is that allowing for double
Chip closes envelope；Second is that necessary patch encapsulation, it is not possible to be plug-in unit encapsulation, such efficiency cost Fang Yuhe envelope SOP-8 is suitable；Third is that
Heat dissipation performance is good enough, and not worse than the heat dissipation performance of conjunction envelope DIP-8 is more, and it is better to radiate, and power tube cost is accordingly lower；
Fourth is that packaging cost cannot be too high, preferably suitable with envelope SOP-8 is closed, height can not be high too many.
In order to enable heat dissipation performance is good enough, need to set about finding from existing power device package.On current market
The power package of large-scale use mainly has TO-220, TO-247, TO-263, TO-252 several.Wherein, TO-220, TO-247
Belong to plug-in unit encapsulation, is unsatisfactory for requirement of the invention；It is screened out from it TO-252, TO-263 of patch encapsulation, for further
It considers.
Next consider cost.Big 6 times of SOP-8 of TO-263 volume ratio or more, packaging cost are 3 times of SOP-8 or more.
And the volume of TO-252 is only about two times larger than SOP-8, packaging cost relatively SOP-8, and it is only slightly higher, it is no more than
1.5 again, substantially meeting requirement.
In general, TO-252 encapsulation complies fully with above-mentioned requirements two, three and at 4 points, unique problem be can carry out it is double
Chip closes envelope, this is also difficult point of the invention.
The TO-252 encapsulation of present mainstream be divided to two kinds, a kind of to develop three pins encapsulated for triode earliest
TO-252-3L；Another kind is the TO-252-5L of five pins derived on the basis of TO-252-3L.
Fig. 1 is the sample application circuit of typical LED constant current driving chip.As shown in Figure 1, typical close envelope constant current driving core
Piece 030 at least has four pins: foot CS power supply foot VDD, is arranged with reference to lower margin GND, power tube high input voltage foot HV, electric current.
If Switching Power Supply, circuit for power conversion 070 then includes the devices such as transformer or inductance, freewheeling diode；If linear electricity
Source, circuit for power conversion 070 is then much simpler, may only include several resistance, capacitor.It is special due to city's electric lighting
Property, power tube 001 needs pressure-resistant 500V to 700V or more, so high input voltage foot HV has special resistance to pressure request, package pins
Aerial pressure resistance is not lower than 1KV.
TO-252-5L has five pins, is relatively good selection.It is the lead frame of general TO-252-5L referring to Fig. 2, Fig. 2
Frame structure chart.But there are following two technology barriers for the lead frame.First, it is single-chip frame, cannot close envelope twin-core
Piece；Second, connection framework Ji Dao's is intermediate third pin, is welded in heat dissipation greatly since the drain electrode of power tube directly passes through slicken solder
On Ji Dao, so third foot is exactly high input voltage foot HV, and third foot and the spacing of adjacent crus secunda and the 4th foot are both less than
0.8mm is unsatisfactory for 1KV high pressure code requirement.
In order to overcome the high-tension room between pin away from obstacle, needing will be between high input voltage foot HV and other adjacent pin
Spacing widens.Because of the limited width of TO-252-5L frame itself, the first step considers that the pin by the connection heat dissipation island great Ji is moved to side
Side is perhaps put into the first foot or is put into the 5th foot and (here, according to the usage of trade, names the first foot in order from left to right
Five feet).Second step again removes neighbouring pin, in the case where high input voltage foot HV is the first foot, by original crus secunda
Remove；In the case where high input voltage foot HV is five foot, then the 4th original foot is removed.It is left with four pins in this way,
And the spacing between high input voltage foot HV and neighbouring pin meets 1KV high pressure requirement in 2mm or so.Moreover, because removing
As soon as pin, the routing region of lower portion accordingly has more a piece of small space, can make an island Ge little Ji using this space, use
In installation current constant control chip-die.Heat dissipation great Ji island area and shape originally is constant, is still used for installation power pipe.By
This, the obstacle that dual chip cannot close envelope is overcome, and closes the packaging appearance size and general T O-252 striking resemblances of envelope；With
TO-252-3L or TO-252-5L shape only difference is that, the lead frame of innovation has four pins, rather than
Three pins, nor five pins.
It is the dual chip TO-252 lead frame structure figure of one embodiment of the invention referring to Fig. 3, Fig. 3.The lead frame packet
Multiple lead wire units 101 being connected by dowel are included, here, lead wire unit 101 uses standard TO-252 frame width, is
6.50±0.01mm.Lead wire unit 101 includes the first base island 102, the second base island 103 and four terminal pins.Wherein, the first base
Island 102 is original island heat dissipation great Ji, its shape and area uses TO-252-5L standard.It is most right positioned at lead wire unit 101
The terminal pin 4 of side is connected with the first base island 102, for example, terminal pin 4 can be used as the high input voltage foot of power tube.Second base island 103
For the Ji Dao newly founded, it is located at the end of the terminal pin 3 adjacent with terminal pin 4.Spacing between terminal pin 1,2,3 uses
TO-252-5L standard pin pitch is 1.27 ± 0.01mm；Due to a pin fewer than TO-252-5L, between terminal pin 3,4
Spacing can be twice of above-mentioned standard pin pitch, for example 2.54 ± 0.01mm.
Terminal pin 1-4 uses TO-252-5L standard pin width, is 0.50 ± 0.01mm.Draw with each on the first base island 102
Stitch uses TO-252 standard thickness, is 0.50 ± 0.01mm.The end of terminal pin 1,2,4 is equipped with the silver-plated area 104 of lead.First
Base island 102 is for installing the first chip, such as power chip；First base island 102 is relative to the predetermined height of the second base island 103 sinking one
Degree, such as 0.50mm or so.Second base island 103 is for installing the second chip, as LED constant current controls chip.
Preferably, the lateral minimum widith on the second base island 103 is, TO-252-5L standard pin pitch (1.27 ± 0.01mm) with
The sum of standard pin width (0.50 ± 0.01mm), for example 1.77mm or so.Longitudinal height on the second base island 103 can be with its transverse direction
Width is almost the same.In this way, the area on the second base island 103 about can be in 3.1mm2Left and right.
Location hole 107 is equipped on dowel 108, the diameter of location hole 107 is 1.20 ± 0.01mm.
In the example lead frame, multiple lead wire units 101 can be with single-row arrangement；It multiple rows of can also arrange, between each row
It is connected by dowel.For example, Fig. 4 shows lead wire unit 101 in the dual chip TO-252 lead frame of two rows of arrangements.
It is the dual chip TO-252 lead frame structure figure of another embodiment of the present invention referring to Fig. 5, Fig. 5.The lead frame
In, the terminal pin 1 positioned at 201 leftmost side of lead wire unit is connected with the first base island 202, and the second base island 203 is located at and 1 phase of terminal pin
The end of adjacent terminal pin 2.The lead frame is stringent left and right mirror with lead frame shown in Fig. 3, no longer superfluous here
It states.Fig. 6 shows lead wire unit 201 in the dual chip TO-252 lead frame of two rows of arrangements.
Fig. 7 is the TO-252 lead frame structure figure that one embodiment of the invention is equipped with chip, and Fig. 8 is TO- shown in Fig. 7
The cross-sectional view of 252 lead frames.As shown in Figure 7 and Figure 8, in lead wire unit 110, the first base island 102 is relative to the second base island 103
Sink a predetermined altitude h, is equipped with chip IC 1 on the first base island 102, terminal pin 4 is connected with the first base island 102；Second Ji Dao
Chip IC 2, chip IC 1 and chip IC 2 are installed to connect by bonding wire 110 with terminal pin 1-3 on 103.Chip IC 1 can be power
Chip；Chip IC 2 can control chip, its driving power chip operation for control chip, such as LED constant current.
Following table lists new conjunction envelope TO-252 of the invention and two kinds of popular relativities closed between each index of envelope encapsulation.By
It is that patch is installed that Yu Xinhe, which seals TO-252 as conjunction envelope SOP-8, high degree of automation, and cost per efficiency unit is low.Equal conditions
Under, because the new heat dissipation performance for closing envelope TO-252 is to close tetra- times of SOP-8 of envelope or more, the conducting resistance of the former internal power pipe
What is taken is bigger, and power tube cost only has a quarter of the latter.Although the new packaging cost for closing envelope TO-252 itself is than closing
SOP-8 high 50% is sealed, but is integrated, total application cost but may be also lower than closing envelope SOP-8.Generally speaking, power tube
Bigger, cost is higher, and the new cost advantage for closing envelope TO-252 is more obvious.Conversely, power tube is smaller, cost is lower, new to close envelope TO-
252 cost advantage is more unobvious.
| Close envelope SOP-8 | Close envelope DIP-8 | It is new to close envelope TO-252 | |
| Heat dissipation performance | 1 | 2 | 4 |
| Packaging cost | 1 | 2.5 | 1.5 |
| Power tube cost | 1 | 0.5 | 0.25 |
| Efficiency cost | 1 | 4 | 1 |
| Total application cost | 1 | 2~3 times | 0.4~1.2 times |
For example, if closing the power tube for using 4A600V inside envelope SOP-8, cost is 0.3 yuan；And it is changed to new
If closing envelope TO-252, then the power tube of 1A600V can be used, cost is less than 0.1 yuan.Total application cost of the latter
0.2 yuan lower than the former or so, advantage is quite obvious.But if closing the power tube that envelope SOP-8 uses 1A600V, at
Basis is originally less than 0.1 yuan；In the case where using new conjunction envelope TO-252 instead, even with the power tube of 0.5A600V
(the substantially the smallest power tube of industry), cost also wants 0.05 yuan, considers further that the new packaging cost ratio for closing envelope TO-252
Envelope SOP-8 high 50% is closed, total application cost of the two is very nearly the same.In this case, the new advantage for closing envelope TO-252 is unobvious.
Therefore, it newly closes in the especially suitable cooperation of envelope TO-252, the power tube application of high current, this application can about account for
Three to four one-tenth in LED constant current driving chip market.The fact that huge based on LED constant current driving chip market capacity, the present invention
There is positive and important meaning to more inexpensive, higher-quality continuous upgrading for LED constant current driving chip.
It is clear that invention described herein can there are many variations, this variation must not believe that deviation is of the invention
Spirit and scope.Therefore, all changes that will be apparent to those skilled in the art, are included in the culvert of the appended claims
Within the scope of lid.
Claims (8)
1. a kind of TO-252 lead frame, including multiple lead wire units being connected by dowel, the lead wire unit includes the
One Ji Dao, second Ji Dao and four terminal pin, wherein
First Ji Dao is for carrying the first chip, relative to the second Ji Dao one predetermined altitude of sinking；
First lead foot positioned at the lead wire unit leftmost side or the rightmost side is connected with the first Ji Dao；
Second Ji Dao is for carrying the second chip, positioned at the end of second terminal pin adjacent with the first lead foot；
Second, third, the spacing between the 4th terminal pin be T0-252-5L standard pin pitch, between first and second terminal pin
Spacing is twice of the standard pin pitch.
2. lead frame as described in claim 1, which is characterized in that the minimum widith of second Ji Dao is T0-252-5L
The sum of standard pin pitch and standard pin width.
3. lead frame as described in claim 1, which is characterized in that the shape and area of first Ji Dao uses T0-
252-5L standard.
4. lead frame as described in claim 1, which is characterized in that first chip is power chip, and the second chip is
LED constant current controls chip, and the first lead foot is power tube high input voltage foot.
5. a kind of semiconductor packing device, including plastic-sealed body, the lead wire unit being encapsulated within the plastic-sealed body and first,
Two chips, which is characterized in that the lead wire unit includes the first Ji Dao, second Ji Dao and four terminal pin, wherein
First Ji Dao sinks a predetermined altitude relative to the second Ji Dao, installs first chip on the first Ji Dao；
First lead foot positioned at the lead wire unit leftmost side or the rightmost side is connected with the first Ji Dao；
Second Ji Dao is located at the end of second terminal pin adjacent with the first lead foot, on the second Ji Dao described in installation
Second chip, first chip and the second chip by bonding wire with second, third, the 4th terminal pin connect；
Second, third, the spacing between the 4th terminal pin be T0-252-5L standard pin pitch, between first and second terminal pin
Spacing is twice of the standard pin pitch.
6. semiconductor packing device as claimed in claim 5, which is characterized in that the minimum widith of second Ji Dao is T0-
The sum of 252-5L standard pin pitch and standard pin width.
7. semiconductor packing device as claimed in claim 5, which is characterized in that the shape and area of first Ji Dao uses
T0-252-5L standard.
8. semiconductor packing device as claimed in claim 5, which is characterized in that first chip be power chip, second
Chip is that LED constant current controls chip, and the first lead foot is power tube high input voltage foot.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811338171.XA CN109285824A (en) | 2018-11-12 | 2018-11-12 | Dual chip TO-252 lead frame and semiconductor packing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811338171.XA CN109285824A (en) | 2018-11-12 | 2018-11-12 | Dual chip TO-252 lead frame and semiconductor packing device |
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| Publication Number | Publication Date |
|---|---|
| CN109285824A true CN109285824A (en) | 2019-01-29 |
Family
ID=65175356
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811338171.XA Pending CN109285824A (en) | 2018-11-12 | 2018-11-12 | Dual chip TO-252 lead frame and semiconductor packing device |
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| US5399905A (en) * | 1993-01-14 | 1995-03-21 | Mitsubishi Denki Kabushiki Kaisha | Resin sealed semiconductor device including multiple current detecting resistors |
| US20090212284A1 (en) * | 2008-02-22 | 2009-08-27 | Infineon Technologies Ag | Electronic device and manufacturing thereof |
| CN104051397A (en) * | 2013-03-12 | 2014-09-17 | 英飞凌科技奥地利有限公司 | Packaged device comprising non-integer lead pitches and method of manufacturing the same |
| CN106024774A (en) * | 2015-03-31 | 2016-10-12 | 英飞凌科技奥地利有限公司 | Compound semiconductor device including a sensing lead |
| CN205920964U (en) * | 2016-06-28 | 2017-02-01 | 无锡市玉祁红光电子有限公司 | Lead frame with two kinds of chips |
| CN206774530U (en) * | 2017-04-21 | 2017-12-19 | 无锡市宏湖微电子有限公司 | Lead frame for biradical island encapsulated circuit |
| CN208923111U (en) * | 2018-11-12 | 2019-05-31 | 北京模电半导体有限公司 | Dual chip TO-252 lead frame and semiconductor packing device |
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2018
- 2018-11-12 CN CN201811338171.XA patent/CN109285824A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5399905A (en) * | 1993-01-14 | 1995-03-21 | Mitsubishi Denki Kabushiki Kaisha | Resin sealed semiconductor device including multiple current detecting resistors |
| US20090212284A1 (en) * | 2008-02-22 | 2009-08-27 | Infineon Technologies Ag | Electronic device and manufacturing thereof |
| CN104051397A (en) * | 2013-03-12 | 2014-09-17 | 英飞凌科技奥地利有限公司 | Packaged device comprising non-integer lead pitches and method of manufacturing the same |
| CN106024774A (en) * | 2015-03-31 | 2016-10-12 | 英飞凌科技奥地利有限公司 | Compound semiconductor device including a sensing lead |
| CN205920964U (en) * | 2016-06-28 | 2017-02-01 | 无锡市玉祁红光电子有限公司 | Lead frame with two kinds of chips |
| CN206774530U (en) * | 2017-04-21 | 2017-12-19 | 无锡市宏湖微电子有限公司 | Lead frame for biradical island encapsulated circuit |
| CN208923111U (en) * | 2018-11-12 | 2019-05-31 | 北京模电半导体有限公司 | Dual chip TO-252 lead frame and semiconductor packing device |
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